CN107910359A - It is a kind of that there is the LDMOS device and its manufacture method for expanding E SOA regions - Google Patents
It is a kind of that there is the LDMOS device and its manufacture method for expanding E SOA regions Download PDFInfo
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- CN107910359A CN107910359A CN201711091191.7A CN201711091191A CN107910359A CN 107910359 A CN107910359 A CN 107910359A CN 201711091191 A CN201711091191 A CN 201711091191A CN 107910359 A CN107910359 A CN 107910359A
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- 238000000034 method Methods 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000000407 epitaxy Methods 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 238000003032 molecular docking Methods 0.000 claims description 13
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 238000001727 in vivo Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H01L29/7816—
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- H01L29/0684—
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- H01L29/66681—
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention relates to a kind of LDMOS device and its manufacture method for having and expanding E SOA regions, on the one hand by substrate P（10）And N-type epitaxy layer（12）Between introduce the first heavy doping P+ areas（11）, the first heavy doping P+ areas（11）To drain electrode（21）The holoe carrier that avalanche breakdown produces occurs, there is provided new leakage path；On the other hand, which causes most drain terminal hole no longer to circulate from surface, reduces and is trapped N-type epitaxy layer（12）Surface field oxide（17）In hole number, further increase the reliability of device, expand E SOA regions.
Description
Technical field
The present invention relates to a kind of LDMOS device and its manufacture method for having and expanding E-SOA regions, belong to electronic component
Technical field.
Background technology
Lateral double diffusion metal oxide field-effect transistor (LDMOS) is widely used in power management chip, power drives
It is dynamic to wait civil and military field.LDMOS has the advantages that high voltage, high-gain, low distortion, is easy to mutually compatible with planar technology.
As a kind of widely used power device, LDMOS is commonly applied under the adverse circumstances of high voltage and/or high current.And safety
Workspace (SOA) is the electric current and voltage range that power device can reliably and securely work, and i.e. may be worked out of this range
Damage device.Therefore, when designing LDMOS structure, in addition to breakdown voltage and conducting resistance, electric safety operation area
(Electrical Safe-operating-area, E-SOA) is also a key parameter for having to consider.
The content of the invention
The technical problems to be solved by the invention, which are to provide, a kind of can effectively improve having for electronic component reliability
Expand the LDMOS device in E-SOA regions.
In order to solve the above-mentioned technical problem the present invention uses following technical scheme：The present invention devises a kind of with expansion E-
The LDMOS device in SOA regions, including substrate P (10), the first heavy doping P+ areas (11), N-type epitaxy layer (12), the second heavy doping P
+ area (13), PXing Ti areas (14), heavy doping N+ areas (15), leakage stress to adulterate N+ areas (16), field oxide (17), gate oxide
(18), gate electrode (19), source electrode (20) and drain electrode (21)；Wherein, using substrate P (10) level angle as reference, the first weight
The horizontal embedded upper surface for being arranged at substrate P (10) of doping P+ areas (11), the upper surface in the first heavy doping P+ areas (11) and substrate P
(10) upper surface flush, the lower surface in the first heavy doping P+ areas (11) are located in substrate P (10), and the first heavy doping P+ areas
(11) the wherein edge of side in wherein one end docking substrate P (10)；N-type epitaxy layer (12) is arranged at the upper of substrate P (10)
Surface, the second heavy doping P+ areas (13) embed the upper surface for being arranged at N-type epitaxy layer (12), the second heavy doping P+ areas (13) vertically
Top end face and N-type epitaxy layer (12) upper surface flush, dock substrate P (10) side in the first heavy doping P+ areas (11)
The side of the end at edge, is connected to each other with the bottom in the second heavy doping P+ areas (13), and in the second heavy doping P+ areas (13) wherein
The edge of side is corresponded in side docking N-type epitaxy layer (12), the opposite side in the second heavy doping P+ areas (13) is located at N-type epitaxy layer
(12) in, on the cross section view of LDMOS device, the first heavy doping P+ areas (11) mutually hang down with the second heavy doping P+ areas (13)
Directly, L shape P+ charged regions are formed；
The embedded upper surface for being arranged at N-type epitaxy layer (12) in PXing Ti areas (14), outside the upper surface of PXing Ti areas (14) and N-type
Prolong the upper surface flush of layer (12), the wherein side of QiePXing Ti areas (14) is located at N-type extension with the second heavy doping P+ areas (13)
A side surface in layer (12) is connected to each other；Heavy doping N+ areas (15) are embedded to be arranged at PXing Ti areas (14) upper surface, heavy doping N+ areas
(15) the upper surface flush of upper surface and PXing Ti areas (14), the lower surface in heavy doping N+ areas (15) is located at PXing Ti areas (14)
In, and one be located in the second heavy doping P+ areas (13) in N-type epitaxy layer (12) is docked in the wherein side in heavy doping N+ areas (15)
Side surface；Leakage stresses to adulterate N+ areas (16) embedded upper surface for being arranged at N-type epitaxy layer (12), and leakage stresses to adulterate N+ areas (16)
Upper surface and the upper surface flush of N-type epitaxy layer (12), the lower surface that leakage stresses to adulterate N+ areas (16) are located at N-type epitaxy layer
(12) in, and leakage stresses to adulterate N+ areas (16) wherein side with docking the second heavy doping P+ areas relatively in N-type epitaxy layer (12)
(13) another lateral edges of side are connected to each other；
Field oxide (17) is arranged at the upper surface of N-type epitaxy layer (12), and gate oxide (18) is arranged at PXing Ti areas (14)
Upper surface, the embedded upper surface for being arranged at gate oxide (18) of gate electrode (19), source electrode (20) and drain electrode (21) setting
In LDMOS device upper surface, source electrode (20) while dock in heavy doping P+ areas (13) top end face and heavy doping N+ areas (15)
Surface, drain electrode (21) docking leakage stress to adulterate the upper surface of N+ areas (16).
As a preferred technical solution of the present invention：The substrate P (10) is silicon substrate.
As a preferred technical solution of the present invention：The silicon substrate is monocrystalline substrate.
As a preferred technical solution of the present invention：The first heavy doping P+ areas (11) are along LDMOS device section, water
Square upward length is to preset all kinds of scale lengths.
With above-mentioned corresponding, the present invention also technical problems to be solved be to provide it is a kind of have expand E-SOA regions
The manufacture method of LDMOS device, while electronic component reliability is ensured, can effectively improve work efficiency.
In order to solve the above-mentioned technical problem the present invention uses following technical scheme：The present invention devises a kind of with expansion E-
The manufacture method of the LDMOS device in SOA regions, includes the following steps：
Step 1. forms the first heavy doping P+ areas (11) in substrate P (10)；
Step 2. generates N-type epitaxy layer (12) in substrate P (10), ion implanting or diffuses to form PXing Ti areas (14), deep
The second heavy doping P+ areas (13) are diffuseed to form, dry oxidation forms gate oxide (18), deposit gate electrode (19)；
Step 3. ion implanting forms heavy doping N+ areas (15), leakage stresses to adulterate N+ areas (16)；
Step 4. wet-oxygen oxidation forms field oxide (17), and deposited metal forms source electrode (20) and drain electrode (21).
As a preferred technical solution of the present invention：In the step 1, the doping of the first heavy doping P+ areas (11)
Concentration is more than 1e18cm-3。
A kind of LDMOS device and its manufacture method with expansion E-SOA regions of the present invention, using above technical side
Case compared with prior art, has following technique effect：The present invention devises a kind of LDMOS devices for having and expanding E-SOA regions
Part and its manufacture method, compared with prior art, on the one hand by introducing between substrate P (10) and N-type epitaxy layer (12)
The hole current-carrying of avalanche breakdown generation occurs to drain electrode (21) for one heavy doping P+ areas (11), the first heavy doping P+ areas (11)
Son, there is provided new leakage path；On the other hand, which causes most drain terminal hole no longer to be flowed from surface
It is logical, reduce the hole number being trapped in N-type epitaxy layer (12) surface field oxide (17), further increase device can
By property, E-SOA regions are expanded.
Brief description of the drawings
Fig. 1 is common LDMOS device diagrammatic cross-section；
Fig. 2 is the designed diagrammatic cross-section with the LDMOS device for expanding E-SOA of the present invention.
Wherein, 10.P substrates, 11. first heavy doping P+ areas, 12.N type epitaxial layers, 13. second heavy doping P+ areas, 14.P types
Body area, 15. heavy doping N+ areas, 16. leakages stress to adulterate N+ areas, 17. field oxides, 18. gate oxides, 19. gate electrodes, 20. sources
Electrode, 21. drain electrodes.
Embodiment
The embodiment of the present invention is described in further detail with reference to Figure of description.
As shown in Fig. 2, the present invention devises a kind of LDMOS device for having and expanding E-SOA regions, among practical application,
Specifically include monocrystalline substrate, the first heavy doping P+ areas (11), N-type epitaxy layer (12), the second heavy doping P+ areas (13), p-type body
Area (14), heavy doping N+ areas (15), leakage stress to adulterate N+ areas (16), field oxide (17), gate oxide (18), gate electrode
(19), source electrode (20) and drain electrode (21)；In practical application, for the first heavy doping P+ areas (11), first is further designed
Heavy doping P+ areas (11) are to preset all kinds of scale lengths along the length in LDMOS device section, horizontal direction, that is, design a variety of rulers
The first very little heavy doping P+ areas (11)；Wherein, using monocrystalline substrate level angle as reference, the first heavy doping P+ areas (11) are horizontal
The embedded upper surface for being arranged at monocrystalline substrate, the upper surface in the first heavy doping P+ areas (11) and the upper surface phase of monocrystalline substrate
Concordantly, the lower surface in the first heavy doping P+ areas (11) is located in monocrystalline substrate, and wherein the one of the first heavy doping P+ areas (11)
The edge of wherein side in end docking monocrystalline substrate；N-type epitaxy layer (12) is arranged at the upper surface of monocrystalline substrate, the second weight
Doping P+ areas (13) embeds the upper surface for being arranged at N-type epitaxy layer (12), the top end face in the second heavy doping P+ areas (13) vertically
With the upper surface flush of N-type epitaxy layer (12), the end of monocrystalline substrate one side edge is docked in the first heavy doping P+ areas (11)
The side in portion, is connected to each other with the bottom in the second heavy doping P+ areas (13), and wherein side docking N in the second heavy doping P+ areas (13)
The edge of side is corresponded on type epitaxial layer (12), the opposite side in the second heavy doping P+ areas (13) is located in N-type epitaxy layer (12),
On the cross section view of LDMOS device, the first heavy doping P+ areas (11) are mutually perpendicular to the second heavy doping P+ areas (13), form L-shaped
Shape P+ charged regions.
The embedded upper surface for being arranged at N-type epitaxy layer (12) in PXing Ti areas (14), outside the upper surface of PXing Ti areas (14) and N-type
Prolong the upper surface flush of layer (12), the wherein side of QiePXing Ti areas (14) is located at N-type extension with the second heavy doping P+ areas (13)
A side surface in layer (12) is connected to each other；Heavy doping N+ areas (15) are embedded to be arranged at PXing Ti areas (14) upper surface, heavy doping N+ areas
(15) the upper surface flush of upper surface and PXing Ti areas (14), the lower surface in heavy doping N+ areas (15) is located at PXing Ti areas (14)
In, and one be located in the second heavy doping P+ areas (13) in N-type epitaxy layer (12) is docked in the wherein side in heavy doping N+ areas (15)
Side surface；Leakage stresses to adulterate N+ areas (16) embedded upper surface for being arranged at N-type epitaxy layer (12), and leakage stresses to adulterate N+ areas (16)
Upper surface and the upper surface flush of N-type epitaxy layer (12), the lower surface that leakage stresses to adulterate N+ areas (16) are located at N-type epitaxy layer
(12) in, and leakage stresses to adulterate N+ areas (16) wherein side with docking the second heavy doping P+ areas relatively in N-type epitaxy layer (12)
(13) another lateral edges of side are connected to each other.
Field oxide (17) is arranged at the upper surface of N-type epitaxy layer (12), and gate oxide (18) is arranged at PXing Ti areas (14)
Upper surface, the embedded upper surface for being arranged at gate oxide (18) of gate electrode (19), source electrode (20) and drain electrode (21) setting
In LDMOS device upper surface, source electrode (20) while dock in heavy doping P+ areas (13) top end face and heavy doping N+ areas (15)
Surface, drain electrode (21) docking leakage stress to adulterate the upper surface of N+ areas (16).
Compared with common LDMOS device as shown in Figure 1, innovation of the present invention is that the introducing in vivo in device is heavily doped
Miscellaneous N+ areas (15), and be connected with the second heavy doping P+ areas (13).
The advantage of the inventive structure is embodied in when avalanche breakdown occurs for device, due to the presence in heavy doping N+ areas (15),
Hole leakage current is transferred in vivo by the surface of device, and heavy doping N+ areas (15) are such that internal leakage path resistance is relatively low,
So as to improve the electric safety operation area (E-SOA) of device.The change of leakage path make it that the heat by field oxide (17) capture carries
Flow sub- number of cavities to reduce, further improve the reliability of device, expand the safety operation area of device.
The advantage of the inventive structure is also embodied in heavy doping N+ areas (15) and the second heavy doping P+ areas of low-resistance, heavy doping
(13) it is connected, reduces the current potential in heavy doping N+ areas (15), N-type epitaxy layer (12) exhausts when strengthening resistance state, improve N-type
The doping concentration of epitaxial layer (12), improves the compromise between device electric breakdown strength and conducting resistance.
It is of the invention into one for the LDMOS device designed by the present invention with expansion E-SOA regions with above-mentioned corresponding
Walk and devise the manufacture method with the LDMOS device for expanding E-SOA regions, in practical application, specifically comprise the following steps：
Step 1. forms the first heavy doping P+ areas (11) in substrate P (10), wherein, first heavy doping P+ area (11) are mixed
Miscellaneous concentration is more than 1e18cm-3.
Step 2. generates N-type epitaxy layer (12) in substrate P (10), ion implanting or diffuses to form PXing Ti areas (14), deep
The second heavy doping P+ areas (13) are diffuseed to form, dry oxidation forms gate oxide (18), deposit gate electrode (19).
Step 3. ion implanting forms heavy doping N+ areas (15), leakage stresses to adulterate N+ areas (16).
Step 4. wet-oxygen oxidation forms field oxide (17), and deposited metal forms source electrode (20) and drain electrode (21).
Above-mentioned technical proposal is designed to have the LDMOS device and its manufacture method for expanding E-SOA regions, with the prior art
Compare, on the one hand by introducing the first heavy doping P+ areas (11), first weight between substrate P (10) and N-type epitaxy layer (12)
Adulterate the holoe carrier that avalanche breakdown generation occurs to drain electrode (21) for P+ areas (11), there is provided new leakage path；It is another
Aspect, the new leakage path cause most drain terminal hole no longer to circulate from surface, reduce and be trapped N-type epitaxy layer
(12) the hole number in surface field oxide (17), further increases the reliability of device, expands E-SOA regions.
Embodiments of the present invention are explained in detail above in conjunction with attached drawing, but the present invention is not limited to above-mentioned implementation
Mode, within the knowledge of a person skilled in the art, can also be on the premise of present inventive concept not be departed from
Make various variations.
Claims (6)
1. a kind of have the LDMOS device for expanding E-SOA regions, it is characterised in that：Including substrate P (10), the first heavy doping P+
Area (11), N-type epitaxy layer (12), the second heavy doping P+ areas (13), PXing Ti areas (14), heavy doping N+ areas (15), leakage stress to adulterate
N+ areas (16), field oxide (17), gate oxide (18), gate electrode (19), source electrode (20) and drain electrode (21)；Wherein, with P
Substrate (10) level angle is reference, the horizontal embedded upper surface for being arranged at substrate P (10) in the first heavy doping P+ areas (11), first
The upper surface in heavy doping P+ areas (11) and the upper surface flush of substrate P (10), the lower surface position in the first heavy doping P+ areas (11)
In substrate P (10), and the wherein edge of side in wherein one end docking substrate P (10) in the first heavy doping P+ areas (11)；N-type
Epitaxial layer (12) is arranged at the upper surface of substrate P (10), and the second heavy doping P+ areas (13) are embedded vertically to be arranged at N-type epitaxy layer
(12) upper surface, the top end face in the second heavy doping P+ areas (13) and the upper surface flush of N-type epitaxy layer (12), the first weight
Adulterate the side for the end that substrate P (10) one side edge is docked on P+ areas (11), the bottom phase with the second heavy doping P+ areas (13)
Docking, and the edge of side is wherein corresponded in the second heavy doping P+ areas (13) in side docking N-type epitaxy layer (12), second is heavily doped
The opposite side of miscellaneous P+ areas (13) is located in N-type epitaxy layer (12), on the cross section view of LDMOS device, the first heavy doping P+ areas
(11) it is mutually perpendicular to the second heavy doping P+ areas (13), forms L shape P+ charged regions；
The embedded upper surface for being arranged at N-type epitaxy layer (12) in PXing Ti areas (14), the upper surface of PXing Ti areas (14) and N-type epitaxy layer
(12) upper surface flush, the wherein side of QiePXing Ti areas (14) are located at N-type epitaxy layer with the second heavy doping P+ areas (13)
(12) side surface in is connected to each other；Heavy doping N+ areas (15) are embedded to be arranged at PXing Ti areas (14) upper surface, heavy doping N+ areas
(15) the upper surface flush of upper surface and PXing Ti areas (14), the lower surface in heavy doping N+ areas (15) is located at PXing Ti areas (14)
In, and one be located in the second heavy doping P+ areas (13) in N-type epitaxy layer (12) is docked in the wherein side in heavy doping N+ areas (15)
Side surface；Leakage stresses to adulterate N+ areas (16) embedded upper surface for being arranged at N-type epitaxy layer (12), and leakage stresses to adulterate N+ areas (16)
Upper surface and the upper surface flush of N-type epitaxy layer (12), the lower surface that leakage stresses to adulterate N+ areas (16) are located at N-type epitaxy layer
(12) in, and leakage stresses to adulterate N+ areas (16) wherein side with docking the second heavy doping P+ areas relatively in N-type epitaxy layer (12)
(13) another lateral edges of side are connected to each other；
Field oxide (17) is arranged at the upper surface of N-type epitaxy layer (12), and gate oxide (18) is arranged at the upper of PXing Ti areas (14)
Surface, the embedded upper surface for being arranged at gate oxide (18) of gate electrode (19), source electrode (20) and drain electrode (21) are arranged at
LDMOS device upper surface, source electrode (20) while docks heavy doping P+ areas (13) top end face and heavy doping N+ areas (15) upper table
Face, drain electrode (21) docking leakage stress to adulterate the upper surface of N+ areas (16).
2. a kind of according to claim 1 have the LDMOS device for expanding E-SOA regions, it is characterised in that：The substrate P
(10) it is silicon substrate.
3. a kind of according to claim 2 have the LDMOS device for expanding E-SOA regions, it is characterised in that：The silicon substrate
For monocrystalline substrate.
4. a kind of according to claim 1 have the LDMOS device for expanding E-SOA regions, it is characterised in that：First weight
It is to preset all kinds of scale lengths that P+ areas (11), which are adulterated, along the length in LDMOS device section, horizontal direction.
It is 5. a kind of for the manufacturer described in any one in Claims 1-4 with the LDMOS device for expanding E-SOA regions
Method, it is characterised in that include the following steps：
Step 1. forms the first heavy doping P+ areas (11) in substrate P (10)；
Step 2. generates N-type epitaxy layer (12) in substrate P (10), ion implanting or diffuses to form PXing Ti areas (14), deep diffusion
The second heavy doping P+ areas (13) are formed, dry oxidation forms gate oxide (18), deposit gate electrode (19)；
Step 3. ion implanting forms heavy doping N+ areas (15), leakage stresses to adulterate N+ areas (16)；
Step 4. wet-oxygen oxidation forms field oxide (17), and deposited metal forms source electrode (20) and drain electrode (21).
A kind of 6. manufacture method with the LDMOS device for expanding E-SOA regions according to claim 5, it is characterised in that：
In the step 1, the doping concentration of the first heavy doping P+ areas (11) is more than 1e18cm-3。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711091191.7A CN107910359A (en) | 2017-11-08 | 2017-11-08 | It is a kind of that there is the LDMOS device and its manufacture method for expanding E SOA regions |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711091191.7A CN107910359A (en) | 2017-11-08 | 2017-11-08 | It is a kind of that there is the LDMOS device and its manufacture method for expanding E SOA regions |
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| CN107910359A true CN107910359A (en) | 2018-04-13 |
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ID=61842691
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0802567A2 (en) * | 1996-04-15 | 1997-10-22 | Denso Corporation | Semiconductor device and manufacturing method thereof |
| US20110101454A1 (en) * | 2009-11-05 | 2011-05-05 | Hisao Ichijo | Semiconductor device and method for producing the same |
| CN102412162A (en) * | 2011-11-23 | 2012-04-11 | 上海华虹Nec电子有限公司 | Method for improving NLDMOS breakdown voltage |
| CN102623506A (en) * | 2012-04-10 | 2012-08-01 | 中国科学院微电子研究所 | High-reliability SOI LDMOS power device |
| CN106531802A (en) * | 2016-04-08 | 2017-03-22 | 长沙理工大学 | Low on-resistance novel high-voltage SJ power device |
| CN106684150A (en) * | 2016-11-10 | 2017-05-17 | 西安阳晓电子科技有限公司 | LDMOS with low conduction resistance and relatively low total gate charge and preparation method for LDMOS |
-
2017
- 2017-11-08 CN CN201711091191.7A patent/CN107910359A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0802567A2 (en) * | 1996-04-15 | 1997-10-22 | Denso Corporation | Semiconductor device and manufacturing method thereof |
| US20110101454A1 (en) * | 2009-11-05 | 2011-05-05 | Hisao Ichijo | Semiconductor device and method for producing the same |
| CN102412162A (en) * | 2011-11-23 | 2012-04-11 | 上海华虹Nec电子有限公司 | Method for improving NLDMOS breakdown voltage |
| CN102623506A (en) * | 2012-04-10 | 2012-08-01 | 中国科学院微电子研究所 | High-reliability SOI LDMOS power device |
| CN106531802A (en) * | 2016-04-08 | 2017-03-22 | 长沙理工大学 | Low on-resistance novel high-voltage SJ power device |
| CN106684150A (en) * | 2016-11-10 | 2017-05-17 | 西安阳晓电子科技有限公司 | LDMOS with low conduction resistance and relatively low total gate charge and preparation method for LDMOS |
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