CN107910310A - A kind of multi-chip fan-out package structure and its method for packing - Google Patents

A kind of multi-chip fan-out package structure and its method for packing Download PDF

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Publication number
CN107910310A
CN107910310A CN201711454534.1A CN201711454534A CN107910310A CN 107910310 A CN107910310 A CN 107910310A CN 201711454534 A CN201711454534 A CN 201711454534A CN 107910310 A CN107910310 A CN 107910310A
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China
Prior art keywords
chips
chip
wiring layer
metal bumps
coating film
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CN201711454534.1A
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Chinese (zh)
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CN107910310B (en
Inventor
张爱兵
陈栋
孙超
张黎
陈锦辉
赖志明
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Jiangyin Changdian Advanced Packaging Co Ltd
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Jiangyin Changdian Advanced Packaging Co Ltd
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Priority to CN201711454534.1A priority Critical patent/CN107910310B/en
Publication of CN107910310A publication Critical patent/CN107910310A/en
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Publication of CN107910310B publication Critical patent/CN107910310B/en
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A kind of multi-chip fan-out package structure of the present invention and its method for packing, belong to technical field of semiconductor encapsulation.It include with the A chips of A die metal bumps, wiring layer, A chips coating film and with the B chips of B die metal bumps, wiring layer, B chip coating films again, B chips are arranged at A Chip Vertical upper areas, B chips exterior lateral area sets perforation, filling metal charge, A chips and B chips, metal charge, wiring layer are filled in perforation, wiring layer completes signal interconnection again by coating.Passivation protection layer and metal connecting piece are set above the wiring layer again, generate final packaging body.The present invention improves the reliability of product and reduces product cost.

Description

A kind of multi-chip fan-out package structure and its method for packing
Technical field
The present invention relates to a kind of multi-chip fan-out package structure and its method for packing, belongs to semiconductor packaging neck Domain.
Background technology
With the development of electronic technology, semiconductor packages tends to high density, multi-functional, low-power consumption, the direction minimized Development, in order to meet the systemic-function of product more sophisticated, the integrated encapsulation technology of multi-chip interconnection has obtained faster development. The multi-chip package scheme of mainstream has the following two kinds at present：
1. use SIP encapsulation schemes：
A. multiple chips 103 are subjected to horizontal Tile distribution, chip 103 passes through weld tabs to substrate 101（Fig. 1-1）；
B. multiple chips 103 are subjected to vertical stacking arrangement, bottom chip 103 passes through weld tabs to substrate, remaining chip 103 Substrate 101 is connected to by routing technique（Fig. 1-2）.
Realize that the signal between chip 103 and chip 103 is interconnected by 101 internal wiring of substrate, it is logical to multiple chips 103 Cross filler material 102 to carry out underfill and carry out plastic packaging protection to it by plastic packaging material 104, this module is integrally finally welded to Printed circuit board (PCB), to realize that the interconnection of product integrates.Need to transfer by the wiring of multilayer in the program to realize between chip Interconnection, the problem of and substrate metal layer and medium thickness are thicker, usual presence signal transmission delay；And due to adding base Plate realizes that the interconnection of chip chamber integrates, and packaging cost is of a relatively high.
2. using fan-out-type interconnection scheme, multi-chip 201 is subjected to horizontal Tile distribution, and will using covering material 202 Chip 201 carries out cladding and forms new silicon wafer carrier, this new silicon wafer carrier is connected up and bump technology again, is ultimately formed Packaging body（Fig. 2）, this packaging body can be welded direct to printed circuit board (PCB).The program is due to eliminating substrate portion, contra 1 cost of case is relatively low, and employs wafer scale technique, and product routing capabilities are stronger, and chip interconnection paths are shorter, has more preferable Electric property.But the program still suffers from following problem：
A. chip can only horizontal arrangement, chip fan-out area is larger, causes final package dimension larger, every wafer level packaging body Negligible amounts, add product cost to a certain degree；
B. line layer and convex block are grown directly upon chip surface, since covering material and chip are deposited in the technical process such as connecting up again Larger stress can be produced in the unmatched problems of CTE, technical process, easily leads to chip-pad area or chip surface protection Layer produces the problems such as crack；
C. chip is Know good die（Known good chip；Before operation, bad core can be gone out by craft screenings such as tests Piece, what is used in technical process has all been chip）, but connect up directly grown above chip again, when metal, wiring layer is more again During layer wiring, causing the good chip in part, there are a certain number of yield loss.
The content of the invention
It is an object of the invention to overcome the shortcomings of above-mentioned encapsulation scheme, there is provided a kind of multi-chip fan-out package structure and Its method for packing, to improve the reliability of product and reduce product cost.
What the present invention was realized in：
A kind of multi-chip fan-out package structure of the present invention, it includes A chips, the A that front sets several A die metal bumps Chip coating film and B chips, B chip coating films with several B die metal bumps, the B chips are arranged on A chips Vertical direction region, the A chips have several, and the B chips have several；
The A die metal bumps side sets wiring layer, and the wiring layer horizontal extension is simultaneously selective discontinuous, and A chips lead to A die metal bumps are crossed to be connected with wiring layer；
The A chips coating film protects A chips and its A die metal bumps, wiring layer cladding, the upper surface of wiring layer and A The upper surface flush of chip coating film；
The upper surface of the wiring layer and the upper surface covering coating film of A chip coating films,
The B beneath chips set load film, and B chips are completed to be fixedly connected with coating film by load film；
The B chips coating film cladding B chips and its B die metal bumps, expose the top of B die metal bumps；
The exterior lateral areas of the B chips sets cladding perforation, and the bottom for coating perforation is gone directly the upper surface of wiring layer, cladding perforation Interior filling brazing metal, the B die metal bumps top are flushed with the brazing metal top of cladding perforation filling,
The B chips coating film, B die metal bumps above the brazing metal of cladding perforation filling with setting wiring layer again, institute State again the metal welding that wiring layer horizontal extension is simultaneously selective discontinuous, and the A chips and B chips pass through filling in cladding perforation Material, wiring layer, wiring layer completes signal interconnection again；
Passivation protection layer and metal connecting piece are set above the wiring layer again.
Alternatively, the A die metal bumps material is Sn or CuSn or CuNiSn or CuNiSnAg.
Alternatively, the material of the B die metal bumps is Cu or CuSn or CuNiSn or CuNiSnAg.
Alternatively, the thickness of the B die metal bumps is 5~100um.
Alternatively, the thickness of the B chips is 50~200um.
Alternatively, the material of the brazing metal of the cladding perforation filling is Sn or CuSn or CuSnAg.
Alternatively, the depth of the cladding perforation is 150~400um.
Alternatively, the metal connecting piece includes but not limited to soldered ball, welding block.
A kind of method for packing of multi-chip fan-out package structure of the present invention, it realizes that process is as follows：
Step 1, by wafer scale bump technology, A die metal bumps, the material of the A die metal bumps are grown in A chip surfaces Matter is Sn or CuSn or CuNiSn or CuNiSnAg, its top is equipped with soldered ball or welding block；
Step 2, by wafer scale bump technology, B die metal bumps, the material of the B die metal bumps are grown in B chip surfaces Expect that for Cu or CuSn or CuNiSn or CuNiSnAg, its thickness range be 5~100um；
Step 3, ordinary silicon wafer is taken to be cleaned；
Step 4, coating film being formed by press mold or Shooting Technique in silicon chip crystal column surface, the material of coating film is moulding compound, its Thickness range is 25~150um；
Step 5, wafer scale wiring technique is carried out in cladding film surface, forms wiring layer；
Step 6, by Flip Chip Bond Technique, by the A flip-chips with A die metal bumps to wiring layer；
Step 7, the wafer that upside-down mounting is had to A chips carries out plastic packaging protection by A chips coating film；
Step 8, using grinding technique, the silicon of this wafer rear is removed, retains coating film, A chips and its A chip metals Convex block, forms new silicon wafer carrier；
Step 9, using load technique, B chip of the new crystal column surface formal dress with B die metal bumps, B chips pass through dress herein Piece film is fixedly connected with coating film；
Step 10, by plastic packaging or press mold technique, B die metal bumps B chips upward and line layer is made to be coated by B chips Film coats completely；
Step 11, form cladding by drilling technology, the B chips coating film of the exterior lateral area of the B chips above wiring layer and wear Hole, and will be coated in perforation and be filled up completely with brazing metal by way of filling out ball or solder printing in cladding perforation；
Step 12, using flatening process, the filling brazing metal coated in perforation is thrown and is put down, while it is convex to expose B chip metals The top of block；
Step 13, B chips coating film, expose top B die metal bumps and cladding perforation filling brazing metal top Portion grows wiring layer again by wafer scale wiring technique；
Step 14, layer protection is being passivated above wiring layer again, and is growing soldered ball or welding block, generating final packaging body.
Alternatively, the A chip bottoms are bottom filler.
Beneficial effect
The beneficial effects of the invention are as follows：
1) fan-out package mode is employed, is in vertical distribution between chip, can greatly reduce the size of final encapsulation body, Increase the packaging body quantity of every wafer, so as to effectively reduce product cost；
2) the module chips pad and wiring layer, all transferred again by metal coupling between wiring layer and complete electrical property and connect, The metal coupling can effectively by product connect up again or bump technology in the stress that produces shifted, so as to effectively protect The regions such as chip bonding pad are protected, improve the mechanical property of product；The module ensure that due to shorter interconnection transmission path at the same time The splendid electric property of product；
3）The multi-chip fan-out package structure of the present invention employs TMV（Plastic packaging material perforation/cladding material perforation）+RDL（Cloth again Line）+Flipchip bump（Flip chip bonding）Module realize interconnection of multiple chips between two and three dimensions；
4）When chip interconnection need by multiple layer metal wiring layer is transferred again when, can be effectively by certain several layers of metal cloth again Line layer is designed in the RDL of TMV+RDL+Flipchip bump modules, due to RDL in the module（Connect up again）For Know good RDL（Known good line layer；Before operation, bad line layer can be gone out by craft screenings such as AOI, core can have been avoided Piece is attached to bad line layer）, the yield loss of good die can be effectively reduced；
5）TMV is due to the more difficult control of technique, its surface is it is difficult to ensure that planarization；By by metal coupling and TMV（Plastic packaging material is worn Hole/cladding material perforation）Planarized together so that subsequent metal wiring layer or the technique that protective layer etc. is related to spin coating again again Easily operation and at the same time obtain more preferable yield quality.
Brief description of the drawings
Fig. 1-1, Fig. 1-2 and Fig. 2 are the schematic diagram of traditional multi-chip fan-out package structure；
Fig. 3 is a kind of schematic diagram of the embodiment of multi-chip fan-out package structure of the present invention；
Fig. 3 A to Fig. 3 N are the technical process schematic diagram of the method for packing of Fig. 3 embodiments；
Fig. 4 is a kind of schematic diagram of another embodiment of multi-chip fan-out package structure of the present invention；
Wherein：
Coating film 301
A chips 302A
A chip 302A1, A chips 302A2
A die metal bumps 303
Wiring layer 304
Cladding perforation filling metal charge 305
Load film 306
B chips 302B
B chip 302B1, B chips 302B2
B die metal bumps 307
Wiring layer 308 again
Passivation layer protection 309
Solder bumps 310
A chips coating film 311
B chips coating film 312.
Embodiment
The present invention is described more fully hereinafter with reference to attached drawing now, example the invention is shown in the accompanying drawings Property embodiment, so that the disclosure fully conveys the scope of the present invention to those skilled in the art.However, the present invention can be with It is embodied in many different forms, and should not be construed as limited to embodiments set forth here.
Referring to Fig. 3, a kind of multi-chip fan-out package structure of the present invention, the front of A chips 302A sets several A chips Metal coupling 303, the A die metal bumps 303 are arranged in array or arrange according to design requirement.A die metal bumps 303 Material is Sn or CuSn or CuNiSn or CuNiSnAg.Wiring layer 304 is arranged on the A die metal bumps 303 1 of A chips 302A Side, horizontal extension.A chips 302A is connected by A die metal bumps 303 with wiring layer 304, and the material of wiring layer 304 is Cu Or CuCr.Transferred between the chip bonding pad and wiring layer 304 of A chips 302A by metal coupling and complete electrical property connection, the gold Belong to convex block can effectively by product connect up again or bump technology in the stress that produces shifted, so as to be effectively protected core The regions such as piece pad, improve the mechanical property of product；The module ensure that product due to shorter interconnection transmission path at the same time Splendid electric property.
A chip 302A and its A die metal bumps 303, wiring layer 304 are coated protection by A chips coating film 311, wiring The upper surface of layer 304 and the upper surface flush of A chips coating film 311.Usually, the material of A chips coating film 311 is moulding compound Or the combination of moulding compound and bottom filler.
The upper surface of wiring layer 304 and the upper surface covering coating film 301 of A chips coating film 311, usually, coating film 301 material is moulding compound, its thickness range is 25~150um.
A chip 302A vertical directions region is provided with B chips 302B, the B chip of several B die metal bumps 307 The thickness range of 302B is 50~200um.B die metal bumps 307 are arranged in array or arrange according to design requirement.The B The material of die metal bumps 307 is Cu or CuSn or CuNiSn or CuNiSnAg, its thickness range is 5~100um.B chips The load film 306 that thickness range is 15~50um is set below 302B, and B chips 302B is completed by load film 306 and coating film 301 are fixedly connected.Fan-out package mode is employed, is in vertical distribution between A chip 302A and B chips 302B, Ke Yiji The size of big reduction final encapsulation body, increases the packaging body quantity of every wafer, so as to effectively reduce product cost.
Material coats B chip 302B and its B die metal bumps 307 for the B chips coating film 312 of moulding compound completely, Expose the top of B die metal bumps 307.
The exterior lateral area of B chips 302B sets cladding perforation, and the bottom for coating perforation is gone directly the upper surface of wiring layer 304. The depth of the cladding perforation is 150~400um.The cladding perforation filling metal charge 305 of filling brazing metal in cladding perforation, Brazing metal is such as：Sn or CuSn or CuSnAg.The top of B die metal bumps 307 and 305 tops of cladding perforation filling metal charge are neat Flat, the wiring layer again 308 that material is Cu or CuCr is placed in B chips coating film 312, B die metal bumps 307 and cladding perforation and fills out Fill the top of metal charge 305, and horizontal extension.A chips 302A and B chips 302B is by coating perforate filling metal charge 305, wiring Layer 304, again wiring layer 308 complete signal interconnection.It is convex by metal between B chips 302B chips pad and again wiring layer 308 Electrical property connection is completed in block switching, the metal coupling can effectively by product connect up again or bump technology in the stress that produces Shifted, so as to be effectively protected the regions such as chip bonding pad, improve the mechanical property of product；The module is due to shorter at the same time Interconnection transmission path, ensure that the splendid electric property of product.
The top of wiring layer 308 sets passivation protection layer 309 and metal coupling 310 again, generates final packaging body.
The multi-chip fan-out package structure of the present invention employs TMV（Plastic packaging material perforation/cladding material perforation）+RDL（Cloth again Line）+Flipchip bump（Flip chip bonding）Module realize interconnection of multiple chips between two and three dimensions.
A kind of multi-chip fan-out package structure of the present invention and its method for packing realize that process is as follows：
Step 1, as shown in Figure 3A, by wafer scale bump technology, the growth A die metal bumps 303 on A chip 302A surfaces, The material of the A die metal bumps 303 is Sn or CuSn or CuNiSn or CuNiSnAg, its top is equipped with soldered ball or welding block.
Step 2, as shown in Figure 3B, by wafer scale bump technology, B die metal bumps are grown on B chip 302B surfaces 307.The material of the B die metal bumps 307 is Cu or CuSn or CuNiSn or CuNiSnAg, its thickness range for 5~ 100um。
Step 3, as shown in Figure 3 C, ordinary silicon wafer 30 is taken to be cleaned.
Step 4, as shown in Figure 3D, coating film 301 is formed by press mold or Shooting Technique on 30 surface of silicon chip wafer.Cladding The material of film 301 is moulding compound, its thickness range is 25~150um.
Step 5, as shown in FIGURE 3 E, wafer scale wiring technique is carried out on 301 surface of coating film, forms wiring layer 304.
Step 6, as illustrated in Figure 3 F, by Flip Chip Bond Technique, by the A chip 302A upside-down mountings with A die metal bumps 303 To wiring layer 304.
Step 7, as shown in Figure 3 G, the wafer that upside-down mounting is had to A chips 302A carries out plastic packaging guarantor by A chips coating film 311 Shield, usually, A chip bottoms can increase underfill material protection to replace the plastic packaging of bottom to protect.
Step 8, as shown in figure 3h, using grinding technique, the silicon of this wafer rear is removed, reservation coating film 301, A chip 302A and its A die metal bumps 303, form new silicon wafer carrier.
Step 9, as shown in fig. 31, using load technique, new crystal column surface formal dress is with B die metal bumps 307 herein B chips 302B, B chip 302B be fixedly connected by load film 306 with coating film 301.
Step 10, as shown in figure 3j, by plastic packaging or press mold technique, the B chips of B die metal bumps 307 upward are made 302B and line layer 304 are coated completely by B chips coating film 312.
Step 11, as shown in Fig. 3 K, by drilling technology, the exterior lateral area of the B chips 302B above wiring layer 304 B chips coating film 312 forms cladding perforation, and cladding is perforated filling metal charge 305 by way of filling out ball or solder printing It will be filled up completely in cladding perforation.
Step 12, as shown in figure 3l, using flatening process, cladding perforation filling metal charge 305 is thrown flat, is exposed at the same time The top of B die metal bumps 307.By the way that B die metal bumps 307 are carried out together with cladding perforation filling metal charge 305 Planarization so that the technique that follow-up wiring layer again or again protective layer etc. are related to spin coating is easier operation, and obtains at the same time more preferable Yield quality.
Step 13, as shown in fig.3m, B chips coating film 312, expose top B die metal bumps 307 and cladding 305 top of perforation filling metal charge grows wiring layer 308 again by wafer scale wiring technique.
Step 14, as shown in Fig. 3 N, protected being passivated layer 309 above wiring layer 308 again, and grow soldered ball or welding block 310, generate final packaging body.
A kind of multi-chip fan-out package structure of the present invention and its method for packing are not limited to above preferred embodiment, such as：Can With setting and A chips several A chip 302A1, A chips 302A2 arranged in parallel etc., can set and B chip parallels Several B chip 302B1, B chips 302B2 of row etc., as shown in Figure 4.In addition, the bottom of A chips 302A with bottom filler come Protection, to replace the plastic packaging of bottom to protect.
Therefore without departing from the spirit and scope of the present invention, the technology according to the present invention is real by any those skilled in the art Any modification, equivalent variations and the modification that confrontation above example is made, each fall within the protection that the claims in the present invention are defined In the range of.

Claims (10)

1. a kind of multi-chip fan-out package structure, it is characterised in that it includes front and sets several A die metal bumps A chips, A chips coating film and B chips, B chip coating films with several B die metal bumps, the B chips are arranged on The vertical direction region of A chips, the A chips have several, and the B chips have several；
The A die metal bumps side sets wiring layer, and the wiring layer horizontal extension is simultaneously selective discontinuous, and A chips lead to A die metal bumps are crossed to be connected with wiring layer；
The A chips coating film protects A chips and its A die metal bumps, wiring layer cladding, the upper surface of wiring layer and A The upper surface flush of chip coating film；
The upper surface of the wiring layer and the upper surface covering coating film of A chip coating films,
The B beneath chips set load film, and B chips are completed to be fixedly connected with coating film by load film；
The B chips coating film cladding B chips and its B die metal bumps, expose the top of B die metal bumps；
The exterior lateral areas of the B chips sets cladding perforation, and the bottom for coating perforation is gone directly the upper surface of wiring layer, cladding perforation Interior filling brazing metal, the B die metal bumps top are flushed with the brazing metal top of cladding perforation filling,
The B chips coating film, B die metal bumps above the brazing metal of cladding perforation filling with setting wiring layer again, institute State again the metal welding that wiring layer horizontal extension is simultaneously selective discontinuous, and the A chips and B chips pass through filling in cladding perforation Material, wiring layer, wiring layer completes signal interconnection again；
Passivation protection layer and metal connecting piece are set above the wiring layer again.
2. multi-chip fan-out package structure according to claim 1, it is characterised in that the A die metal bumps material Expect for Sn or CuSn or CuNiSn or CuNiSnAg.
3. multi-chip fan-out package structure according to claim 1, it is characterised in that the B die metal bumps Material is Cu or CuSn or CuNiSn or CuNiSnAg.
4. multi-chip fan-out package structure according to claim 1, it is characterised in that the B die metal bumps Thickness is 5~100um.
5. multi-chip fan-out package structure according to claim 1, it is characterised in that the thickness of the B chips is 50 ~200um.
6. multi-chip fan-out package structure according to claim 1, it is characterised in that the gold of the cladding perforation filling The material for belonging to solder is Sn or CuSn or CuSnAg.
7. multi-chip fan-out package structure according to claim 1, it is characterised in that it is described cladding perforation depth be 150~400um.
8. multi-chip fan-out package structure according to claim 1, it is characterised in that the metal connecting piece include but It is not limited to soldered ball, welding block.
9. a kind of method for packing of multi-chip fan-out package structure, it realizes that process is as follows：
Step 1, by wafer scale bump technology, A die metal bumps, the material of the A die metal bumps are grown in A chip surfaces Matter is Sn or CuSn or CuNiSn or CuNiSnAg, its top is equipped with soldered ball or welding block；
Step 2, by wafer scale bump technology, B die metal bumps, the material of the B die metal bumps are grown in B chip surfaces Expect that for Cu or CuSn or CuNiSn or CuNiSnAg, its thickness range be 5~100um；
Step 3, ordinary silicon wafer is taken to be cleaned；
Step 4, coating film being formed by press mold or Shooting Technique in silicon chip crystal column surface, the material of coating film is moulding compound, its Thickness range is 25~150um；
Step 5, wafer scale wiring technique is carried out in cladding film surface, forms wiring layer；
Step 6, by Flip Chip Bond Technique, by the A flip-chips with A die metal bumps to wiring layer；
Step 7, the wafer that upside-down mounting is had to A chips carries out plastic packaging protection by A chips coating film；
Step 8, using grinding technique, the silicon of this wafer rear is removed, retains coating film, A chips and its A chip metals Convex block, forms new silicon wafer carrier；
Step 9, using load technique, B chip of the new crystal column surface formal dress with B die metal bumps, B chips pass through dress herein Piece film is fixedly connected with coating film；
Step 10, by plastic packaging or press mold technique, B die metal bumps B chips upward and line layer is made to be coated by B chips Film coats completely；
Step 11, form cladding by drilling technology, the B chips coating film of the exterior lateral area of the B chips above wiring layer and wear Hole, and will be coated in perforation and be filled up completely with brazing metal by way of filling out ball or solder printing in cladding perforation；
Step 12, using flatening process, the filling brazing metal coated in perforation is thrown and is put down, while it is convex to expose B chip metals The top of block；
Step 13, B chips coating film, expose top B die metal bumps and cladding perforation filling brazing metal top Portion grows wiring layer again by wafer scale wiring technique；
Step 14, layer protection is being passivated above wiring layer again, and is growing soldered ball or welding block, generating final packaging body.
10. the method for packing of multi-chip fan-out package structure according to claim 9, it is characterised in that in step 7, The A chip bottoms are bottom filler.
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CN106876363A (en) * 2017-03-13 2017-06-20 江苏长电科技股份有限公司 The fan-out package structure and its process of 3D connections
CN206685369U (en) * 2017-03-08 2017-11-28 华进半导体封装先导技术研发中心有限公司 A kind of two-sided fanout system class encapsulation structure
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120010021A (en) * 2010-07-23 2012-02-02 삼성전기주식회사 Semiconductor module and manufactureing method thereof
CN103915421A (en) * 2012-12-28 2014-07-09 台湾积体电路制造股份有限公司 Methods and apparatus for forming package-on-packages
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