CN107910264A - A kind of production method of fully- depleted soi structure - Google Patents
A kind of production method of fully- depleted soi structure Download PDFInfo
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- CN107910264A CN107910264A CN201711092666.4A CN201711092666A CN107910264A CN 107910264 A CN107910264 A CN 107910264A CN 201711092666 A CN201711092666 A CN 201711092666A CN 107910264 A CN107910264 A CN 107910264A
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- layer
- fully
- production method
- soi structure
- depleted soi
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 41
- 239000000463 material Substances 0.000 claims abstract description 84
- 239000004065 semiconductor Substances 0.000 claims abstract description 41
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 13
- 239000001301 oxygen Substances 0.000 claims abstract description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 9
- 238000002360 preparation method Methods 0.000 claims abstract description 9
- 238000002955 isolation Methods 0.000 claims abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 230000008859 change Effects 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 1
- 238000005498 polishing Methods 0.000 claims 1
- 230000008901 benefit Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910017435 S2 In Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention provides a kind of production method of fully- depleted soi structure, mainly including step：Semiconductor material layer is formed, and semiconductor material layer is patterned；Layer of channel material is formed on the top surface of semiconductor material layer and two sides；Semiconductor material layer after removing graphically；Oxide layer is formed, makes the top surface of oxide layer covering oxygen buried layer, the top surface of layer of channel material and two sides；Oxide layer is thinned, forms fleet plough groove isolation structure；Remaining technique is continued to complete, to form fully- depleted soi structure.The production method improves the preparation process of FD SOI, reduces production cost, and enables the semiconductor devices comprising the fully- depleted soi structure preferably to give play to performance advantage, and significantly saves power consumption；Therefore, the production method of the fully- depleted soi structure and wide application prospect and good market potential are respectively provided with according to product made from the production method.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of production method of fully- depleted soi structure.
Background technology
On insulator in silicon (SOI) technology, gold is formed on the thin silicone layer of the insulation material layer of covering such as silica
Belong to oxide semiconductor field effect transistor (MOSFET).The device being formed on SOI provides many better than its bulk homologue
Advantage.For example, SOI devices generally have reduced junction capacity, it is small to the reverse main body effect not having, soft error is immunized
Property, complete dielectric isolation and it is small arrive without bolt-lock effect.Therefore, SOI technology can realize the performance, higher of higher speed
Packing density and the power consumption of reduction.
In the prior art, there are two kinds of conventional soi structure：Part depletion SOI (PD-SOI) structures and full consumption
SOI (FD-SOI) structure to the greatest extent.Wherein, in 32nm/28nm and in the high-order semiconductor fabrication process of lower node, to include fully- depleted
The wafer (fully- depleted wafer) of soi structure (FD-SOI) is mainly made of the very thin silicon layer on oxygen buried layer (BOX) and BOX, from
And the transistor to be built up in this layer provides special performance, FD-SOI ensure that the various crucial categories of transistor with very thin top layer
Property.Compared with traditional Bulk CMOS, on the premise of same performance is kept, fully- depleted wafer can save up to 40% power consumption.
Equally, according to different design optimizations, the processor peak performance highest based on fully- depleted wafer can lift 60%.
The content of the invention
For technological deficiency existing in the prior art, it is contemplated that improving the preparation process of FD-SOI, production is reduced
Cost, and a kind of new fully- depleted soi structure is provided.
Specifically, the present invention adopts the following technical scheme that：
A kind of production method of fully- depleted soi structure, it comprises the following steps：
S1：Semi-conductive substrate is provided, the top surface of the Semiconductor substrate is provided with an oxygen buried layer；In the oxygen buried layer
Top surface on form semiconductor material layer, and the semiconductor material layer is patterned；
S2：A layer of channel material is formed on the top surface of the semiconductor material layer after graphical and two sides；
S3：Remove it is described it is graphical after semiconductor material layer；
S4：An oxide layer is formed, the oxide layer is covered top surface, the top surface of the layer of channel material of the oxygen buried layer
And two sides；
S5：The oxide layer is thinned, so that the top surface of the top surface of the oxide layer after being thinned and the layer of channel material
Flush, so that the oxide layer of the layer of channel material both sides forms fleet plough groove isolation structure (STI)；
S6：Remaining grid preparation process, source-drain electrode preparation process are continued to complete, further to form fully- depleted SOI junction
Structure；These techniques in this step are all the conventional technical means in this area, and are not related to the inventive point of the present invention, therefore
Repeat no more herein.
Preferably, in the S1 of the production method of above-mentioned fully- depleted soi structure, the material of the semiconductor material layer
For Si.
Preferably, in the S2 of the production method of above-mentioned fully- depleted soi structure, the material choosing of the layer of channel material
From following any：SiGe, SiC, Si.Difference based on NMOS tube and PMOS tube structure, may be selected suitable layer of channel material
Material；Wherein, what deserves to be explained is, when the material of the semiconductor material layer is Si, the material of the layer of channel material
Can be SiGe or SiC；It is described when being, for example, Ge when the material of the semiconductor material layer is the semiconductor material beyond Si
The material of layer of channel material can be Si.
Preferably, in the S2 of the production method of above-mentioned fully- depleted soi structure, the thickness of the layer of channel material≤
100nm。
Preferably, in the S2 of the production method of above-mentioned fully- depleted soi structure, the layer of channel material passes through extension
Growth is formed.
Preferably, in the S3 of the production method of above-mentioned fully- depleted soi structure, the figure is removed using wet etching
Semiconductor material layer after shape.In addition, between above-mentioned S2 and S3, alternatively comprise the following steps：To the channel material
The both ends of layer perform etching, respectively to expose one section of semiconductor material layer below the both ends of the layer of channel material, in order to rear
Continue and implement wet etching in the S3；On this basis it is further preferred that in a top view, above-mentioned each section exposed
The length ＜ 5nm of semiconductor material layer.
Preferably, in the S4 of the production method of above-mentioned fully- depleted soi structure, the oxygen is formed using deposition process
Change layer.
Preferably, in the S5 of the production method of above-mentioned fully- depleted soi structure, using cmp method
(CMP) oxide layer is thinned.
Preferably, in the S4 and S5 of the production method of above-mentioned fully- depleted soi structure, the material of the oxide layer is
Silica.
Therefore, technical solution provided by the present invention, can obtain following beneficial technique effect：
The implementation of particular step S1~S6 provided by the present invention, improves the preparation process of FD-SOI, reduces production
Cost, and enable the semiconductor devices comprising the fully- depleted soi structure preferably to give play to performance advantage, and significantly
Save power consumption；Therefore, the production method of the fully- depleted soi structure and it is respectively provided with according to product made from the production method wide
Application prospect and good market potential.
Brief description of the drawings
Fig. 1 is the FB(flow block) according to the production method of fully- depleted soi structure of the present invention；
Fig. 2 is the corresponding structure diagrams of S1 according to the production method of fully- depleted soi structure of the present invention；
Fig. 3 is the corresponding structure diagrams of S2 according to the production method of fully- depleted soi structure of the present invention；
Fig. 4 is the corresponding structure diagrams of S3 according to the production method of fully- depleted soi structure of the present invention；
Fig. 5 is the corresponding structure diagrams of S4 according to the production method of fully- depleted soi structure of the present invention；
Fig. 6 is the corresponding structure diagrams of S5 according to the production method of fully- depleted soi structure of the present invention；
Fig. 7 is the corresponding structure diagrams of S6 according to the production method of fully- depleted soi structure of the present invention；
Step pair optional between the S2 and S3 according to the production method of fully- depleted soi structure of the present invention Fig. 8
The structure diagram answered；
Wherein, 1- Semiconductor substrates, 2- oxygen buried layers, 3- semiconductor material layers, 4- layer of channel material, 5- oxide layers, D1- are sudden and violent
The length of each section of semiconductor material layer exposed.
Embodiment
Those skilled in the art are reading detailed description below and referring to the drawings after, will become apparent to the present invention
Content.With reference to embodiment, the present invention is further elaborated, but the present invention is not limited to implementation below.
Referring to Fig. 1, the production method of fully- depleted soi structure provided by the present invention includes step S1~S6.
As shown in Fig. 2, implement S1：Semi-conductive substrate 1 is provided first, is provided with the top surface of the Semiconductor substrate 1
One oxygen buried layer 2；Semiconductor material layer 3 is formed on the top surface of the oxygen buried layer 2, and the semiconductor material layer 3 is carried out
Graphically.
As shown in figure 3, implement S2：A raceway groove is formed on the top surface of the semiconductor material layer 3 after graphical and two sides
Material layer 4.
As shown in figure 4, implement S3：Remove it is described it is graphical after semiconductor material layer 3.
As shown in figure 5, implement S4：An oxide layer 5 is formed, the oxide layer 5 is covered the top surface of the oxygen buried layer 2, institute
State top surface and the two sides of layer of channel material 4；
As shown in fig. 6, implement S5：Be thinned the oxide layer 5 so that be thinned after the oxide layer 5 top surface with it is described
The top surface of layer of channel material 4 flushes, so that the oxide layer 5 of 4 both sides of the layer of channel material forms shallow trench isolation junction
Structure (STI)；
As shown in fig. 7, implement S6：Remaining grid preparation process, source-drain electrode preparation process are continued to complete, with further shape
Help depletion SOI structure.
In a preferred embodiment, the material of the semiconductor material layer 3 in the S1 is Si, at this time, the S2
In the material of the layer of channel material 4 be SiGe.
In a further advantageous embodiment, the material of the semiconductor material layer 3 in the S1 is Si, at this time, described
The material of the layer of channel material 4 in S2 is SiC.
In a further advantageous embodiment, the material of the semiconductor material layer 3 in the S1 is Ge, at this time, described
The material of the layer of channel material 4 in S2 is Si.
In a preferred embodiment, thickness≤100nm of the layer of channel material 4 in the S2.
In a preferred embodiment, the layer of channel material 4 in the S2 is by being epitaxially-formed.
In addition, referring to Fig. 8, it is further comprising the steps of between the S2 and S3 in an optional embodiment：To institute
The both ends for stating layer of channel material 4 perform etching, respectively to expose one section of semi-conducting material below the both ends of the layer of channel material 4
Layer 3；In a further preferred embodiment, the length D1 ＜ 5nm of the above-mentioned each section of semiconductor material layer exposed.
In a preferred embodiment, in the S3, using wet etching remove it is described it is graphical after semiconductor material
The bed of material 3.
In a preferred embodiment, in the S4, the oxide layer 5 is formed using deposition process.
In a preferred embodiment, in the S5, the oxide layer is thinned using cmp method (CMP)
5。
In a preferred embodiment, in the S4 and S5, the material of the oxide layer 5 is silica.
The specific embodiment of the present invention is described in detail above, but it is intended only as example, it is of the invention and unlimited
It is formed on particular embodiments described above.To those skilled in the art, it is any to the equivalent modifications that carry out of the present invention and
Substitute also all among scope of the invention.Therefore, the impartial conversion made without departing from the spirit and scope of the invention and
Modification, all should be contained within the scope of the invention.
Claims (9)
1. a kind of production method of fully- depleted soi structure, it is characterised in that comprise the following steps：
S1：Semi-conductive substrate is provided, the top surface of the Semiconductor substrate is provided with an oxygen buried layer；On the top of the oxygen buried layer
Semiconductor material layer is formed on face, and the semiconductor material layer is patterned；
S2：A layer of channel material is formed on the top surface of the semiconductor material layer after graphical and two sides；
S3：Remove it is described it is graphical after semiconductor material layer；
S4：An oxide layer is formed, the oxide layer is covered top surface, the top surface and two of the layer of channel material of the oxygen buried layer
Side；
S5：The oxide layer is thinned, so that the top surface of the oxide layer after being thinned is flushed with the top surface of the layer of channel material,
So that the oxide layer of the layer of channel material both sides forms fleet plough groove isolation structure；
S6：Remaining grid preparation process, source-drain electrode preparation process are continued to complete, further to form fully- depleted soi structure.
2. the production method of fully- depleted soi structure according to claim 1, it is characterised in that in the S1, described half
The material of conductor material layer is Si.
3. the production method of fully- depleted soi structure according to claim 1, it is characterised in that in the S2, the ditch
The material of road material layer is selected from following any：SiGe, SiC, Si.
4. the production method of fully- depleted soi structure according to claim 1, it is characterised in that in the S2, the ditch
Thickness≤100nm of road material layer.
5. the production method of fully- depleted soi structure according to claim 1, it is characterised in that in the S2, the ditch
Road material layer is by being epitaxially-formed.
6. the production method of fully- depleted soi structure according to claim 1, it is characterised in that in the S3, use is wet
Method etching remove it is described it is graphical after semiconductor material layer.
7. the production method of fully- depleted soi structure according to claim 1, it is characterised in that in the S4, using heavy
Product method forms the oxide layer.
8. the production method of fully- depleted soi structure according to claim 1, it is characterised in that in the S5, using change
Learn mechanical polishing method and the oxide layer is thinned.
9. the production method of fully- depleted soi structure according to claim 1, it is characterised in that in the S4 and S5, institute
The material for stating oxide layer is silica.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711092666.4A CN107910264B (en) | 2017-11-08 | 2017-11-08 | Manufacturing method of fully-depleted SOI structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711092666.4A CN107910264B (en) | 2017-11-08 | 2017-11-08 | Manufacturing method of fully-depleted SOI structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107910264A true CN107910264A (en) | 2018-04-13 |
| CN107910264B CN107910264B (en) | 2020-06-30 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5807771A (en) * | 1996-06-04 | 1998-09-15 | Raytheon Company | Radiation-hard, low power, sub-micron CMOS on a SOI substrate |
| US20030215989A1 (en) * | 2001-04-12 | 2003-11-20 | Sang-Su Kim | Semiconductor device having gate all around type transistor and method of forming the same |
| CN1905127A (en) * | 2005-07-27 | 2007-01-31 | 精工爱普生株式会社 | Method for manufacturing a semiconductor substrate and method for manufacturing a semiconductor device |
| CN101170134A (en) * | 2007-11-30 | 2008-04-30 | 西安理工大学 | Full consumption Air_A1N_SOI MOSFETs part structure and its making method |
| CN103367450A (en) * | 2013-05-09 | 2013-10-23 | 北京大学 | Radiation-hardened SOI (silicon-on-insulator) device and preparation method thereof |
| CN103915483A (en) * | 2012-12-28 | 2014-07-09 | 瑞萨电子株式会社 | Field effect transistor with channel core modified to reduce leakage current and method of fabrication |
-
2017
- 2017-11-08 CN CN201711092666.4A patent/CN107910264B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5807771A (en) * | 1996-06-04 | 1998-09-15 | Raytheon Company | Radiation-hard, low power, sub-micron CMOS on a SOI substrate |
| US20030215989A1 (en) * | 2001-04-12 | 2003-11-20 | Sang-Su Kim | Semiconductor device having gate all around type transistor and method of forming the same |
| CN1905127A (en) * | 2005-07-27 | 2007-01-31 | 精工爱普生株式会社 | Method for manufacturing a semiconductor substrate and method for manufacturing a semiconductor device |
| CN101170134A (en) * | 2007-11-30 | 2008-04-30 | 西安理工大学 | Full consumption Air_A1N_SOI MOSFETs part structure and its making method |
| CN103915483A (en) * | 2012-12-28 | 2014-07-09 | 瑞萨电子株式会社 | Field effect transistor with channel core modified to reduce leakage current and method of fabrication |
| CN103367450A (en) * | 2013-05-09 | 2013-10-23 | 北京大学 | Radiation-hardened SOI (silicon-on-insulator) device and preparation method thereof |
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