CN107910036A - The test method of personalized MCU personalizations memory block - Google Patents
The test method of personalized MCU personalizations memory block Download PDFInfo
- Publication number
- CN107910036A CN107910036A CN201711072315.7A CN201711072315A CN107910036A CN 107910036 A CN107910036 A CN 107910036A CN 201711072315 A CN201711072315 A CN 201711072315A CN 107910036 A CN107910036 A CN 107910036A
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- Prior art keywords
- trim
- memory block
- personalized
- test
- test method
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The present invention provides a kind of test method for being used to test personalized MCU personalizations memory block.This method makes carbon copies back the mode of personalized memory block to realize by reading the trim values in Trim registers, and the value.After the functional test of personalized memory block is completed, since functional test includes erasable operation, personalized memory block content has been destroyed at this time.In the case where not ensureing electricity, the trim values that can be stored by reading in trim registers, and trim values are made carbon copies go back to personalized memory block to ensure the integrality of trim values.It can not only ensure the test coverage of personalized memory block by using this method, but also ensure that trim data are not lost.
Description
Technical field:
A kind of test method of personalized memory block for calibration tape personalization memory block MCU.It belongs to measuring technology
Field.
Background technology：
The test method of personalization MCU personalizations memory block is directed at this stage, and general memory block function using acquiescence does not have
It is problematic, trim values are write the memory block.Subsequently through these enabled trim values, test by the mode of trim functions of modules,
To ensure that trim values are correct.Such a test method, it is impossible to distinguish by trim functions of modules failure have module cause in itself or
Memory block self problem causes.Meanwhile because detailed screening was not done in personalized memory block, the reliability subsequently used is also not
It can be guaranteed.
Based on this, which describes a kind of test method for being used to test personalized MCU personalizations memory block：In trim
After the completion of, trim values are read in trim registers, hereafter personalized memory block is screened in detail；After the completion of screening,
Read the personalized memory block of Trim registers manifolding.It can not only ensure the test coverage of personalized memory block by the method, but also
Ensure that trim data are not lost.
Main illustrate of text of the invention describes a kind of test method for being used to test personalized MCU personalizations memory block, with
Conventional test methodologies are compared, and can not only ensure the test coverage of personalized memory block, but also ensure that trim data are not lost.
The content of the invention:
, can the technical problem to be solved in the present invention is to provide a kind of test method of personalization MCU personalizations memory block
Ensure that personalized memory block is capped and saves the testing time.The invention mainly includes steps：
1) first power on, complete institute the IP in need for being trim trim operate, trim values recorded personalization and deposit
In storage unit；
2) power on for the second time, in this power up, bootstrap can be loaded into trim in trim registers in CPU, at the same time
It is made to come into force；After being operated more than completing, the functional test of personalized memory block is carried out；The functional test can deposit personalization
Storage area carries out erasable, to cause inside to be stored trim values loss；
3) after completing personalized memory block test, in the case where not ensureing electricity, by reading trim register instructions
Read out trim values are preserved in register, with write command, make carbon copies to personalized memory block.
4) ensure that trim data are not lost by reading trim registers to make carbon copies personalized memory block；
Chip can be loaded into trim registers automatically after the power is turned on, trim data.The not lower electricity of test process chips, with
This is protected
Card data in register is not lost.After completing personalized memory block test, trim data are made carbon copies into personalization
Memory block.
Method using the present invention, in the case where ensureing trim data integrities, can ensure the survey of personalized memory block
Coverage rate is tried, to ensure the follow-up use reliability of chip.
Brief description of the drawings：
Fig. 1, trim flow chart
Fig. 2, test ＆ manifolding flow charts
Embodiment：
The present invention is described in further detail with embodiment below in conjunction with the accompanying drawings：
After the power is turned on, because of process variations, selected power supply IP cannot be guaranteed storage unit and other modules normal work to chip, need
Trim operations are carried out in advance；Meanwhile memory block IP also needs to complete the trim operations that different vendor requires；Above trim operation generations
Trim values be stored in personalized memory block.
With reference to shown in attached drawing 1, it is as follows that the personalization MCU powers on trim processes：
Step 1, powers on, and judges personalized storage area data validity where trim values.Area's no data at this time, therefore fill
Carry design default value.
Step 2, according to design requirement, carries out the trim of each IP.
Step 3, carries out memory block trim.
Above-mentioned trim values, are write personalized memory block by step 4.
Step 5, lower electricity.
Most of company no longer carries out functional screening after completion trim is tested and is write for personalized memory block.But
This region stores data to chip using most important, is lost during later stage use, can directly contribute chip failure.Therefore adopt
With this method, realize the screening of personalized memory block, ensure the reliability in follow-up use.
With reference to shown in attached drawing 2, test ＆ manifoldings flow is as follows：
Step 1, powers on, and judges personalized storage area data validity where trim values.
Step 2, area's data are effective at this time, are loaded into trim registers.
Step 3, carries out personalized memory block functional test, including erasable test etc..
Step 4, reads trim values in register, makes carbon copies into personalized memory block.
Step 5, lower electricity.
Claims (4)
1. the test method of personalization MCU personalizations memory block, it is characterised in that comprise the following steps：
1) first power on, complete the trim operations of the institute IP in need for being trim, trim values recorded and personalized store list
In member；
2) power on for the second time, in this power up, bootstrap can be loaded into trim in trim registers in CPU, while make it
Come into force；After being operated more than completing, the functional test of personalized memory block is carried out；The functional test can be to personalized memory block
Carry out erasable, to cause inside to be stored trim values loss；
3) after completing personalized memory block test, in the case where not ensureing electricity, posted by reading trim register instructions handle
Trim values are preserved in storage to read out, and with write command, are made carbon copies to personalized memory block.
4) ensure that trim data are not lost by reading trim registers to make carbon copies personalized memory block.
2. test method as claimed in claim 1, it is characterised in that the step 2) for the second time after the power is turned on, trim data
It is to be loaded into trim registers automatically.
3. test method as claimed in claim 1, it is characterised in that the not lower electricity of each step test process chips,
Ensure that data in register is not lost with this.
4. test method as claimed in claim 1, it is characterised in that the step 3) completes personalized memory block and tests it
Afterwards, trim data are made carbon copies into personalized memory block.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711072315.7A CN107910036A (en) | 2017-11-04 | 2017-11-04 | The test method of personalized MCU personalizations memory block |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711072315.7A CN107910036A (en) | 2017-11-04 | 2017-11-04 | The test method of personalized MCU personalizations memory block |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107910036A true CN107910036A (en) | 2018-04-13 |
Family
ID=61842834
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711072315.7A Pending CN107910036A (en) | 2017-11-04 | 2017-11-04 | The test method of personalized MCU personalizations memory block |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109613420A (en) * | 2019-01-30 | 2019-04-12 | 上海华虹宏力半导体制造有限公司 | The test method of chip |
Citations (2)
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| EP2365488A1 (en) * | 2010-03-08 | 2011-09-14 | Fujitsu Semiconductor Limited | Apparatus and method for testing semiconductor integrated circuits, and a non-transitory computer-readable medium having a semiconductor integrated circuit testing program |
| CN106293633A (en) * | 2016-08-15 | 2017-01-04 | 深圳市博巨兴实业发展有限公司 | A kind of instruction fetch control module for MCU SOC |
-
2017
- 2017-11-04 CN CN201711072315.7A patent/CN107910036A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2365488A1 (en) * | 2010-03-08 | 2011-09-14 | Fujitsu Semiconductor Limited | Apparatus and method for testing semiconductor integrated circuits, and a non-transitory computer-readable medium having a semiconductor integrated circuit testing program |
| CN106293633A (en) * | 2016-08-15 | 2017-01-04 | 深圳市博巨兴实业发展有限公司 | A kind of instruction fetch control module for MCU SOC |
Non-Patent Citations (1)
| Title |
|---|
| 徐明皞: "关于提高芯片ICS模块良品率的研究", 《中国优秀硕士学位论文全文数据库（电子期刊）》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109613420A (en) * | 2019-01-30 | 2019-04-12 | 上海华虹宏力半导体制造有限公司 | The test method of chip |
| CN109613420B (en) * | 2019-01-30 | 2021-04-06 | 上海华虹宏力半导体制造有限公司 | Chip testing method |
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Application publication date: 20180413 |