CN107908135B

CN107908135B - Digital implementation method for soft start of direct current electronic load

Info

Publication number: CN107908135B
Application number: CN201711220461.XA
Authority: CN
Inventors: 赵浩华; 高志齐; 赵志坚; 陈绪聪
Original assignee: Changzhou Tonghui Electronics Co ltd
Current assignee: Changzhou Tonghui Electronics Co ltd
Priority date: 2017-11-29
Filing date: 2017-11-29
Publication date: 2020-09-08
Anticipated expiration: 2037-11-29
Also published as: CN107908135A

Abstract

The invention relates to a digital implementation method for soft start of a direct current electronic load, which comprises the steps of converting sampling time T, an initial level Vo, a termination level Vs, a slope signal sampling frequency N1 and a time constant tau into integers by using a CPU (central processing unit) as a reference respectively, and writing the integers into a bus data processing module of an FPGA (field programmable gate array); completing formula calculation by a DAC data generation module in a single sampling period to obtain an input signal of the system; calculating by a differential equation to obtain an output signal, and converting the output signal into a level value of an actual control signal through a compensation module; generating a cycle control logic by a DAC data generation module, and transmitting the obtained level signal value to an SPI output control module; the SPI output control module simulates sequential logic and outputs a final control signal to a chip pin. The invention only comprises an integer addition, subtraction, multiplication and division digital algorithm, and the FPGA carries out real-time calculation of the control signal, thereby meeting the setting of any parameter and achieving the frequency response index, thereby well realizing the soft start function.

Description

Digital implementation method for soft start of direct current electronic load

Technical Field

The invention relates to the field of power testing, in particular to a digital implementation method for soft start of a direct current electronic load.

Background

With the rapid development of new energy industry, the demand of power supply testing on high-performance electronic loads is increasingly expanding. The number of layers of electronic load products in the market is infinite, and most of electronic loads can only control the current to rise along a straight line according to a set rising slope in the aspect of realizing the function of controlling the rising time of the current. The method has the disadvantages that firstly, the power-on process of the inductive load cannot be simulated; when the power supply to be tested generates oscillation or sharply changed current, the current is difficult to stabilize in the process of starting the load; and thirdly, unnecessary overcurrent protection can be generated when the loading is started.

In the prior art, only hardware is used to implement the soft start function (such as the circuit shown in fig. 1). In this method, the signal generated by the slope generator is sent to the RC series circuit, and the voltage output from the capacitor terminal is used as the control signal (as shown in fig. 2). The selection of the soft start time parameter is realized by connecting different resistors (8 resistors with different values in fig. 1). The disadvantage is that the optional parameters are limited and cannot meet the actual requirement. However, if a general software method is used, two difficulties are faced: the use of a high-performance DSP can realize the arbitrary setting of soft start parameters, but the frequency response range of 1MHz is difficult to reach (the calculation and data transmission of a single complex formula are difficult to be completed within 1us, and the data transmission is limited by the bus efficiency); although bus transmission time is saved by using the FPGA capable of performing parallel computation, the FPGA cannot perform operation of transcendental functions, and excessively huge computation finally results in that the frequency response range of 1MHz cannot be met. Therefore, how to realize the setting of any soft start time parameter and reach the frequency response range of 1MHz becomes a key technical problem.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: a digital implementation method for soft start of a direct current electronic load is provided.

The technical scheme adopted by the invention is as follows: a digital implementation method for soft start of a direct current electronic load comprises the following steps:

1) the CPU converts the sampling time T, the initial level Vo, the termination level Vs, the sampling times N1 of the slope signal and the time constant tau into integers by taking the DAC as a reference respectively and writes the integers into a bus data processing module of the FPGA;

2) according to the formula

In a single sampling period (1us), the DAC data generation module completes formula calculation to obtain a signal e (n) generated by the analog slope generator, and the signal e (n) is used as an input signal of the system.

3) According to the formula

The output signal v (n) is calculated from the difference equation.

4) And converting v (n) into the level value of the actual control signal through the compensation module.

5) And (4) generating a cyclic control logic by a DAC data generation module, and transmitting the level signal value obtained in the step (4) to the SPI output control module.

6) The SPI output control module simulates sequential logic of an ADR5541 chip and outputs a final control signal to a chip pin.

The invention has the beneficial effects that: the invention only comprises an integer addition, subtraction, multiplication and division digital algorithm, and the FPGA carries out real-time calculation of the control signal, thereby meeting the setting of any parameter and achieving the frequency response index, thereby well realizing the soft start function.

Drawings

The invention is further illustrated with reference to the following figures and examples.

FIG. 1 is a schematic diagram of a hardware circuit implementation of the soft start function;

fig. 2 is a waveform diagram of the DAC output signal measured by an oscilloscope with the abscissa as time and the unit us.

FIG. 3 is a theoretical plot of the time domain continuous signal of the system, with time on the abscissa and in units of s;

fig. 4 is a graph of a computational simulation using a difference equation with the abscissa as a sampling point.

Fig. 5 is a schematic diagram of an FPGA-based implementation.

Detailed Description

The invention will now be described in further detail with reference to the drawings and preferred embodiments. These drawings are simplified schematic views illustrating only the basic structure of the present invention in a schematic manner, and thus show only the constitution related to the present invention.

A digital implementation method for soft start of a direct current electronic load has the following working principle:

A. establishment of system mathematical model

As shown in fig. 1, let the output voltage of the slope generator be e (t), the voltage of the capacitor end be v (t), and the following differential equation can be obtained according to KVL theorem and the charge transfer law:

let the slope be K (A/s), time be t, start level be Vo, end voltage be Vs, then e (t) can be expressed as a piecewise function:

substituting the formula (1-2) into the formula (1-1):

let τ be RC. And solving a differential equation by using Laplace transform/inverse transform to obtain an expression of a time domain signal:

wherein:

in practical engineering, when t is 5 τ + t1, v (t) is approximately equal to Vs. The segmented expression of the control signal can be further rewritten as:

the theoretical curve of the piecewise function is shown in fig. 3.

It can be seen that the mathematical model established above conforms to the working conditions of an actual circuit.

B. Solving differential equations from system functions

If the system input is e (t) and the output is v (t). When e (t) is the unit impulse function, v (t) is the system function h (t). According to the formula (1-1), the compound can be obtained:

when bilinear transformation is adopted, the conversion relation from the s-domain function to the z-domain function is as follows:

where T is the sampling time interval at which the analog signal is sampled at equal intervals. The index is 1 us.

Substituting into formula (2-1) and finishing to obtain:

and also

Obtaining:

wherein:

since T is a unit sampling time, τ and T1 are both integer multiples of T. The following modifications are made to the formula (2-4):

in the formula (3-6), the terms (2 τ -T) and (2 τ + T) are constant values, and only once calculation is needed when τ and T are written, and then repeated calculation is not needed. Thus, it can be seen that the expression (3-6) includes 3 times of integer multiplication, 2 times of integer addition, and 1 time of integer division in total. The FPGA can complete this calculation.

The simulation curve of the difference equation is shown in fig. 4.

It can be seen that the algorithm design strictly follows the design requirements.

C.FPGA realizes soft start

According to the formulas 3-6, the CPU completes parameter setting and transmission, the FPGA completes formula calculation and logic control, and finally data are transmitted to the DAC control chip ADR5541 pin. The implementation principle is shown in fig. 5.

The FPGA portion includes three modules: the device comprises a bus data processing module, a DAC data generation module and an SPI output control module.

The bus data processing module: the bus part adopts 8-bit data signal lines, 3-bit address signal lines, 1-bit chip selection signal lines, 1-bit read effective signal lines and 1-bit write effective signal lines. The parameters related to the formula are transmitted to a formula calculation module, relevant state signals are read back, and necessary control signals are generated.

A DAC data generation module: DAC data generation includes processing logic for 2 additions, 3 multiplications, 1 division, data compensation logic, and control and data signal logic needed to cyclically generate the SPI output control module.

The SPI output control module: this module will generate control logic that satisfies the timing of the ADR5541 chip.

All modules adopt 50M external crystal oscillators, so that the stability of clock signals is ensured, and meanwhile, synchronous logic processing is adopted, so that the stability of a system is favorably kept. The chip ADR5541 for realizing the DA conversion function supports an input clock of 25MHz at most, outputs 16-bit precision data and meets the data transmission logic of the SPI standard. The frequency response requires 1MHz, i.e. 1us, to send data once, and it takes 40ns 16 ns 640ns to complete 16-bit SPI data, so there is more than enough time. New data needs to be generated once within 1us of unit sampling time (50 clocks), wherein the logic related to the multiplication and division part needs to make timing constraints to prevent data competition.

The FPGA adopted by the invention is EP4CE6E22C8 of Altera company, the total logic unit is 6272, about 2000 logic units are consumed, and most of the FPGAs in the current market can meet the requirements. Meanwhile, the FPGA is responsible for data operation logic, and a chip responsible for the CPU function only needs to complete simple functions such as parameter setting, state detection and the like, so that the selectable range is wide, even part of the FPGA can be replaced by a built-in soft core nios, and the realization cost and difficulty are reduced to a certain extent.

The control principle of realizing soft start based on the FPGA can accurately calculate the control signal of each sampling point so as to output DAC (digital-to-analog converter) to realize current load.

While particular embodiments of the present invention have been described in the foregoing specification, the various illustrations do not limit the spirit of the invention, and one of ordinary skill in the art, after reading the description, can make modifications and alterations to the particular embodiments described above without departing from the spirit and scope of the invention.

Claims

1. A digital implementation method for soft start of a direct current electronic load is characterized by comprising the following steps:

1) the CPU converts the sampling time T, the initial level Vo, the termination level Vs, the sampling times N1 of the slope signal and the time constant tau into integers by taking a digital-to-analog converter DAC as a reference respectively and writes the integers into a bus data processing module of the FPGA;

2) in a single sampling period, finishing formula calculation by a digital-to-analog converter DAC data generation module to obtain a signal e (n) generated by an analog slope generator and used as an input signal of a system;

the formula for generating signal e (n) is:

(ii) a Wherein T is sampling time, τ and T1 are integer multiples of T, K is slope, T1=

；

3) Calculating to obtain an output signal v (n) through a difference equation;

the output signal v (n) is: v (n) =

(ii) a Wherein, the terms (2 tau-T) and (2 tau + T) are fixed values, and only once calculation is needed when tau and T are written, and then repeated calculation is not needed;

4) converting v (n) into a level value of an actual control signal through a compensation module;

5) generating a cyclic control logic by a digital-to-analog converter (DAC) data generation module, and transmitting the level signal value obtained in the step 4) to an SPI output control module;

6) the SPI output control module simulates chip sequential logic and outputs a final control signal to a chip pin.