CN107894598B - Universal four-channel digital anti-interference baseband circuit and implementation method - Google Patents

Abstract

The invention relates to a universal four-channel digital anti-interference baseband circuit and an implementation method thereof, wherein an input four-channel analog intermediate frequency signal is converted into a digital intermediate frequency signal, the four-channel intermediate frequency signal is processed by an FPGA anti-interference baseband processing circuit, and the up-converted digital intermediate frequency signal is converted into an analog intermediate frequency signal, so that the digital anti-interference processing of the analog intermediate frequency signal is realized; meanwhile, ARM9 processing circuit application programs respectively read four-channel down-conversion data in a storage circuit SDRAM and analyze and process the four-channel down-conversion data, and send the four-channel down-conversion data to an upper computer interface through an RS232 interface in an interface circuit to display four-channel radio frequency front end state information according to related protocols; the ARM9 processing circuit collects detection information of the power supply current detection circuit, the working state of the anti-interference baseband circuit is judged through the set fault threshold, and interaction with direct locking of an external user and online loading instructions of a program is achieved through the interface circuit. The requirements of the anti-interference antenna wide-voltage application range of the aircraft/missile-borne satellite are met.

Description

Universal four-channel digital anti-interference baseband circuit and implementation method

Technical Field

The invention relates to a universal four-channel digital anti-interference baseband circuit and an implementation method thereof, which are applied to the universal four-channel digital anti-interference baseband circuit meeting the requirements of different platforms of a machine/missile-borne Beidou satellite anti-interference antenna.

Background

The existing Beidou satellite anti-interference antenna comprehensively considers product volume and cost, generally adopts a four-channel digital anti-interference baseband circuit, has more circuit design types due to different requirements of different platforms, has different functions such as controlled through locking, on-line loading, power supply current detection, power supply protection and the like besides main functions such as A/D, D/A and FPGA anti-interference baseband processing according to the current product requirements, and sometimes needs to be realized by adding additional microprocessors due to different hardware realization modes of various products, so that the problems of more hardware types and quantity, more device type selection types and the like are caused.

The existing digital anti-interference baseband circuit mainly has the advantages of small direct current power supply voltage range in the aspect of power supply circuit design, and the design without power supply protection can not meet the requirements of part of GJB181-1986 on-board power supply characteristics; in the design of the interactive software with the external user, the implementation is mainly realized by adding an FPGA circuit with smaller resources, the FPGA hardware description language realizes interface protocol conversion software, communication software with an upper computer interface and program portability in the aspect of online program loading, and the implementation is complex; in the aspect of the design of a storage circuit, an on-chip FLASH storage software program is mainly adopted, and the capacity is small, so that large-scale program and large-scale data storage cannot be met. Therefore, the functional requirements of each product on the digital anti-interference unit are unified, the types of components, the number and the types of hardware are reduced, the resource utilization rate of the single ARM9 for realizing the functions is improved, and the stability and the reliability of a circuit are improved.

Disclosure of Invention

In view of the defects existing in the prior art, the invention provides a universal four-channel digital anti-interference baseband circuit.

The invention aims to meet the requirements of the anti-interference antenna wide-voltage application range of the machine/missile-borne satellite, and the microprocessor adopts high-level language to realize interface protocol conversion software, interface communication software with an upper computer and on-line program loading program design, so that the program portability is good, and the implementation and maintenance are easy; the large-capacity FLASH chips outside the ARM9 and the FPGA are used for storing large programs and a large amount of data, and the universal four-channel digital anti-interference baseband circuit meets the requirements of multiple platforms in the aspects of power circuit design, anti-interference software hardware requirement design and real-time processing of a large amount of data, so that the universal design is realized.

The invention adopts the technical proposal for realizing the aim that: a universal four-channel digital anti-interference baseband circuit is characterized in that: the device comprises a DC/DC power supply conversion circuit, a power supply current detection circuit, a power supply protection circuit, an A/D analog-to-digital conversion circuit, a D/A digital-to-analog conversion circuit, a clock distribution circuit, an ARM9 processing circuit, an FPGA anti-interference baseband processing circuit, a clock and reset circuit, a storage circuit and an interface circuit;

the DC/DC power conversion circuit is respectively connected with the power current detection circuit, the power protection circuit, the A/D analog-to-digital conversion circuit, the D/A digital-to-analog conversion circuit, the clock distribution circuit, the ARM9 processing circuit, the FPGA anti-interference baseband processing circuit, the clock and reset circuit, the storage circuit and the interface circuit, the power protection circuit is connected with the power current detection circuit, the power current detection circuit is connected with the ARM9 processing circuit, the FPGA anti-interference baseband processing circuit is respectively connected with the A/D analog-to-digital conversion circuit, the clock distribution circuit, the D/A digital-to-analog conversion circuit, the storage circuit and the ARM9 processing circuit, and the clock distribution circuit is connected with the A/D analog-to-digital conversion circuit, and the ARM9 processing circuit is respectively connected with the clock and reset circuit, the storage circuit and the interface circuit;

the circuit firstly performs overvoltage and undervoltage protection on a power supply part through a power supply protection circuit, then converts the input 9V-36V direct current voltage into two paths of +5V voltages through a DC/DC power supply conversion circuit, one path of digital +5V supplies power to the whole digital anti-interference baseband circuit, the other path of analog +5V voltage is used as a reserved voltage to supply power to the satellite anti-interference antenna analog part, the digital +5V circuit is converted into four paths of voltages through a secondary power supply, the four paths of voltages are +3.3V, +1.8V, +1.2V and +1.0V respectively, and the +3.3V is the pin power supply voltage of the FPGA anti-interference baseband processing circuit and the ARM9 processing circuit; +1.8V mainly supplies power for the A/D analog-to-digital conversion circuit and the FPGA anti-interference baseband processing circuit; +1.2V and +1.0V are respectively the nuclear power supply of ARM9 processing circuit and FPGA anti-interference baseband processing circuit, the requirement on voltage precision is higher;

the power supply current detection circuit detects an input direct current power supply, sends a detected signal to the ARM9 processing circuit for processing to judge the working state of the digital anti-interference baseband circuit, and transmits the detected signal to inertial navigation through a serial port;

the satellite anti-interference antenna radio frequency part generates four paths of 46.52 +/-10.23 MHz Beidou intermediate frequency signals, the four paths of A/D conversion circuits convert the Beidou intermediate frequency signals into digital signals, the digital signals are sent to the FPGA anti-interference baseband processing circuit for anti-interference processing, and the anti-interference processed data are converted into analog Beidou intermediate frequency signals through the D/A conversion circuit;

the memory circuit core mainly comprises NANDFLASH, NORFLASH and SDRAM three memory chips, wherein the NANDFLASH is connected with the ARM9 microprocessor, and is mainly used for storing an anti-interference program of the FPGA anti-interference baseband processing circuit, and when the FPGA anti-interference baseband processing circuit is powered on, the FPGA anti-interference baseband processing circuit starts anti-interference work through loading the program of the boot of the ARM9 processing circuit; the NORFLASH chip is mainly used for storing ARM9 processing circuit application programs, and the application programs are mainly responsible for collecting and processing sampling data of the FPGA anti-interference baseband processing circuit on four paths of radio frequency channels, program on-line loading, power supply current detection and control functions of interface part separation and dispersion; SDRAM mainly stores the data of the FPGA anti-interference baseband processing circuit and ARM9 processing circuit;

the interface circuit part mainly comprises two paths of RS232 level serial ports, two paths of RS422 level serial ports, controlled discrete quantity, an ARM9 processing circuit JTAG interface and a JTAG download interface of the FPGA anti-interference baseband processing circuit, wherein one path of RS232 serial ports are used for debugging and online program upgrading, one path of RS232 serial ports are used for reporting the working state of the four-channel anti-interference baseband circuit and communicating with external user data, one path of RS422 serial ports are used for interacting with the inertial navigation interface, and one path of RS422 serial ports are reserved;

the controlled discrete quantity is an I/O interface connected with the ARM9 processing circuit, and an external instruction is received through a serial port to control the discrete quantity so as to realize the direct locking function of the satellite anti-interference antenna; the two JTAG interfaces are mainly used for online debugging of the program.

The implementation method of the universal four-channel digital anti-interference baseband circuit is characterized by comprising the following steps: after the four-channel digital anti-interference baseband circuit is electrified, all circuit hardware starts to initialize, firstly an ARM9 processing circuit respectively reads target codes of an ARM9 processing circuit application program and an FPGA anti-interference processing program in a storage circuit through a boot loader, the target codes are loaded into the ARM9 processing circuit and the FPGA anti-interference baseband processing circuit, and a software program starts to run;

the input four-channel analog intermediate frequency signal is acquired into a four-channel digital intermediate frequency signal through an A/D analog-to-digital conversion circuit, and anti-interference software of an FPGA anti-interference baseband processing circuit carries out channel gain consistency influence factor self-adaptive compensation processing, digital down-conversion processing, low-pass filtering, weight generation iteration and updating, frequency domain filtering, secondary quantization and digital up-conversion processing on the four-channel intermediate frequency signal respectively, and the up-converted digital intermediate frequency signal is converted into an analog intermediate frequency signal through a D/A digital-to-analog conversion circuit, so that the digital anti-interference processing of the analog intermediate frequency signal is realized; when the anti-interference processing is carried out, ARM9 processing circuit application programs respectively read four-channel down-conversion data in a storage circuit SDRAM and carry out analysis processing, and the four-channel down-conversion data are sent to an upper computer interface for display through an RS232 interface in an interface circuit according to a related protocol, so that state information of the four-channel radio frequency front end is displayed in real time; ARM9 processing circuit gathers power supply current detection circuit detection information, judges anti-interference baseband circuit operating condition through the fault threshold that sets up, realizes the interaction with outside user direct-connection shutting and procedure on-line loading instruction through RS232 interface, RS422 interface and I/O mouth discrete quantity in the interface circuit.

The invention is characterized in that: the DC/DC direct-current power supply conversion circuit realizes that direct-current 9V-36V wide-range voltage input primary power supply is converted into a double-circuit +5V power supply, the secondary power supply is respectively converted into +3.3V, +1.8V, +1.2V and +1.0V, wherein +5V power supply can respectively supply power to the anti-interference antenna radio frequency part and the digital anti-interference unit circuit, and four voltages of the secondary power supply conversion can supply power to the A/D chip, the D/A chip, the ARM9 microprocessor, the FPGA baseband processor and the like; the power supply current detection circuit can judge the working state of each part of the digital anti-interference unit by detecting the current of the power supply circuit, and the ARM9 processing circuit timely processes and reports the fault code of the unit board; the power supply protection circuit can realize the functions of overvoltage 60V protection, reverse-40V voltage protection, adjustable overvoltage and undervoltage protection range and the like; the ARM9 processing circuit mainly controls the radio frequency power supply part by controlling the through locking of the anti-interference antenna, reads four paths of radio frequency digital signals acquired by the A/D analog-to-digital conversion circuit in the SDRAM of the storage circuit, visually displays the four paths of radio frequency digital signals through an upper computer software interface, processes power supply current detection information, and has the functions of loading an FPGA anti-interference program boot, upgrading an online program and the like; the FPGA anti-interference baseband processing circuit is mainly used for carrying out anti-interference processing on radio frequency signals acquired by four paths of A/Ds, and the processed signals are converted into analog intermediate frequency signals through a D/A digital-to-analog conversion circuit; the dual-channel static electricity protection device has two paths of RS232 serial ports and two paths of RS422 serial ports, and has +15V static electricity protection function.

Drawings

FIG. 1 is a circuit connection block diagram of the invention;

fig. 2 is a software flow chart of the invention.

Detailed Description

The invention is further described below with reference to the accompanying drawings.

As shown in FIG. 1, the universal four-channel digital anti-interference baseband circuit comprises a DC/DC power supply conversion circuit, a power supply current detection circuit, a power supply protection circuit, an A/D analog-to-digital conversion circuit, a D/A digital-to-analog conversion circuit, a clock distribution circuit, an ARM9 processing circuit, an FPGA anti-interference baseband processing circuit, a clock and reset circuit, a storage circuit and an interface circuit.

The DC/DC power conversion circuit is respectively connected with the power current detection circuit, the power protection circuit, the A/D analog-to-digital conversion circuit, the D/A digital-to-analog conversion circuit, the clock distribution circuit, the ARM9 processing circuit, the FPGA anti-interference baseband processing circuit, the clock and reset circuit, the storage circuit and the interface circuit, the power protection circuit is connected with the power current detection circuit, the power current detection circuit is connected with the ARM9 processing circuit, the FPGA anti-interference baseband processing circuit is respectively connected with the A/D analog-to-digital conversion circuit, the clock distribution circuit, the D/A digital-to-analog conversion circuit, the storage circuit and the ARM9 processing circuit, the clock distribution circuit is connected with the A/D analog-to-digital conversion circuit, and the ARM9 processing circuit is respectively connected with the clock and reset circuit, the storage circuit and the interface circuit.

The circuit firstly performs overvoltage and undervoltage protection on a power supply part through a power supply protection circuit, then converts the input 9V-36V direct current voltage into two paths of +5V voltages through a DC/DC power supply conversion circuit, one path of digital +5V supplies power to the whole digital anti-interference baseband circuit, the other path of analog +5V voltage is used as a reserved voltage to supply power to the satellite anti-interference antenna analog part, the digital +5V circuit is converted into four paths of voltages through a secondary power supply, the four paths of voltages are +3.3V, +1.8V, +1.2V and +1.0V respectively, and the +3.3V is the pin power supply voltage of the FPGA anti-interference baseband processing circuit and the ARM9 processing circuit; +1.8V mainly supplies power for the A/D analog-to-digital conversion circuit and the FPGA anti-interference baseband processing circuit; +1.2V and +1.0V are respectively the nuclear power supply of ARM9 processing circuit and FPGA anti-interference baseband processing circuit, and have higher requirements on voltage precision.

The power supply current detection circuit detects an input direct current power supply, sends a detected signal to the ARM9 processing circuit for processing to judge the working state of the digital anti-interference baseband circuit, and transmits the digital anti-interference baseband circuit to inertial navigation through a serial port.

The satellite anti-interference antenna radio frequency part generates four paths of 46.52 +/-10.23 MHz Beidou intermediate frequency signals, the four paths of A/D conversion circuits convert the Beidou intermediate frequency signals into digital signals, the digital signals are sent to the FPGA anti-interference baseband processing circuit for anti-interference processing, and the anti-interference processed data are converted into analog Beidou intermediate frequency signals through the D/A conversion circuit.

The memory circuit core mainly comprises NANDFLASH, NORFLASH and SDRAM three memory chips, wherein the NANDFLASH is connected with the ARM9 microprocessor, and is mainly used for storing an anti-interference program of the FPGA anti-interference baseband processing circuit, and when the FPGA anti-interference baseband processing circuit is powered on, the FPGA anti-interference baseband processing circuit starts anti-interference work through loading the program of the boot of the ARM9 processing circuit; the NORFLASH chip is mainly used for storing ARM9 processing circuit application programs, and the application programs are mainly responsible for collecting and processing sampling data of the FPGA anti-interference baseband processing circuit on four paths of radio frequency channels, program on-line loading, power supply current detection and control functions of interface part separation and dispersion; SDRAM mainly stores the data of FPGA anti-interference baseband processing circuit and ARM9 processing circuit.

The interface circuit part mainly comprises two paths of RS232 level serial ports, two paths of RS422 level serial ports, controlled discrete quantity, an ARM9 processing circuit JTAG interface and a JTAG downloading interface of the FPGA anti-interference baseband processing circuit, wherein one path of RS232 serial ports are used for debugging and online program upgrading, one path of RS232 serial ports are used for reporting the working state of the four-channel anti-interference baseband circuit and communicating with external user data, one path of RS422 serial ports are used for interacting with the inertial navigation interface, and one path of RS422 serial ports are reserved.

The controlled discrete quantity is an I/O interface connected with the ARM9 processing circuit, and an external instruction is received through a serial port to control the discrete quantity so as to realize the direct locking function of the satellite anti-interference antenna; the two JTAG interfaces are mainly used for online debugging of the program.

As shown in fig. 2, a general four-channel digital anti-interference baseband circuit implementation method comprises the following steps: after the four-channel digital anti-interference baseband circuit is electrified, all circuit hardware starts to initialize, firstly an ARM9 processing circuit respectively reads ARM9 application programs and FPGA anti-interference processing program target codes of NORFLASH and NANDFLASH in a storage circuit through boot loading programs and loads the ARM9 application programs and the FPGA anti-interference processing program target codes into the ARM9 processing circuit and the FPGA anti-interference baseband processing circuit, and software programs start to run;

the input four-channel analog intermediate frequency signals are acquired into four-channel digital intermediate frequency signals through an A/D analog-to-digital conversion circuit, and the FPGA anti-interference baseband processing circuit anti-interference software respectively performs channel gain consistency and other influence factor self-adaptive compensation processing, digital down-conversion processing, low-pass filtering, weight generation iteration and updating, frequency domain filtering, secondary quantization and digital up-conversion processing on the four-channel intermediate frequency signals, and the up-converted digital intermediate frequency signals are converted into analog intermediate frequency signals through a D/A digital-to-analog conversion circuit, so that the digital anti-interference processing on the analog intermediate frequency signals is realized; when the anti-interference processing is carried out, ARM9 processing circuit application programs respectively read four-channel down-conversion data in a storage circuit SDRAM and carry out analysis processing, and the four-channel down-conversion data are sent to an upper computer interface for display through an RS232 interface in an interface circuit according to a related protocol, so that state information of the four-channel radio frequency front end is displayed in real time; ARM9 processing circuit gathers power supply current detection circuit detection information, judges anti-interference baseband circuit operating condition through the fault threshold that sets up, realizes the interaction with outside through shutting and the online loading user instruction of procedure through RS232 interface, RS422 interface and I/O mouth discrete quantity in the interface circuit.

On one hand, the invention realizes the design of direct current 9V-36V wide-range voltage input, overvoltage and undervoltage protection and various low-voltage value power supply conversion circuits, and can meet the requirements of machine/missile-borne satellite anti-interference antenna voltage input application and the requirements of part GJB181-1986 on-board power supply characteristics; on the other hand, ARM9 processing circuits are adopted to replace circuit designs of small-resource FPGA circuits, and in the design of interaction software with external users, high-level language is adopted to realize interface protocol conversion software, communication software with an upper computer interface, on-line program loading, power supply current detection functions and controlled through locking functions, compared with the design of FPGA hardware description language software, the method has the advantages of good program portability and convenience in implementation and maintenance; and the large-scale program and a large amount of data are stored for the ARM9 and the large-capacity FLASH chips outside the FPGA plug-in, so that the boot loading mode of the FPGA anti-interference program and the ARM9 application program is realized, and the requirement of large-scale anti-interference software on the real-time processing of the large amount of interference data is met.

The main technical indexes which can be achieved by the invention are as follows:

input voltage:	DC9V～36V；
			output DC ripple voltage:	<5%；
current sensing capability:	0～3A；
			power consumption:	≤8W；
62MHz input clock:	frequency accuracy: (+ -0.3 PPM (Normal temperature);
				clock error: (-50 to +50) Hz;
	level: LVTTL;
			ADC valid bit number:	≥9.5bit；
noise figure:	≤1dB；
			input/output intermediate frequency signal frequency:	46.52±10.23MHz；
output intermediate frequency signal out-of-band rejection:	-3dB bandwidth: 20.46MHz;
				-40dB bandwidth: 30.69MHz;
static protection:	IEC61000-4-2 level 4：
				15kV (air discharge);
	8kV (contact discharge);
				MIL STD 883E-Method 3015-7：class3
	25kV HBM (human body model);
			insulation resistance:	≥20MΩ；
trouble free run time:	≥50000h；
			ambient temperature:	－45～+60℃；
relative humidity:	(95.+ -. 3)% temperature 40 ℃.

Claims (2)

1. A universal four-channel digital anti-interference baseband circuit is characterized in that: the device comprises a DC/DC power supply conversion circuit, a power supply current detection circuit, a power supply protection circuit, an A/D analog-to-digital conversion circuit, a D/A digital-to-analog conversion circuit, a clock distribution circuit, an ARM9 processing circuit, an FPGA anti-interference baseband processing circuit, a clock and reset circuit, a storage circuit and an interface circuit;

the DC/DC power conversion circuit is respectively connected with the power current detection circuit, the power protection circuit, the A/D analog-to-digital conversion circuit, the D/A digital-to-analog conversion circuit, the clock distribution circuit, the ARM9 processing circuit, the FPGA anti-interference baseband processing circuit, the clock and reset circuit, the storage circuit and the interface circuit, the power protection circuit is connected with the power current detection circuit, the power current detection circuit is connected with the ARM9 processing circuit, the FPGA anti-interference baseband processing circuit is respectively connected with the A/D analog-to-digital conversion circuit, the clock distribution circuit, the D/A digital-to-analog conversion circuit, the storage circuit and the ARM9 processing circuit, and the clock distribution circuit is connected with the A/D analog-to-digital conversion circuit, and the ARM9 processing circuit is respectively connected with the clock and reset circuit, the storage circuit and the interface circuit;

the circuit firstly performs overvoltage and undervoltage protection on a power supply part through a power supply protection circuit, then converts the input 9V-36V direct current voltage into two paths of +5V voltages through a DC/DC power supply conversion circuit, one path of digital +5V supplies power to the whole digital anti-interference baseband circuit, the other path of analog +5V voltage is used as a reserved voltage to supply power to the satellite anti-interference antenna analog part, the digital +5V circuit is converted into four paths of voltages through a secondary power supply, the four paths of voltages are +3.3V, +1.8V, +1.2V and +1.0V respectively, and the +3.3V is the pin power supply voltage of the FPGA anti-interference baseband processing circuit and the ARM9 processing circuit; +1.8V mainly supplies power for the A/D analog-to-digital conversion circuit and the FPGA anti-interference baseband processing circuit; +1.2V and +1.0V are respectively the nuclear power supply of ARM9 processing circuit and FPGA anti-interference baseband processing circuit, the requirement on voltage precision is higher;

the power supply current detection circuit detects an input direct current power supply, sends a detected signal to the ARM9 processing circuit for processing to judge the working state of the digital anti-interference baseband circuit, and transmits the detected signal to inertial navigation through a serial port;

the satellite anti-interference antenna radio frequency part generates four paths of 46.52 +/-10.23 MHz Beidou intermediate frequency signals, the four paths of A/D conversion circuits convert the Beidou intermediate frequency signals into digital signals, the digital signals are sent to the FPGA anti-interference baseband processing circuit for anti-interference processing, and the anti-interference processed data are converted into analog Beidou intermediate frequency signals through the D/A conversion circuit;

the memory circuit core mainly comprises NANDFLASH, NORFLASH and SDRAM three memory chips, wherein the NANDFLASH is connected with the ARM9 microprocessor, and is mainly used for storing an anti-interference program of the FPGA anti-interference baseband processing circuit, and when the FPGA anti-interference baseband processing circuit is powered on, the FPGA anti-interference baseband processing circuit starts anti-interference work through loading the program of the boot of the ARM9 processing circuit; the NORFLASH chip is mainly used for storing ARM9 processing circuit application programs, and the application programs are mainly responsible for collecting and processing sampling data of the FPGA anti-interference baseband processing circuit on four paths of radio frequency channels, program on-line loading, power supply current detection and control functions of interface part separation and dispersion; SDRAM mainly stores the data of the FPGA anti-interference baseband processing circuit and ARM9 processing circuit;

the interface circuit part mainly comprises two paths of RS232 level serial ports, two paths of RS422 level serial ports, controlled discrete quantity, an ARM9 processing circuit JTAG interface and a JTAG download interface of the FPGA anti-interference baseband processing circuit, wherein one path of RS232 serial ports are used for debugging and online program upgrading, one path of RS232 serial ports are used for reporting the working state of the four-channel anti-interference baseband circuit and communicating with external user data, one path of RS422 serial ports are used for interacting with the inertial navigation interface, and one path of RS422 serial ports are reserved;

the controlled discrete quantity is an I/O interface connected with the ARM9 processing circuit, and an external instruction is received through a serial port to control the discrete quantity so as to realize the direct locking function of the satellite anti-interference antenna; the two JTAG interfaces are mainly used for online debugging of the program.

2. A method for implementing the universal four-channel digital anti-interference baseband circuit according to claim 1, comprising the steps of: after the four-channel digital anti-interference baseband circuit is electrified, all circuit hardware starts to initialize, firstly an ARM9 processing circuit respectively reads target codes of an ARM9 processing circuit application program and an FPGA anti-interference processing program in a storage circuit through a boot loader, the target codes are loaded into the ARM9 processing circuit and the FPGA anti-interference baseband processing circuit, and a software program starts to run;

the input four-channel analog intermediate frequency signal is acquired into a four-channel digital intermediate frequency signal through an A/D analog-to-digital conversion circuit, and anti-interference software of an FPGA anti-interference baseband processing circuit carries out channel gain consistency influence factor self-adaptive compensation processing, digital down-conversion processing, low-pass filtering, weight generation iteration and updating, frequency domain filtering, secondary quantization and digital up-conversion processing on the four-channel intermediate frequency signal respectively, and the up-converted digital intermediate frequency signal is converted into an analog intermediate frequency signal through a D/A digital-to-analog conversion circuit, so that the digital anti-interference processing of the analog intermediate frequency signal is realized; when the anti-interference processing is carried out, ARM9 processing circuit application programs respectively read four-channel down-conversion data in a storage circuit SDRAM and carry out analysis processing, and the four-channel down-conversion data are sent to an upper computer interface for display through an RS232 interface in an interface circuit according to a related protocol, so that state information of the four-channel radio frequency front end is displayed in real time; ARM9 processing circuit gathers power supply current detection circuit detection information, judges anti-interference baseband circuit operating condition through the fault threshold that sets up, realizes the interaction with outside user direct-connection shutting and procedure on-line loading instruction through RS232 interface, RS422 interface and I/O mouth discrete quantity in the interface circuit.