CN107888976B - Program upgrading device and upgrading method based on LVDS signal lines - Google Patents
Program upgrading device and upgrading method based on LVDS signal lines Download PDFInfo
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- CN107888976B CN107888976B CN201711157459.2A CN201711157459A CN107888976B CN 107888976 B CN107888976 B CN 107888976B CN 201711157459 A CN201711157459 A CN 201711157459A CN 107888976 B CN107888976 B CN 107888976B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs
- H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
- H04N21/440236—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display by media transcoding, e.g. video is transformed into a slideshow of still pictures, audio is converted into text
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/25—Management operations performed by the server for facilitating the content distribution or administrating data related to end-users or client devices, e.g. end-user or client device authentication, learning user preferences for recommending movies
- H04N21/262—Content or additional data distribution scheduling, e.g. sending additional data at off-peak times, updating software modules, calculating the carousel transmission frequency, delaying a video stream transmission, generating play-lists
- H04N21/26291—Content or additional data distribution scheduling, e.g. sending additional data at off-peak times, updating software modules, calculating the carousel transmission frequency, delaying a video stream transmission, generating play-lists for providing content or additional data updates, e.g. updating software modules, stored at the client
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/45—Management operations performed by the client for facilitating the reception of or the interaction with the content or administrating data related to the end-user or to the client device itself, e.g. learning user preferences for recommending movies, resolving scheduling conflicts
- H04N21/458—Scheduling content for creating a personalised stream, e.g. by combining a locally stored advertisement with an incoming stream; Updating operations, e.g. for OS modules ; time-related management operations
- H04N21/4586—Content update operation triggered locally, e.g. by comparing the version of software modules in a DVB carousel to the version stored locally
Abstract
The invention discloses a program upgrading device and method based on LVDS signal lines, comprising a signal generating device and a signal receiving device arranged in an object to be upgraded, wherein the signal generating device is connected with the signal receiving device through the LVDS signal lines; the signal generating device is used for receiving the upgrading file and converting the upgrading file into image data when a control signal on the LVDS signal line enters a frame blanking area; the image data updating device is used for calculating the number of data which can be sent by each frame blanking area and dividing the image data of the updating file into a plurality of sections according to the number of the data; each section of upgrading file data is sequentially sent to a signal receiving device through LVDS signal lines by utilizing each frame blanking area; and the signal receiving device integrates the received upgrade file data to obtain a complete upgrade file, and performs program upgrade operation according to the upgrade file. The invention upgrades the program without influencing the normal image display of the equipment, and has the advantages of high upgrading speed, high stability and reliability and the like.
Description
Technical Field
The invention belongs to the technical field of LVDS signal source communication, and particularly relates to a program upgrading device and method based on LVDS signal lines.
Background
The expansion box converts LVDS video signals output by the signal generator PG into video signals required by the liquid crystal display module, such as DP and VbyOne signals, so that the signal generator PG can adapt to different types of liquid crystal display modules, and the requirement on a signal source is reduced. Generally, when a program of the expansion box is found to be wrong or the liquid crystal display module cannot normally display, or the liquid crystal display module needs other different types of video signals to meet the display requirement, the program in the expansion box needs to be upgraded.
The existing upgrading method is mainly carried out through IIC/SPI/RS484/RS232 communication upgrading interfaces or the like, or programs in the expansion box are upgraded by adopting LVDS video signal lines, but the existing upgrading method has the following defects: the LVDS video signal line is mainly used for transmitting and displaying images and data, and the upgrade file transmitted by the LVDS video signal line occupies the transmission bandwidth of the displayed images and data, so that the expansion box cannot normally display the images in the process of program upgrade, and the expansion box can normally work only after the upgrade is finished.
Disclosure of Invention
Aiming at the defects or improvement requirements of the prior art, the invention provides a program upgrading device and method based on LVDS signal lines, which can upgrade programs without influencing normal image display of equipment and has the advantages of high upgrading speed, high stability and high reliability.
In order to achieve the above object, according to one aspect of the present invention, there is provided a program upgrading apparatus based on LVDS signal lines, comprising a signal generating device and a signal receiving device built in an object to be upgraded, the signal generating device being connected to the signal receiving device via the LVDS signal lines;
the signal generating device is used for receiving the upgrading file and converting the upgrading file into image data when a control signal on the LVDS signal line enters a frame blanking area; the image data updating device is used for calculating the number of data which can be sent by each frame blanking area and dividing the image data of the updating file into a plurality of sections according to the number of the data; each section of upgrading file data is sequentially sent to a signal receiving device through LVDS signal lines by utilizing each frame blanking area;
the signal receiving device integrates the received upgrade file data to obtain a complete upgrade file, and carries out program upgrade operation according to the upgrade file.
Preferably, the program upgrading device based on LVDS signal lines further includes a first memory and a second memory; the first memory is communicated with the signal generating device and used for storing the upgrade file received by the signal generating device; the second memory is communicated with the signal receiving device and used for storing the upgrade file integrated by the signal receiving device.
Preferably, in the program upgrading device based on LVDS signal lines, the signal generating device includes a processor and a first FPGA that communicate with each other, the first FPGA communicates with the signal receiving device through the LVDS signal lines, and the first memory is connected to the first FPGA;
the processor is used for sequentially receiving the upgrade files sent by the external upper computer in the form of a plurality of data packets, forwarding the upgrade files to the first FPGA, and controlling the first FPGA to perform caching, reading and unpacking operations;
the first FPGA is used for unpacking the received multiple data packets and splicing data in the data packets to obtain an upgrade file; the system is used for converting the upgrade file into a bit width form of image data and replacing the control signal on the LVDS signal line with the image data when the control signal enters a frame blanking area; the image data updating device is used for calculating the number of data which can be sent by each frame blanking area and dividing the image data of the updating file into a plurality of sections according to the number of the data; and sequentially sending each section of upgrading file data to a signal receiving device through LVDS signal lines by utilizing each frame blanking area.
Preferably, the processor of the program upgrading device based on LVDS signal lines is further configured to calculate whether the received data packet is correct; if yes, sending packet information back to an external upper computer to request to send a next data packet; if not, sending packet information back to an external upper computer, requesting to retransmit the data packet, controlling the first FPGA to eliminate the error data packet and caching the retransmitted data packet; after all the data packets are received, sending the received packet returning information to an external upper computer;
before sending upgrade file data, the first FPGA sends initial mark data, serial number mark data of the upgrade file data and data number, and then sends each data of the upgrade file data one by one; and after the upgrade file data is sent, sending a finish mark and verification data.
Preferably, the signal receiving device of the program upgrading device based on the LVDS signal line includes a second FPGA and an MCU, the second FPGA communicates with the first FPGA through the LVDS signal line, the MCU establishes communication connections with the second FPGA and the processor, respectively, and the second memory is connected to the second FPGA;
the second FPGA is used for receiving each section of upgrading file data sent by the first FPGA in each frame blanking area in sequence and integrating each section of received upgrading file data to obtain a complete upgrading file; and is used for calculating whether the received upgrade file data of each section is correct or not, if so, informing the processor of sending the next section of upgrade file data through the MCU; if not, informing the processor to resend the upgrade file data through the MCU; and after the data of all the upgrade files are received, feeding back a receiving completion state to the processor through the MCU.
Preferably, the signal receiving device of the program upgrading device based on the LVDS signal line further includes a FLASH chip connected to the second FPGA;
the second FPGA comprises an LVDS signal receiving module, a memory control logic module and an upgrading module which are sequentially connected, the LVDS signal receiving module, the upgrading module and the second memory are communicated with the memory control logic module, and the FLASH chip is connected with the upgrading module;
the LVDS signal receiving module is used for receiving upgrade file image data transmitted by the first FPGA; the memory control logic module is used for caching the received image data of the upgrade file into a second memory; the upgrading module is used for reading the upgrading file image data in the second memory and converting the upgrading file image data into a signal form and a time sequence required by the FLASH chip;
the upgrading module comprises an ASMI control submodule, an ASMI cache submodule and an upgrading interface submodule, wherein the ASMI cache submodule and the upgrading interface submodule are communicated with the ASMI control submodule; and the FLASH chip is connected with the upgrading interface submodule.
Preferably, in the program upgrading device based on the LVDS signal lines, when the FPGA program in the object to be upgraded is upgraded, the second FPGA converts the upgrade file into a configuration format required by the upgrade module, and sends the file size, the upgrade enable signal and the file address to the ASMI control submodule, writes the upgrade data of the corresponding address into the ASMI cache submodule, and controls the upgrade interface submodule to convert the upgrade data into a signal form and a timing sequence required by the FLASH chip, and writes the signal form and the timing sequence into the FLASH chip;
when the MCU program in the object to be upgraded is upgraded, the second FPGA converts the upgrade file into the file format and the data coding form of the MCU program, and the converted upgrade file is burned into the EEPROM of the MCU according to the upgrade time sequence.
According to another aspect of the present invention, there is provided a program upgrading method based on LVDS signal lines, including the steps of:
s1: acquiring an upgrade file, converting the upgrade file into a bit width form of image data, and replacing a control signal on an LVDS signal line with the image data when the control signal enters a frame blanking area;
s2: calculating the number of data which can be sent by each frame blanking area, and dividing the image data of the upgrade file into a plurality of sections according to the number of the data;
s3: sequentially sending each section of upgrading file data to an object to be upgraded through LVDS signal lines by utilizing each frame blanking area;
s4: and integrating the received upgrade file data to obtain a complete upgrade file, and carrying out program upgrade operation on the object to be upgraded according to the received upgrade file.
Preferably, the program upgrading method further includes, before the step S1, the following steps:
s01: acquiring an upgrade file, dividing the upgrade file into a plurality of data packets and outputting the data packets;
s02: and sequentially receiving the plurality of data packets, unpacking the data packets, and splicing the data in each data packet to obtain a complete upgrade file.
Preferably, in the program upgrading method, when the object to be upgraded is an FPGA program, the upgrade file is converted into a configuration format required by the FPGA; and writing the file size, the upgrade enabling signal, the upgrade address and the upgrade data of the converted upgrade file into the FPGA in sequence.
Preferably, in the program upgrading method, when the object to be upgraded is an MCU program, the upgrade file is converted into a file format and a data coding format required by the MCU, and the converted upgrade file is burned into the MCU according to an upgrade timing sequence.
Preferably, in the program upgrading method, step S02 includes the following steps: calculating whether the received data packet is correct, if so, continuing to send the next data packet; if not, clearing the error data packet and retransmitting; and sending receiving completion state information after all the data packets are received.
Preferably, in the program upgrading method, step S3 includes the following steps: before each section of upgrading file data is sent, firstly sending initial mark data, serial number mark data of the section of upgrading file data and data number, and then sending each data of the section of upgrading file one by one; and after the upgrade file data is sent, sending a finish mark and verification data.
Preferably, the program upgrading method further includes, before the step S4, the following steps: calculating whether the received upgrade file data of each section is correct or not, and if so, sending the next section of upgrade file data; if not, retransmitting the upgrade file data; and after all the upgrade file data are received, sending a receiving completion state.
In general, compared with the prior art, the above technical solution contemplated by the present invention can achieve the following beneficial effects:
(1) the invention provides a program upgrading device and method based on LVDS signal lines, which utilize the LVDS signal lines to upgrade programs, before the upgrade files are sent, a signal generator firstly converts the upgrade files into the bit width form of image data, and the upgrade files are transmitted when each frame of control signals in the LVDS signal lines enter a blanking area, at the moment, no image data is sent on the LVDS signal lines, the transmission bandwidth and gaps are fully utilized, the upgrade files are prevented from being transmitted to influence the normal image data transmission of an expansion box, and the normal point screen display of the expansion box is not influenced; the transmission of the upgrade file is carried out by utilizing the LVDS signal interface to carry out the transmission of the display image data, the utilization rate of the LVDS signal interface is improved, and the IIC/SPI/RS484/RS232 communication interfaces and the like are not occupied;
(2) according to the program upgrading device and method based on the LVDS signal lines, the upgrading file is transmitted to the signal generator from the computer in the form of a plurality of data packets, the signal generator calculates and verifies each received data packet, and the correctness of the upgrading file is guaranteed; the upgrade file is sent to the expansion box from the signal generator in a form of a plurality of data segments, and the expansion box carries out calculation and verification on each received data segment, so that the reliability of the upgrade file is ensured; the problem of upgrading failure or crash caused by transmission errors is avoided;
(3) according to the program upgrading device and method based on the LVDS signal lines, the FPGA in the signal generator sends the lead code data before upgrading starts, the upgrading program is started only when the lead code data received by the FPGA in the expansion box is completely consistent with the content specified by a user, the situation that the burnt data is damaged due to the fact that the signal generator sends a re-upgrading command after the expansion box is upgraded is avoided, the signal generator is greatly prevented from mistakenly burning the expansion box, and upgrading reliability is improved.
Drawings
Fig. 1 is a block diagram of a program upgrading apparatus based on LVDS signal lines according to an embodiment of the present invention;
FIG. 2 is a block diagram of internal modules of an A5 chip according to an embodiment of the present invention;
fig. 3 is a block diagram of internal modules of an upgrade module in the a5 chip according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
FIG. 1 is a block diagram of a program upgrading apparatus based on LVDS signal lines; the program upgrading device based on the LVDS signal line is used for upgrading an FPGA or MCU program in an extension box and comprises a computer and a signal generator which are connected through a network cable, wherein the signal generator and the extension box are connected through the LVDS signal line, and the program upgrading device further comprises a first memory and a second memory which are respectively connected with the signal generator and the extension box;
the computer is used for acquiring an original upgrading file, dividing the original upgrading file into a plurality of data packets and sequentially sending the data packets to the signal generator through the network cable;
the signal generator is used for unpacking the received data packets, splicing the data in each data packet to obtain an original upgrade file, and storing the original upgrade file in a first memory connected with the signal generator; the system is used for converting the original upgrade file into image data when a control signal on the LVDS signal line enters a frame blanking area; the system is used for sending out test mark data and counting to obtain the number of data which can be sent by each frame blanking area, and dividing the image data of the original upgrade file into a plurality of sections according to the number of the data; sequentially sending each section of image data to the expansion box through LVDS signal lines by utilizing a frame blanking area;
the expansion box integrates the received image data to obtain an original upgrade file, and stores the original upgrade file in a second memory connected with the expansion box, and the object to be upgraded in the expansion box performs program upgrade operation according to the received original upgrade file.
The signal generator comprises a processor and a first FPGA, one end of the processor is connected with the computer through a network cable, the other end of the processor is connected with a first end of the first FPGA through an EBI bus, a second end of the first FPGA is connected with the expansion box through an LVDS signal wire, and a third end of the first FPGA is connected with the first memory; in this embodiment, a signal generator of model PG108E is selected, the processor is an ARM chip, and the first FPGA is a Spartan6 chip (hereinafter referred to as S6); DDR3 memory particles are selected as the first memory;
the expansion box is in the model of AMEX01B, the expansion box is provided with a K60 chip, an ArriaV chip (hereinafter referred to as A5) and a Flash EPCQ256 chip, a first end of the A5 chip is connected with a second end of the S6 chip through an LVDS signal line, the second end is connected with a first end of the K60 chip through an EBI bus, a third end is connected with a second memory, and a fourth end is connected with the Flash EPCQ256 chip; the second end of the K60 chip is connected with an ARM chip in the signal generator through a 485 serial port line; the second memory adopts DDR3 memory granules.
FIG. 2 is a block diagram of internal modules of an A5 chip according to an embodiment of the present invention; as shown in fig. 2, the a5 chip includes an LVDS signal receiving module, a memory control logic module and an upgrade module connected in sequence, where the LVDS signal receiving module is connected to the S6 chip through an LVDS signal line and is configured to receive upgrade file image data transmitted through the LVDS signal line; the memory control logic module is connected with the second memory DDR3 and is used for caching the upgrade file image data received by the LVDS signal receiving module into the second memory DDR 3; the upgrading module is connected with the FLASH EPCQ256 chip and used for reading the image data of the upgrading file in the second memory DDR3 and converting the image data of the upgrading file into the signal form and the time sequence required by the FLASH EPCQ256 chip.
FIG. 3 is a block diagram of the internal modules of the upgrade module in the A5 chip according to an embodiment of the present invention; the RSU upgrading module comprises an ASMI control module, an ASMI cache module and an upgrading interface sub-module, one end of each of the ASMI cache module and the upgrading interface sub-module is connected with the ASMI control module, and the other end of the upgrading interface sub-module is connected with the FLASH chip;
when a user needs to remotely upgrade the MCU program in the K60 chip or the FPGA program in the A5 chip, an upgrade file, such as a bin file of the FPGA or the MCU, is read by upper control software in the computer, the upgrade file is formed into a plurality of data packets and is sent to the ARM chip through a network cable in sequence, and after the ARM chip receives the data packets, packet information is sent to the upper control software of the computer.
In order to improve the integrity and the correctness of the upgrade file in the transmission process, the computer and the ARM chip adopt a mode of sending a packet and returning the packet at the same time, namely, when the computer sends one data packet to the ARM chip, the ARM chip forwards the received data packet to the S6 chip through the EBI bus, and after the S6 chip caches the data packet in the first memory DDR3, a state mark is returned to the ARM chip; the ARM chip reads parameters such as a packet header, a length, a check code and the like in the data packet through the EBI bus control S6 chip, and confirms whether the received data packet is correct through calculation, if so, the ARM chip sends the data packet back to the computer to request to send the next data packet; when the ARM chip finds that the data packet received at this time has errors through calculation, the ARM chip sends the data packet back to the computer to request to retransmit the data packet; the computer resends the current data packet, the ARM chip controls the S6 chip to clear the error data packet cached last time and resend the cached data packet, and similarly, the ARM chip needs to recalculate whether the data packet is correct or not. When all data packets are received by the ARM chip and cached in the first memory DDR3, the ARM chip sends packet returning information of a receiving completion state to the computer, and the user department obtains the sending completion information through the computer. By the operation, the reliability of the upgrade file in the transmission process can be ensured, and the problem of upgrade failure or crash caused by transmission errors is avoided.
The ARM chip controls the S6 chip to unpack each upgrade file data packet cached in the first memory DDR3, data in each data packet are spliced together to restore to obtain an original upgrade file, and the original upgrade file is cached in the first memory DDR3 again; and the FPGA is adopted for unpacking and data merging operation, so that the speed of restoring the original upgrade file is greatly improved.
The S6 chip sends the upgrade file to the expansion box through LVDS signal lines to upgrade the FPGA or MCU program in the expansion box. Because the LVDS signal line is used for transmitting image data and time sequence in real time, and the normal dot screen display of the expansion box cannot be influenced in the upgrading process, before the upgrading file is sent, the S6 chip converts the upgrading file into a bit width form of the image data, the image data is 10bit wide according to R, G, B each color, the S6 chip converts the upgrading file into a parallel data form with 30bit wide, and when each frame of control signal in the LVDS signal line enters a blanking area, the converted original file is replaced by the image data, at the moment, no image data is sent on the LVDS signal line, and the data transmitted in each frame of blanking area on the LVDS signal line is the upgrading file data.
Before sending the upgrade file data, when the VSync enters a frame blanking area, the S6 chip continuously sends out test mark data, which do not exceed 8 bits, such as F0F0, FAFA and the like, counts the number of the sent test marks, and when the VSync exits the frame blanking area, the data volume which can be sent in each frame blanking area in the current display image is obtained. Because the expansion box AMEX01B can support displaying images of different types, parameters and resolutions, the length of the frame blanking area of each display image has difference, in order to fully utilize transmission bandwidth and gap and avoid the transmission of the upgrade file from influencing the normal image data transmission of the expansion box, it is necessary to firstly confirm how many data can be sent by different frame blanking areas, after the frame blanking area is finished, the image data of the upgrade file is divided into a plurality of sections according to the number of data that can be sent in each frame blanking area, and the image data of each section of the upgrade file is sent in each subsequent frame blanking area in turn.
When entering the blanking area of the next frame, the S6 chip starts to send the first segment of upgrade file, and before sending, sends an initial flag data, such as 55AA, but it must be different from the data bit number of the test flag data, to ensure that the receiving end can correctly distinguish the test flag data from the initial flag data; sending a serial number mark data, namely, indicating that the currently sent data segment is the data of the second segment of the upgrade file, sending the number of the data of the upgrade file, sending each data of the upgrade file one by one, and sending a mark indicating whether the upgrade file is completely sent after the sending is finished; finally, sending check data, namely, calculating according to all the sent marks and the image data to obtain the check data; it should be noted that the number of data of the upgrade file should be the total number of data sent this time minus the number of sent flags and checks; when the blanking area of the VSync of each frame is finished, the S6 chip has sent out all the current segment upgrade files, and the LVDS signal lines are still used for continuously transmitting the display image data and the timing sequence, and do not affect the dot screen display of the expansion box. When the next frame blanking area begins, the S6 chip sends the next segment of the upgrade file and its corresponding flag and check data.
An A5 chip in the expansion box detects whether an upgrade file is input when entering a frame blanking area, and performs preparation work after receiving test flag data, wherein the preparation work comprises clearing the area position used for caching the upgrade file in a second memory DDR3, informing a K60 chip of preparation and initializing an internal upgrade module RSU; when entering the frame blanking area of the next frame, the first section of upgrade file, the end mark and the check data are received in sequence after the start mark data is confirmed to be received, and the upgrade file, the end mark and the check data are cached to the designated area position in the second memory DDR 3. After receiving, the A5 chip performs normal image receiving, decoding and displaying operations, and simultaneously takes out the current section of upgrade file cached in the second memory DDR3, calculates and compares the current section of upgrade file with the check data, if the received data is confirmed to be correct, the K60 chip is informed of correct receiving, the K60 chip informs the ARM chip of transmitting the next section of upgrade file data through a 485 serial port line, and the ARM chip instructs the S6 chip to issue the next section of upgrade file to the A5 chip in the blanking area of the next frame; if the A5 chip finds that the current segment of upgrade file data is wrong, the K60 chip informs the ARM chip to retransmit the segment of upgrade file data, and the S6 chip retransmits the segment of upgrade file data in the blanking area of the next frame.
When the A5 chip correctly receives all the upgrade file data and caches the upgrade file data in the second memory DDR3, the reception completion state is fed back to the ARM chip through the K60 chip, the ARM chip instructs the S6 chip to stop sending on one hand, and on the other hand, the reception completion state is reported to upper control software of the computer, and a user can obtain the reception completion state through the computer.
The A5 chip integrates the received upgrade file data into a complete upgrade file, when the object to be upgraded is an FPGA program in the A5 chip, the A5 chip executes write operation on the upgrade module, and the upgrade file in the second memory DDR3 is converted into a configuration format required by the upgrade module, such as data forms of upgrade data, upgrade address, upgrade file size and the like; then informing the ASMI control submodule in the upgrading module of the size of the upgrading file, sending an upgrading enabling signal to the ASMI control submodule, and then respectively writing the upgrading address and upgrading data of the corresponding address into the ASMI control and ASMI cache submodule in the upgrading module; the ASMI control sub-module automatically controls the ASMI upgrade interface sub-module to convert the upgrade data into the signal form and timing required by the Flash EPCQ256 chip and burn it into the chip. After the data of all the upgrade files are completely burned, the A5 chip sends state information to inform the K60 chip that the burning is completed, the K60 chip controls a power supply circuit of the A5 chip to power off after a period of time is delayed after receiving the state information sent by the A5 chip to ensure that the burning process inside the EPCQ256 chip is completely completed, the A5 chip is powered on and reset again and initializes the internal logic of the FPGA, the A5 chip feeds back the completion state to the K60 chip after the initialization is completed, the K60 chip reads a new device identification number and a new program version number of the A5 chip and feeds back the new device identification number and the new program version number to the ARM chip, the ARM chip informs a user of the new version number and the new device label number through a.
When an object to be upgraded is an MCU program in a K60 chip, an A5 chip converts an upgrade file in a second memory DDR3 into a file format and a data coding form required by a K60 chip, and informs an ARM chip through the K60 chip, the ARM chip feeds back a command of delaying for a plurality of times to upgrade to an A5 chip through a K60 chip, the A5 chip starts delaying, the ARM chip controls the K60 chip to enter an upgrade state during the delay, the upgrade state is controlled and completed generally for hundreds of ms, and after the delay is over, the A5 chip burns upgrade file data into an E2PROM of the K60 chip according to the upgrade time sequence of the K60 chip; before upgrading, the ARM chip firstly estimates the time required by the upgrading of the K60 chip, the estimated time is generally slightly larger than the actual upgrading time of the K60 chip, in the upgrading process, the ARM chip inquires the state of the K60 chip on one hand, and times the upgrading time on the other hand, when the time counted by the ARM chip reaches the estimated time, the A5 chip is in a waiting state after finishing upgrading, the ARM chip restarts the K60 chip, the version number and the device number are fed back to a computer through the ARM chip, and the K60 chip finishes upgrading.
The invention also provides a program upgrading method based on the program upgrading device, which comprises the following steps:
s1: reading an upgrade file through upper control software in a computer, dividing the upgrade file into a plurality of data packets, and sequentially sending the data packets to a signal generator through a network cable;
s2: the signal generator sequentially receives the data packets and stores the data packets in a first memory connected with the signal generator; calculating whether the received data packet is correct, if so, continuing to send the next data packet; if not, clearing the error data packet and retransmitting; sending receiving completion state information after all the data packets are received; unpacking all the data packets, and splicing the data in each data packet to obtain a complete upgrade file;
s3: the signal generator converts the upgrade file into a bit width form of image data and replaces the upgrade file with the image data when a control signal on the LVDS signal line enters a frame blanking area;
s4: sending test mark data and counting to obtain the number of data which can be sent by each frame blanking area, and dividing the image data of the upgrade file into a plurality of sections according to the number of the data;
s5: sequentially transmitting each section of upgrading file data to an object to be upgraded through LVDS signal lines by utilizing each frame blanking area; before each section of upgrading file data is sent, firstly sending initial mark data, serial number mark data of the section of upgrading file data and data number, and then sending each data of the section of upgrading file one by one; after the upgrade file data is sent, sending a finish mark and verification data;
s6: the expansion box receives each section of upgrading file data in sequence, calculates whether the received data is correct, and sends the next section of upgrading file data if the received data is correct; if not, retransmitting the upgrade file data; after all the upgrade file data are received, sending a receiving completion state; integrating the received upgrade file data to obtain a complete upgrade file, and storing the complete upgrade file in a second memory connected with the expansion box;
s7: when the FPGA program in the expansion box is upgraded, the second FPGA converts the upgrade file into a configuration format required by an upgrade module, sends the file size, an upgrade enable signal and a file address to the ASMI control submodule, writes the upgrade data of the corresponding address into the ASMI cache submodule, controls the upgrade interface submodule to convert the upgrade data into a signal form and a time sequence required by a FLASH chip, and writes the signal form and the time sequence into the FLASH chip; after burning, the FPGA carries out internal logic initialization, and feeds back the device mark number and the program version number of the FPGA to a user, and upgrading is completed.
S8: when the MCU program in the expansion box is upgraded, the second FPGA converts the original upgrade file into the file format and the data coding form of the MCU program, the converted original upgrade file is burnt into the EEPROM of the MCU according to the upgrade time sequence, after the burning is finished, the MCU is restarted and the version number and the device number are fed back to a user, and the upgrading is finished.
Compared with the existing program upgrading method, the program upgrading device and the upgrading method based on the LVDS signal lines provided by the invention have the advantages that the normal image display of equipment is not influenced when the program is upgraded, the upgrading speed is high, the stability is high, the reliability is high and the like.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A program upgrading device based on LVDS signal lines is characterized by comprising a signal generating device and a signal receiving device arranged in an object to be upgraded, wherein the signal generating device is connected with the signal receiving device through the LVDS signal lines;
the signal generating device is used for receiving an upgrading file and converting the upgrading file into image data when a control signal on the LVDS signal line enters a frame blanking area; the system is used for sending out test mark data and counting after entering a frame blanking area, calculating the number of data which can be sent by each frame blanking area, and dividing the image data of the upgrade file into a plurality of sections according to the number of the data; each section of upgrading file data is sequentially sent to a signal receiving device through LVDS signal lines by utilizing each frame blanking area;
and the signal receiving device integrates the sequentially received upgrade file data to obtain a complete upgrade file, and performs program upgrade operation according to the upgrade file.
2. The LVDS signal line-based program upgrade device according to claim 1, further comprising a first memory and a second memory; the first memory is communicated with the signal generating device and used for storing the upgrade file received by the signal generating device; the second memory is communicated with the signal receiving device and used for storing the upgrade file integrated by the signal receiving device.
3. The program upgrading device based on LVDS signal lines according to claim 1 or 2, wherein the signal generating device comprises a processor and a first FPGA which are communicated with each other, the first FPGA is communicated with the signal receiving device through the LVDS signal lines, and the first memory is connected with the first FPGA;
the processor is used for sequentially receiving the upgrade files sent by the external upper computer in the form of a plurality of data packets, forwarding the upgrade files to the first FPGA, and controlling the first FPGA to perform caching, reading and unpacking operations;
the first FPGA is used for unpacking the received multiple data packets and splicing data in the data packets to obtain an upgrade file; the system is used for converting the upgrade file into a bit width form of image data and replacing the control signal on the LVDS signal line with the image data when the control signal enters a frame blanking area; the image data updating device is used for calculating the number of data which can be sent by each frame blanking area and dividing the image data of the updating file into a plurality of sections according to the number of the data; and sequentially sending each section of upgrading file data to a signal receiving device through LVDS signal lines by utilizing each frame blanking area.
4. The program upgrading device based on LVDS signal lines according to claim 3, wherein the signal receiving device comprises a second FPGA and an MCU, the second FPGA communicates with the first FPGA through the LVDS signal lines, the MCU establishes communication connection with the second FPGA and the processor respectively, and a second memory is connected with the second FPGA;
the second FPGA is used for receiving each section of upgrading file data sent by the first FPGA in each frame blanking area in sequence and integrating each received section of upgrading file data to obtain a complete upgrading file; the MCU is used for calculating whether the received upgrade file data of each section is correct or not, and if so, informing the processor of sending the next section of upgrade file data through the MCU; if not, informing the processor to resend the upgrade file data through the MCU; and after the data of all the upgrade files are received, feeding back a receiving completion state to the processor through the MCU.
5. The LVDS signal line-based program upgrading device according to claim 4, wherein the signal receiving device further comprises a FLASH chip connected to the second FPGA;
the second FPGA comprises an LVDS signal receiving module, a memory control logic module and an upgrading module which are sequentially connected, the LVDS signal receiving module, the upgrading module and the second memory are communicated with the memory control logic module, and the FLASH chip is connected with the upgrading module;
the LVDS signal receiving module is used for receiving upgrade file image data transmitted by the first FPGA; the memory control logic module is used for caching the received image data of the upgrade file into a second memory; the upgrading module is used for reading the upgrading file image data in the second memory and converting the upgrading file image data into a signal form and a time sequence required by the FLASH chip;
the upgrading module comprises an ASMI control submodule, an ASMI cache submodule and an upgrading interface submodule, wherein the ASMI cache submodule and the upgrading interface submodule are communicated with the ASMI control submodule; and the FLASH chip is connected with the upgrading interface submodule.
6. A program upgrading method based on LVDS signal lines is characterized by comprising the following steps:
s1: acquiring an upgrade file, converting the upgrade file into a bit width form of image data, and replacing a control signal on an LVDS signal line with the image data when the control signal enters a frame blanking area;
s2: sending test mark data and counting after entering a frame blanking area, calculating the number of data which can be sent by each frame blanking area, and dividing the image data of the upgrade file into a plurality of sections according to the number of the data;
s3: sequentially sending each section of upgrading file data to an object to be upgraded through LVDS signal lines by utilizing each frame blanking area;
s4: and integrating the sequentially received upgrade file data to obtain a complete upgrade file, and carrying out program upgrade operation on the object to be upgraded according to the received upgrade file.
7. The program upgrading method of claim 6, wherein step S1 is preceded by the steps of:
acquiring an upgrade file, dividing the upgrade file into a plurality of data packets and outputting the data packets;
and sequentially receiving the plurality of data packets, unpacking the data packets, and splicing the data in each data packet to obtain a complete upgrade file.
8. The program upgrading method according to claim 6 or 7, wherein when the object to be upgraded is an FPGA program, the upgrade file is converted into a configuration format required by the FPGA; writing the file size, the upgrade enabling signal, the upgrade address and the upgrade data of the converted upgrade file into the FPGA in sequence;
and when the object to be upgraded is an MCU program, converting the upgrade file into a file format and a data coding form required by the MCU, and burning the converted upgrade file into the MCU according to an upgrade time sequence.
9. The program upgrading method of claim 7, further comprising the steps of: calculating whether the received data packet is correct, if so, continuing to send the next data packet; if not, clearing the error data packet and retransmitting; and sending receiving completion state information after all the data packets are received.
10. The program upgrading method of claim 6, wherein the step S3 includes the steps of: before each section of upgrading file data is sent, firstly sending initial mark data, serial number mark data of the section of upgrading file data and data number, and then sending each data of the section of upgrading file one by one; and after the upgrade file data is sent, sending a finish mark and verification data.
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| CN109002306A (en) * | 2018-06-25 | 2018-12-14 | 深圳市创鑫激光股份有限公司 | Method for upgrading software, upgrading terminals, laser marking machine and laser marking system |
| CN111866363B (en) * | 2019-04-26 | 2022-05-31 | 杭州海康威视数字技术股份有限公司 | Camera remote upgrading method and device, electronic equipment and readable storage medium |
| CN110769207B (en) * | 2019-11-19 | 2022-04-01 | 深圳开立生物医疗科技股份有限公司 | Electronic endoscope signal transmission method, device, equipment and system |
| CN112416404A (en) * | 2020-11-24 | 2021-02-26 | 东莞埃科思科技有限公司 | 3D module system upgrading method and device, electronic equipment and medium |
| CN114978898B (en) * | 2022-05-12 | 2024-04-12 | 泽景(西安)汽车电子有限责任公司 | Data transmission control method and device, head-up display and storage medium |
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