CN107872269A - Multifrequency digital micro repeater - Google Patents

Multifrequency digital micro repeater Download PDF

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Publication number
CN107872269A
CN107872269A CN201610854672.8A CN201610854672A CN107872269A CN 107872269 A CN107872269 A CN 107872269A CN 201610854672 A CN201610854672 A CN 201610854672A CN 107872269 A CN107872269 A CN 107872269A
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CN
China
Prior art keywords
analog
circuit module
signal
radio frequency
module
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CN201610854672.8A
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Chinese (zh)
Inventor
闵海军
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Rosenberger Technologies Co Ltd
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Rosenberg (shanghai) Telecom Technology Co Ltd
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Application filed by Rosenberg (shanghai) Telecom Technology Co Ltd filed Critical Rosenberg (shanghai) Telecom Technology Co Ltd
Priority to CN201610854672.8A priority Critical patent/CN107872269A/en
Publication of CN107872269A publication Critical patent/CN107872269A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B7/00Radio transmission systems, i.e. using radiation field
    • H04B7/14Relay systems
    • H04B7/15Active relay systems
    • H04B7/155Ground-based stations
    • H04B7/15528Control of operation parameters of a relay station to exploit the physical medium
    • H04B7/15542Selecting at relay station its transmit and receive resources
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04WWIRELESS COMMUNICATION NETWORKS
    • H04W88/00Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
    • H04W88/08Access point devices
    • H04W88/10Access point devices adapted for operation in multiple networks, e.g. multi-mode access points

Abstract

Present invention is disclosed a kind of multifrequency digital micro repeater, including first medium multiplefrequency mixer and second medium multiplefrequency mixer, for being filtered, separating to link signal;At least one first radio frequency analog amplification circuit module and the second radio frequency analog amplification circuit module, for being filtered, amplifying to the link signal after filtering, separating;At least one first D/A converting circuit module and at least one second D/A converting circuit module, for the link signal after filtering, amplifying mutually change between data signal and analog signal;And FPGA module, for being extracted to data signal, interpolation, shaping filter processing;The present invention has merged GSM/DCS/WCDMA/TD_LTE systems based on FPGA module, can realize the signal transacting of multiple frequency bandwidths, realizes that 2G/3G/4G signals cover, has the advantages of integrated level is high, cost is low.

Description

Multifrequency digital micro repeater
Technical field
The present invention relates to a kind of mobile communication technology field, more particularly, to a kind of multifrequency digital micro repeater.
Background technology
With the fast development of Mobile Communications Market, user increasingly wishes that high quality communication can be provided whenever and wherever possible.For This, mobile communication service business starts to be difficult to the blind area design repeater that covers in outdoor, the inferior electric wave of interior of building and ground, with Meets the needs of user is for session services to greatest extent.
Common, Mobile communication direct base station type includes GSM Mobile communication direct base statioies, cdma mobile communication repeater etc., Mobile communication direct base station provides different detailed settlement projects for various signal blind zones, and its accommodation is as follows:Extension of service model Enclose, the signal blind zone for eliminating the obstacles such as coverage hole, such as high mountain, building, the woods and being formed;Strengthen field strength in suburb, expand The covering at big suburb station;Set up along highway, enhancing covering efficiency;Solves in-door covering, as signal declines in building The deamplification such as cut signal blind area, underground commercial center, subway, tunnel blind area;The signal of idle base station is guided into covering for busy base station In cover region, realize to dredge and hurry;Other regions that can not be directed through signal because of shielding etc..
With the high speed development of mobile communication, repeater is only capable of realizing single using more and more extensive in traditional repeater Individual or two band bandwidths are handled, and hardware design is complicated, cost is high, can not meet the needs of the communication network development, Therefore, it is necessary to wireless digital Miniature repeater designed for multifrequency multi-standard.
The content of the invention
The defects of it is an object of the invention to overcome prior art, there is provided a kind of multifrequency digital micro repeater, it is described more Frequency word Miniature repeater has merged GSM/DCS/WCDMA/TD_LTE systems, at the signal that can realize multiple frequency bandwidths Reason, finally realize that 2G/3G/4G signals cover, there is the advantages of integrated level is high, cost is low.
To achieve the above object, the present invention proposes following technical scheme:A kind of multifrequency digital micro repeater, including
First medium multiplefrequency mixer and second medium multiplefrequency mixer, for being filtered, separating to link signal;
At least one first radio frequency analog amplification circuit module and the second radio frequency analog amplification circuit module, for filter Link signal after ripple, separation is filtered, amplified;
At least one first D/A converting circuit module and at least one second D/A converting circuit module, for filtering, Link signal after amplification mutually changed between data signal and analog signal;And
FPGA module, for being extracted to data signal, interpolation, shaping filter processing;
The first radio frequency analog amplification circuit module and first medium multiplefrequency mixer, and the first D/A converting circuit Module is connected;
The FPGA module and the first D/A converting circuit module, and the second D/A converting circuit module are connected;Institute The second radio frequency analog amplification circuit module and the second D/A converting circuit module are stated, and second medium multiplefrequency mixer is connected Connect.
Preferably, the first radio frequency analog amplification circuit module include the first rf analog front-end amplification circuit module and First radio frequency analog rear end amplification circuit module, the first rf analog front-end amplification circuit module include at least one amplification Device and SAW filter, the first radio frequency analog rear end amplification circuit module include at least one amplifier harmony surface filtering Device.
Preferably, the second radio frequency analog amplification circuit module include the second rf analog front-end amplification circuit module and Second radio frequency analog rear end amplification circuit module, the second radio frequency analog rear end amplification circuit module include at least one amplification Device and SAW filter, the second rf analog front-end amplifying circuit include at least one amplifier and SAW filter.
Preferably, the first analog to digital conversion circuit module includes being used to convert analog signals into the first of data signal ADC analog to digital conversion circuits module and the first DAC D/A converting circuit modules for converting digital signals into analog signal.
Preferably, the first ADC analog to digital conversion circuits module includes low-noise amplifier, the IQ orthogonal modulations being connected Device, frequency mixer, amplifier, and Finite Impulse Response filter, the first DAC D/A converting circuits module include the CIC being connected Interpolation filter, at least one amplifier, and frequency mixer.
Preferably, the second D/A converting circuit module includes being used to convert analog signals into the second of data signal ADC analog to digital conversion circuits module and the 2nd DAC D/A converting circuit modules for converting digital signals into analog signal.
Preferably, the 2nd ADC analog to digital conversion circuits module includes low-noise amplifier, the IQ orthogonal modulations being connected Device, frequency mixer, amplifier, and Finite Impulse Response filter, the 2nd DAC D/A converter modules include the CIC interpolation being connected Wave filter, at least one amplifier, and frequency mixer.
Preferably, penetrated between the first medium multiplefrequency mixer and the first radio frequency analog amplification circuit module provided with first Frequency switching circuit module, penetrated between the second medium multiplefrequency mixer and the second radio frequency analog amplification circuit module provided with second Frequency switching circuit.
Preferably, the first radio frequency analog amplification circuit module include the first rf analog front-end amplification circuit module and First radio frequency analog rear end amplification circuit module, the first radio frequency analog rear end amplification circuit module include at least one amplification Device, the first rf analog front-end amplifying circuit include at least one amplifier.
Preferably, the first radio-frequency switch circuit module and the second radio-frequency switch circuit module include the annular being connected Device switchs with time slot switching.
The beneficial effects of the invention are as follows:
Multifrequency digital micro repeater of the present invention, GSM/DCS/WCDMA/TD_LTE has been merged based on FPGA module System, can realize the signal transacting of multiple frequency bandwidths, finally realize that 2G/3G/4G signals cover, have integrated level it is high, into The advantages of this is low.
Brief description of the drawings
Fig. 1 is the system block diagram schematic diagram of the present invention;
Fig. 2 is the hardware circuit schematic diagram of the present invention.
Reference:1st, first medium multiplefrequency mixer, the 2, first radio frequency analog amplification circuit module, the 20, first radio frequency AFE(analog front end) amplification circuit module, the 21, first radio frequency analog rear end amplification circuit module, the 3, first D/A converting circuit module, 30th, the first ADC analog to digital conversion circuit modules, the 31, the first DAC D/A converting circuit modules, 4, FPGA module, the 5, second digital-to-analogue turns Change circuit module, the 50, the 2nd DAC D/A converting circuit modules, the 51, the 2nd ADC analog to digital conversion circuit modules, the 6, second radio frequency mould Intend amplification circuit module, the 60, second radio frequency analog rear end amplification circuit module, the 61, second rf analog front-end amplifying circuit mould Block, 7, second medium multiplefrequency mixer, the 8, first radio-frequency switch circuit module, the 9, second radio-frequency switch circuit module.
Embodiment
Below in conjunction with the accompanying drawing of the present invention, clear, complete description is carried out to the technical scheme of the embodiment of the present invention.
A kind of disclosed multifrequency digital micro repeater, has merged GSM/DCS/WCDMA, and TDD_LTE System, 2G/3G/4G networks can be covered simultaneously.
A kind of as shown in figure 1, theory structure frame of preferred embodiment of multifrequency digital micro repeater one of the present invention Figure, the multifrequency digital micro repeater includes
First medium multiplefrequency mixer 1 and second medium multiplefrequency mixer 7, for being filtered, separating to link signal;
At least one first radio frequency analog amplification circuit module 2 and the second radio frequency analog amplification circuit module 6, for filter Link signal after ripple, separation is filtered, amplified;
At least one first D/A converting circuit module 3 and at least one second D/A converting circuit module 5, for filtering Link signal after ripple, amplification mutually changed between data signal and analog signal;And
FPGA module 4, for being extracted to data signal, interpolation, shaping filter processing;
Wherein, first medium multiplefrequency mixer is connected with donor antenna, the first radio frequency analog amplification circuit module 2 It is connected with first medium multiplefrequency mixer 1, and the first D/A converting circuit module 3;The digital-to-analogue of FPGA module 4 and first Change-over circuit mould, and the second D/A converting circuit module 5 are connected;The second radio frequency analog amplification circuit module 6 and Two D/A converting circuit modules 5, and second medium multiplefrequency mixer 7 are connected, the second medium multiplefrequency mixer with again Hair antenna is connected.
With reference to shown in Fig. 1 and Fig. 2, the first radio frequency analog amplification circuit module 2 is put including the first rf analog front-end The big radio frequency analog rear end amplification circuit module 21 of circuit module 20 and first;The first D/A converting circuit module 3 includes the One ADC analog to digital conversion circuits module 30 and the first DAC D/A converting circuits module 31;The second D/A converting circuit module 5 Including the 2nd ADC analog to digital conversion circuits module 51 and the 2nd DAC D/A converting circuits module 50;The second radio frequency analog amplification Circuit module 6 includes the second radio frequency analog rear end amplification circuit module 60 and the second rf analog front-end amplification circuit module 61.
Further, when handling down link signal, the first rf analog front-end amplification circuit module 20 and the One medium multiplefrequency mixer 1, and the first ADC analog to digital conversion circuits module 30 are connected, also, the first ADC moduluses turn Change circuit module 30 with FPGA module 4 to be connected, the 2nd DAC D/A converting circuits module 50 and FPGA module 4, Yi Ji The module of two radio frequency analog rear end amplifying circuit 60 is connected, and the second radio frequency analog rear end amplification circuit module 60 and Second medium multiplefrequency mixer 7 is connected;Specifically, the first medium multiplefrequency mixer 1 isolates down link signal, by institute Down link signal is stated to input to the amplification of the first rf analog front-end amplification circuit module 20 progress signal, filtering process, processing Down link signal afterwards converts analog signals into zero intermediate frequency data signal by the first ADC analog to digital conversion circuits module 30, The zero intermediate frequency data signal inputs to FPGA module 4 and carries out digital filtering processing, the descending chain after the processing of FPGA module 4 Road signal converts digital signals into analog signal by the 2nd DAC D/A converting circuits module 50, and the analog signal is passed through Second radio frequency analog rear end amplification circuit module 60 is amplified, after filtering process, is inputted to the combining of second medium multiplefrequency mixer 7 Output.
The process of uplink signal is handled with handling the process of down link signal on the contrary, specifically, described second penetrates Frequency AFE(analog front end) amplification circuit module 61 and second medium multiplefrequency mixer 7, and the phase of the 2nd ADC analog to digital conversion circuits module 51 Connection, and the 2nd ADC analog to digital conversion circuits module 51 is connected with FPGA module 4, the first DAC D/A converting circuit moulds Block 31 is connected with the radio frequency analog rear end amplification circuit module 21 of FPGA module 4 and first, and the first radio frequency analog rear end Amplification circuit module 21 is connected with the first medium multiplefrequency mixer 1;Specifically, the second medium multiplefrequency mixer 7 Uplink signal is isolated, and the uplink signal is inputted to the second rf analog front-end amplification circuit module 61 Row amplification, filtering process, the down link signal after processing turn analog signal by the 2nd ADC analog to digital conversion circuits module 51 Zero intermediate frequency data signal is changed to, and inputs to FPGA module 4 and carries out digital filtering processing, the uplink after the processing of FPGA module 4 Road signal is changed into analog signal by the first DAC digital to analog conversion circuits, and the analog signal passes through the second radio frequency analog rear end Amplification circuit module 60 amplifies, filter after, by being exported after the combining of first medium multiplefrequency mixer 1.
In the present embodiment, when handling TD_LTE signals, first medium multiplefrequency mixer 1 and second medium multiplefrequency mixer 7 can not isolate TD_LTE uplink and downlink timeslot signals, therefore, amplify in the radio frequency analog of first medium multiplefrequency mixer 1 and first The first radio-frequency switch circuit module 8, the amplification of the radio frequency analog of second medium multiplefrequency mixer 7 and second are provided between circuit module 2 The second radio-frequency switch circuit module 8 is provided between circuit module 6, specifically, the first radio-frequency switch circuit module 8 and second Radio-frequency switch circuit module 8 includes circulator and time slot switching switch, and the circulator can make link signal one-way transmission, Time slot switching switch is finally entered to be separated TD_LTE uplink and downlink timeslot signals.
With reference to shown in Fig. 1 and Fig. 2, multifrequency digital micro repeater of the present invention, pass through FPGA module and multiple the One radio frequency analog amplification circuit module 2, the first D/A converting circuit module 3, the second D/A converting circuit module 5, and second Radio frequency analog amplification circuit module 6 is connected, and can realize the 2G/3G/4G under GSM/DCS/WCDMA, and TDD_LTE standards Covering.
In the present embodiment, GSM/DCS/WCDMA, and TD_LTE standard signals respectively include GSM down link signals and GSM uplink signals, DCS down link signals and DCS uplink signals, WCDMA down link signals and WCDMA are up Link signal, and TD_LTE uplink and downlink timeslot signals.Further, it is descending to GSM by taking gsm system, TD_LTE systems as an example Link signal and GSM uplink signals, and modules are carried out specifically during TD_LTE uplink and downlink timeslot signal transactings It is bright, and DCS, and WCDMA system are identical with gsm system.
(1) GSM down link signals and GSM uplink signals are handled
As shown in Fig. 2 during processing GSM down link signals, the first rf analog front-end amplification circuit module 20 is wrapped Low-noise amplifier, SAW filter, and amplifier are included, specifically as shown in Fig. 2 the low-noise amplifier, sound table Face wave filter, and amplifier are sequentially connected, and after down link signal is amplified by low-noise amplifier, then pass through sound table Face wave filter is filtered processing, and the down link signal after filtering process needs after amplifying again input to the first ADC moduluses Change-over circuit is further processed, and the amplifier is integrated with digital ATT functions, adjusts repeater gain size, so as to Reach control uplink downlink balance.
The first ADC analog to digital conversion circuits module 30 includes low-noise amplifier, IQ quadrature modulators, frequency mixer, put Big device, and Finite Impulse Response filter, it is specific as shown in Fig. 2 the low-noise amplifier, IQ quadrature modulators, frequency mixer, Amplifier, and Finite Impulse Response filter are sequentially connected and connect;Enter the first ADC moulds by amplification, filtered down link signal Low noise amplification is carried out first after number conversion circuit module 30, and the signal after amplification carries out IQ orthogonal modulations, the signal after modulation By frequency mixer and with local frequency synthesizer caused by concussion frequency be mixed, synthesize zero intermediate frequency signals, the zero intermediate frequency Signal is further amplified into FIR filter, is zero intermediate frequency data signal by AD analog-to-digital conversions, is finally fed through FPGA moulds Block 4 carries out base band signal process.
The FPGA module 4 is mainly extracted to data signal, interpolation, formation filtering process, specifically, the FPGA The speed crossed rate signal and drop to suitable Digital Signal Processing that module 4 comes AD by Digital Down Convert, is extracted by FIR The a series of processing such as wave filter, frequency band or bandwidth required for selecting, passing through Digital Up Convert filtering interpolation, need The frequency band or bandwidth wanted are moved on required carrier frequency.
The 2nd DAC D/A converting circuits module 50 includes CIC interpolation filters, gain amplifier, frequency mixer, described CIC interpolation filters, gain amplifier, frequency mixer, which are sequentially connected, to be connect;Data signal after the processing of FPGA module 4 carries out DA conversion Be converted to analog signal device, main function carries out DA conversion filter and amplifications to the data signal of entrance, then by with local frequency Frequency of oscillation caused by rate synthesizer is mixed, and the signal after mixing exports after being amplified.
The second radio frequency analog rear end amplification circuit module 60 includes at least one amplifier, SAW filter, tool Body as illustrated, the second radio frequency analog rear end amplification circuit module by amplifier, SAW filter, amplifier, amplifier Composition is sequentially connected, the analog signal exported to the 2nd DAC D/A converting circuits module 50 is amplified, filtering process.
When handling GSM uplink signals, the second rf analog front-end amplification circuit module 61 is put including low noise Big device, SAW filter, amplifier, it is specific as shown in Fig. 2 low-noise amplifier, SAW filter, and amplifier It is sequentially connected and connects, GSM uplink signals is amplified, filtering process.
The 2nd ADC analog to digital conversion circuits module 51 includes low-noise amplifier, IQ quadrature modulators, frequency mixer, put Big device, and Finite Impulse Response filter, it is specific as shown in Fig. 2 the low-noise amplifier, IQ quadrature modulators, frequency mixer, Amplifier, and Finite Impulse Response filter are sequentially connected and connect, and enter the 2nd ADC moulds by amplification, filtered uplink signal Low noise amplification is carried out first after number conversion circuit module 51, and the signal after amplification carries out IQ orthogonal modulations, the signal after modulation By frequency mixer and with local frequency synthesizer caused by concussion frequency be mixed, synthesize zero intermediate frequency signals, the zero intermediate frequency Signal is further amplified into after FIR filter converted by AD after be converted to zero intermediate frequency data signal, be finally fed through FPGA module 4 carries out base band signal process.
The first DAC D/A converting circuits module 31 includes CIC interpolation filters, gain amplifier, frequency mixer, such as schemes Shown in 2, the CIC interpolation filters, gain amplifier, frequency mixer are sequentially connected and connect;Data signal after the processing of FPGA module 4 Carry out DA conversion and be converted to analog signal, main function carries out DA conversion filter and amplifications to the data signal of entrance, then passed through With local frequency synthesizer caused by frequency of oscillation be mixed, the signal after mixing exports after being amplified.
The first radio frequency analog rear end amplification circuit module 21 includes SAW filter, amplifier, specifically, as schemed Shown in 2, the SAW filter and amplifier, which are sequentially connected, to be connect, and the first radio frequency analog rear end amplification circuit module 21 is to second The analog signal that DAC D/A converting circuits module 50 exports is amplified, filtering process.
(2) TD_LTE uplink and downlink timeslot signals are handled
When handling TD_LTE descending time slot signals, the first rf analog front-end amplification circuit module 20 includes amplifier, such as Shown in Fig. 2, the amplifier is connected with time slot switching switch, and the time slot switching switch is connected with circulator, and time slot is cut Change input to the first rf analog front-end amplification circuit module 20 after switch isolates TD_LTE downstream signals and be amplified processing;
The first ADC analog to digital conversion circuits module 30 includes low-noise amplifier, IQ quadrature modulators, frequency mixer, put Big device, and Finite Impulse Response filter, it is specific as shown in Fig. 2 the low-noise amplifier, IQ quadrature modulators, frequency mixer, Amplifier, and Finite Impulse Response filter are sequentially connected and connect;Enter the first ADC moulds by amplification, filtered down link signal Low noise amplification is carried out first after number conversion circuit module 30, and the signal after amplification carries out IQ orthogonal modulations, the signal after modulation By frequency mixer and with local frequency synthesizer caused by concussion frequency be mixed, synthesize zero intermediate frequency signals, the zero intermediate frequency Signal is further amplified into FIR filter, is zero intermediate frequency data signal by AD analog-to-digital conversions, is finally fed through FPGA moulds Block 4 carries out base band signal process.
The FPGA module 4 is mainly extracted to data signal, interpolation, formation filtering process, specifically, the FPGA The speed crossed rate signal and drop to suitable Digital Signal Processing that module 4 comes AD by Digital Down Convert, is extracted by FIR The a series of processing such as wave filter, frequency band or bandwidth required for selecting, passing through Digital Up Convert filtering interpolation, need The frequency band or bandwidth wanted are moved on required carrier frequency.
The 2nd DAC D/A converting circuits module 50 includes CIC interpolation filters, gain amplifier, frequency mixer, described CIC interpolation filters, gain amplifier, frequency mixer, which are sequentially connected, to be connect;Data signal after the processing of FPGA module 4 carries out DA conversion Be converted to analog signal device, main function carries out DA conversion filter and amplifications to the data signal of entrance, then by with local frequency Frequency of oscillation caused by rate synthesizer is mixed, and the signal after mixing exports after being amplified.
The second radio frequency analog rear end amplification circuit module 60 includes at least one amplifier, SAW filter, tool Body as illustrated, the second radio frequency analog rear end amplification circuit module by amplifier, SAW filter, amplifier, amplifier Composition is sequentially connected, the analog signal exported to the 2nd DAC D/A converting circuits module 50 is amplified, filtering process.
Signal after amplification, filtering process is inputted into the circulator being connected with second medium multiplefrequency mixer, finally Input is exported into second medium multiplefrequency mixer.
When handling TD_LTE ascending time slot signals, as shown in Fig. 2 the second rf analog front-end amplification circuit module 61 includes Low-noise amplifier, SAW filter, and amplifier, the low-noise amplifier are connected with time slot switching switch, institute State time slot switching switch with circulator to be connected, time slot switching switch is inputted to the first radio frequency after isolating TD_LTE upward signals AFE(analog front end) amplification circuit module 20 is amplified processing;
The 2nd ADC analog to digital conversion circuits module 51 includes low-noise amplifier, IQ quadrature modulators, frequency mixer, put Big device, and Finite Impulse Response filter, it is specific as shown in Fig. 2 the low-noise amplifier, IQ quadrature modulators, frequency mixer, Amplifier, and Finite Impulse Response filter are sequentially connected and connect, and enter the 2nd ADC moulds by amplification, filtered uplink signal Low noise amplification is carried out first after number conversion circuit module 51, and the signal after amplification carries out IQ orthogonal modulations, the signal after modulation By frequency mixer and with local frequency synthesizer caused by concussion frequency be mixed, synthesize zero intermediate frequency signals, the zero intermediate frequency Signal is further amplified into after FIR filter converted by AD after be converted to zero intermediate frequency data signal, be finally fed through FPGA module 4 carries out base band signal process.
The first DAC D/A converting circuits module 31 includes CIC interpolation filters, gain amplifier, frequency mixer, such as schemes Shown in 2, the CIC interpolation filters, gain amplifier, frequency mixer are sequentially connected and connect;Data signal after the processing of FPGA module 4 Carry out DA conversion and be converted to analog signal, main function carries out DA conversion filter and amplifications to the data signal of entrance, then passed through With local frequency synthesizer caused by frequency of oscillation be mixed, the signal after mixing exports after being amplified.
The first radio frequency analog rear end amplification circuit module 21 includes amplifier, specifically, as shown in Fig. 2 described put Big device is connected with first annular device, and the first radio frequency analog rear end amplification circuit module 21 is to the 2nd DAC D/A converting circuit moulds After the analog signal that block 50 exports is amplified processing, is inputted into first medium multiplefrequency mixer and exported by circulator.
Multifrequency digital micro direct discharging station is merged using the mobile communications network of multiple types, specifically includes TDD_ 2G, 3G and 4G network of LTE, GSM, DCS, WCDMA standard, it can also be entered in specific implementation according to the network formats that operator provides Row deployment, so as to realize the communication between base station and mobile terminal.
In the present embodiment, by taking GSM/TD_LTE standards as an example, the signal stream of multifrequency digital micro repeater is moved towards to carry out Detailed description, wherein, DCS, WCDMA standard and GSM standard principles are essentially identical.
In gsm system, donor antenna (not shown) couples the down link signal from base station by wireless space, leads to Cross first medium multiplefrequency mixer 1 and isolate GSM down link signals, before GSM down link signals enter the first radio frequency analog Hold amplifying circuit to carry out signal amplification filtering, subsequently enter the first ADC analog to digital conversion circuits module 30 and be converted into analog signal Zero intermediate frequency data signal, zero intermediate frequency data signal carry out digital filter signal transacting, the numeral after processing in FPGA module 4 Data signal is converted into analog signal and is then fed into the second radio frequency by baseband signal the 2nd DAC D/A converting circuits module 50 of feeding Analog back-end amplification circuit module 60 carries out signal amplification filtering, is finally sent into the combining output of second medium multiplefrequency mixer 7.Phase Anti-, retransmitting antenna (not shown) receives the uplink signal from spacing wireless coupling, by second medium multifrequency combining Device 7 isolates GSM uplink signals, and GSM uplink signals carry out modulus change by the 2nd ADC analog conversion circuits module Change, analog signal is converted into data signal feeding FPGA module 4 carries out digital filtered signal processing, the base-band digital after processing Data signal is converted into analog signal and is then fed into the first radio frequency analog by signal the first DAC D/A converting circuits module 31 of feeding Rear end amplification circuit module 21, finally by being exported after the combining of first medium multiplefrequency mixer 1.
In TDD_LTE systems, donor antenna couples the down link signal from base station by wireless space, by the One medium multiplefrequency mixer isolates TD_LTE link signals, and TD_LTE link signals separate into the first radio-frequency switch circuit 8 Go out TD_LTE uplink signals, signal amplification, filtering process carried out by the first rf analog front-end amplification circuit module 20, Subsequently enter the first ADC analog-to-digital conversions circuit module 30 and analog signal is converted into zero intermediate frequency data signal, zero intermediate frequency number Word signal carries out digital filter signal transacting in FPGA module 4, and the digital baseband signal after processing is sent into the 2nd DAC digital-to-analogues Data signal is converted into analog signal by translation circuit module 50, is then fed into the second radio frequency analog rear end amplification circuit module 60 Signal amplification, filtering are carried out, is finally sent into the combining output of second medium multiplefrequency mixer 7.Retransmitting antenna receive from space without The uplink signal of line coupling, isolates TD_LTE signals, TD_LTE link signals enter by second medium multiplefrequency mixer 7 Enter the second radio-frequency switch circuit and isolate TD_LTE upward signals, AD changes are carried out by the 2nd ADC analog conversion circuits module 51 Change, analog signal is converted into data signal is sent into FPGA progress digital filtered signal processing, the baseband digital signal after processing It is sent into the first DAC D/A converting circuits module and data signal is converted into analog signal is then fed into the first radio frequency analog rear end and puts Big circuit module, exported finally by after first medium multiplefrequency mixer combining from BS ports.
Multifrequency digital micro repeater of the present invention, GSM/DCS/WCDMA/TD_LTE has been merged based on FPGA module System, 2G/3G/4G signal transactings are realized, there is the advantages of integrated level is high, cost is low.
The technology contents and technical characteristic of the present invention have revealed that as above, but those skilled in the art still may base Make a variety of replacements and modification without departing substantially from spirit of the present invention, therefore, the scope of the present invention in teachings of the present invention and announcement The content disclosed in embodiment should be not limited to, and various replacements and modification without departing substantially from the present invention should be included, and is this patent Shen Please claim covered.

Claims (10)

  1. A kind of 1. multifrequency digital micro repeater, it is characterised in that including
    First medium multiplefrequency mixer and second medium multiplefrequency mixer, for being filtered, separating to link signal;
    At least one first radio frequency analog amplification circuit module and the second radio frequency analog amplification circuit module, for filtering, point Link signal from after is filtered, amplified;
    At least one first D/A converting circuit module and at least one second D/A converting circuit module, for filtering, amplifying Link signal afterwards mutually changed between data signal and analog signal;And
    FPGA module, for being extracted to data signal, interpolation, shaping filter processing;
    The first radio frequency analog amplification circuit module and first medium multiplefrequency mixer, and the first D/A converting circuit module It is connected;
    The FPGA module and the first D/A converting circuit module, and the second D/A converting circuit module are connected;Described Two radio frequency analog amplification circuit modules and the second D/A converting circuit module, and second medium multiplefrequency mixer are connected.
  2. 2. multifrequency digital micro repeater according to claim 1, it is characterised in that the first radio frequency analog amplification electricity Road module includes the first rf analog front-end amplification circuit module and the first radio frequency analog rear end amplification circuit module, and described first Rf analog front-end amplification circuit module includes at least one amplifier and SAW filter, the amplification of the first radio frequency analog rear end Circuit module includes at least one amplifier and SAW filter.
  3. 3. multifrequency digital micro repeater according to claim 1, it is characterised in that the second radio frequency analog amplification electricity Road module includes the second rf analog front-end amplification circuit module and the second radio frequency analog rear end amplification circuit module, and described second Radio frequency analog rear end amplification circuit module includes at least one amplifier and SAW filter, the amplification of the second rf analog front-end Circuit includes at least one amplifier and SAW filter.
  4. 4. multifrequency digital micro repeater according to claim 1, it is characterised in that the first analog to digital conversion circuit mould Block is including for converting analog signals into the first ADC analog to digital conversion circuits module of data signal and for data signal to be turned It is changed to the first DAC D/A converting circuit modules of analog signal.
  5. 5. multifrequency digital micro repeater according to claim 4, it is characterised in that the first ADC analog-to-digital conversions electricity Road module includes low-noise amplifier, IQ quadrature modulators, the frequency mixer being connected, amplifier, and Finite Impulse Response filter, The first DAC D/A converting circuits module includes CIC interpolation filters, at least one amplifier being connected, and mixing Device.
  6. 6. multifrequency digital micro repeater according to claim 1, it is characterised in that the second D/A converting circuit mould Block is including for converting analog signals into the 2nd ADC analog to digital conversion circuits module of data signal and for data signal to be turned It is changed to the 2nd DAC D/A converting circuit modules of analog signal.
  7. 7. multifrequency digital micro repeater according to claim 6, it is characterised in that the 2nd ADC analog-to-digital conversions electricity Road module includes low-noise amplifier, IQ quadrature modulators, the frequency mixer being connected, amplifier, and Finite Impulse Response filter, The 2nd DAC D/A converter modules include CIC interpolation filters, at least one amplifier being connected, and frequency mixer.
  8. 8. multifrequency digital micro repeater according to claim 1, it is characterised in that the first medium multiplefrequency mixer The first radio-frequency switch circuit module, the second medium multiplefrequency mixer are provided between the first radio frequency analog amplification circuit module The second radio-frequency switch circuit is provided between the second radio frequency analog amplification circuit module.
  9. 9. multifrequency digital micro repeater according to claim 8, it is characterised in that the first radio frequency analog amplification electricity Road module includes the first rf analog front-end amplification circuit module and the first radio frequency analog rear end amplification circuit module, and described first Radio frequency analog rear end amplification circuit module includes at least one amplifier, and the first rf analog front-end amplifying circuit includes at least one Individual amplifier.
  10. 10. multifrequency digital micro repeater according to claim 8, it is characterised in that first radio-frequency switch circuit Module switchs with the circulator that the second radio-frequency switch circuit module includes being connected and time slot switching.
CN201610854672.8A 2016-09-27 2016-09-27 Multifrequency digital micro repeater Pending CN107872269A (en)

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