CN107863377B - Semiconductor element and its manufacturing method - Google Patents
Semiconductor element and its manufacturing method Download PDFInfo
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- CN107863377B CN107863377B CN201610839780.8A CN201610839780A CN107863377B CN 107863377 B CN107863377 B CN 107863377B CN 201610839780 A CN201610839780 A CN 201610839780A CN 107863377 B CN107863377 B CN 107863377B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000002955 isolation Methods 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims description 6
- 239000010408 film Substances 0.000 description 13
- 238000000034 method Methods 0.000 description 7
- 230000035882 stress Effects 0.000 description 7
- 238000000059 patterning Methods 0.000 description 6
- 230000008646 thermal stress Effects 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Abstract
The present invention discloses a kind of semiconductor element and its manufacturing method.The semiconductor element includes substrate, multiple active areas and isolation structure.Substrate has element area and surrounds the neighboring area of the element area.Active area is located in the substrate in the element area, wherein from from the point of view of upper apparent direction, the edge of the end of the active area on the boundary of the neighbouring element area is aligned with each other, and the width of the end of the active area on the boundary of the neighbouring element area is greater than the width of the other parts of the active area.Isolation structure is configured in the substrate, and around the active area and is located in the neighboring area.
Description
Technical field
The present invention relates to a kind of semiconductor element and its manufacturing methods, and more particularly to avoidable pattern density difference institute
The semiconductor element and its manufacturing method for the problem of causing.
Background technique
In current semiconductor fabrication process, usually isolation structure is formed in substrate, is wherein had to define
The element area of multiple active areas and neighboring area.As the size of element persistently reduces, the layout area of element area also with
Diminution.In this way, biggish pattern density difference is caused on substrate, and this pattern density difference is in subsequent production work
It will throw into question in skill.
The boundary in element area and neighboring area is influenced brought by above-mentioned pattern density difference to become apparent.It lifts
For example, when stacking film layer on the active area of neighbouring element zone boundary, influenced that film can be generated by pattern density difference
Ply stress (film stress).In addition, in depositional coating also thermal stress (thermal can be generated in above-mentioned zone
stress).Due to above-mentioned stress in thin film and thermal stress, it is easy that the film layer on the active area of neighbouring element zone boundary has
The problem of toppling over, thus subsequent manufacturing processes are impacted.
Summary of the invention
The purpose of the present invention is to provide a kind of semiconductor element, reliability with higher.
Another object of the present invention is to provide a kind of manufacturing method of semiconductor element, can avoid pattern density difference pair
Subsequent manufacturing processes impact.
In order to achieve the above object, semiconductor element of the invention includes substrate, multiple active areas and isolation structure.Substrate tool
There is element area and surrounds the neighboring area of the element area.Active area is located at the substrate in the element area
In, wherein the terminal edge of the active area on the boundary of the neighbouring element area is aligned with each other from from the point of view of upper apparent direction, and
The width of the end of the active area on the boundary of the neighbouring element area is greater than the width of the other parts of the active area.
Isolation structure is configured in the substrate, and around the active area and is located in the neighboring area.
In an embodiment of semiconductor element of the invention, from from the point of view of upper apparent direction, the neighbouring element area
The shape of end of the active area on boundary be, for example, semicircle or polygonal.
It is above-mentioned from from the point of view of upper apparent direction in an embodiment of semiconductor element of the invention, the neighbouring element region
The end of the active area on the boundary in domain is for example in contact with each other.
In an embodiment of semiconductor element of the invention, above-mentioned active area is for example arranged with array manner.
In an embodiment of semiconductor element of the invention, the boundary of the above-mentioned neighbouring element area it is described active
Boundary alignment of the edge of the end in area for example with the element area.
The manufacturing method of semiconductor element of the invention, comprising the following steps: provide substrate, the substrate has element region
Domain and the neighboring area for surrounding the element area；The part of substrate in the element area and the neighboring area is removed, with
It is formed in first groove and substrate in the neighboring area in substrate in the element area and forms second groove,
Wherein the first groove defines multiple active areas, and from from the point of view of upper apparent direction, the institute on the boundary of the neighbouring element area
The terminal edge for stating active area is aligned with each other, and the width of the end of the active area on the boundary of the neighbouring element area is big
In the width of the other parts of the active area；And isolated material is inserted in the first groove and the second groove.
In an embodiment of the manufacturing method of semiconductor element of the invention, from from the point of view of upper apparent direction, the neighbouring institute
It is, for example, semicircle or polygonal for stating the shape of the end of the active area on the boundary of element area.
In an embodiment of the manufacturing method of semiconductor element of the invention, from from the point of view of upper apparent direction, the neighbouring member
The end of the active area on the boundary in part region is for example in contact with each other.
In an embodiment of the manufacturing method of semiconductor element of the invention, above-mentioned active area is for example with array manner
Arrangement.
In an embodiment of the manufacturing method of semiconductor element of the invention, the boundary of the above-mentioned neighbouring element area
The active area end boundary alignment of the edge for example with the element area.
Based on above-mentioned, in the present invention, since the edge of the end of the active area on the boundary in neighbouring element region is mutually opposite
Standard, and the width of these ends is greater than the width of other parts, therefore the stacked film on the active area of neighbouring element zone boundary
When layer, it can avoid the thermal stress generated when the stress in thin film or depositional coating due to pattern density difference and lead to neighbouring element
The film layer on the boundary in region is toppled over.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and cooperate appended attached drawing
It is described in detail below.
Detailed description of the invention
Figure 1A to Figure 1B is to illustrate according to view on the manufacturing process of semiconductor element depicted in first embodiment of the invention
Figure；
Fig. 2A to Fig. 2 B is to illustrate according to view on the manufacturing process of semiconductor element depicted in second embodiment of the invention
Figure；
Fig. 3 is the upper schematic diagram according to semiconductor element depicted in another embodiment of the present invention；
Fig. 4 is the upper schematic diagram of another embodiment of the first groove in Figure 1A.
Specific embodiment
In the examples below, it is mainly described in substrate and forms active area and the isolation structure to define active area
Manufacturing process steps.In addition, visual actual demand carries out other subsequent production after these above-mentioned manufacturing process steps systems
Technique, such as general known dynamic random access memory (DRAM) manufacture craft or metal oxide semiconductor transistor
(MOS) manufacture craft.
Figure 1A to Figure 1B is to illustrate according to view on the manufacturing process of semiconductor element depicted in first embodiment of the invention
Figure.Firstly, please referring to Figure 1A, substrate 100 is provided.Substrate 100 is, for example, silicon base.Substrate 100, which can be divided into, is used to form institute
Need the element area 100a of the element and neighboring area 100b around element area 100a.Then, is formed in substrate 100
One groove 102 and second groove 104.It will be detailed below the formation of first groove 102 and second groove 104 in the present embodiment
Method.
Patterning manufacture craft for the first time is carried out to substrate 100, part of substrate 100 is removed, in element area 100a
It forms multiple first grooves 102 and forms multiple second grooves 104 in the 100b of neighboring area.In the present embodiment, element
Multiple first grooves 102 extended in a first direction and multiple the first ditches extended in second direction are formed in the 100a of region
Slot 102, and first direction is perpendicular to second direction, however, the present invention is not limited thereto.In other embodiments, depending on actual demand,
One direction can also be not orthogonal to second direction.Since the second groove 102 positioned at neighboring area 100b is to isolation element
Region 100a, therefore from from the point of view of upper apparent direction, compared with first groove 102, second groove 104 has biggish width and occupies
Biggish layout area.
In element area 100a, these first grooves 102 interlaced with each other define multiple active areas 106.In this reality
It applies in example, these active areas 106 are arranged with array manner, have the active area 106 of identical quantity in every a line, have in each column
Have the active area 106 of identical quantity, and in each column least significant end active area 106 it is aligned with each other, however, the present invention is not limited thereto.?
In other embodiments, visual actual demand adjusts the configuration mode of these active areas.
In addition, in the present embodiment, from from the point of view of upper apparent direction, the active area 106 on the boundary of neighbouring element region 100a is (i.e.
The active area 106 of least significant end in each column) end compared with the other parts of active area 106 have biggish width, and this
End extends in neighboring area 104.In the present embodiment, from from the point of view of upper apparent direction, the boundary of neighbouring element region 100a
The shape of the end of active area 106 is, for example, circle, and other parts are then rectangle.However, in other embodiments, from upper view
From the point of view of direction, the end of the active area 106 on the boundary of neighbouring element region 100a is also possible to polygon (such as rectangle, such as Fig. 4
It is shown), as long as end has biggish width compared with other parts.In the present embodiment, have in each column larger
Be separated with a certain distance to each other with the end of larger width in the end of width and adjacent column, i.e., have in adjacent two column compared with
The end of big width does not contact each other, however, the present invention is not limited thereto.In other embodiments, there is larger width in adjacent two column
End can also be in contact with each other, imply that the end of these larger width can link into an integrated entity.
Then, second of patterning manufacture craft is carried out, one of the end in active area 106 with larger width is removed
Point.Importantly, after carrying out above-mentioned patterning manufacture craft, the active area 106 on the boundary of neighbouring element region 100a
End still needs to have biggish width compared with the other parts of active area 106, and neighbouring element region 100a in each column
The edge of the end of the active area 106 on boundary can be also aligned with each other.
In the present embodiment, the part for being located at neighboring area in above-mentioned end, and the side of remaining end section are removed
The boundary alignment of edge and element area 100a, however, the present invention is not limited thereto.In other embodiments, above-mentioned patterning system is being carried out
After making technique, the edge of the end of the active area 106 on the boundary of neighbouring element region 100a can not be with element area 100a's
Boundary alignment implies that portion distal end can be located in the 100b of neighboring area or end can be fully located in element area 100a.
Later, please refer to Figure 1B, in the groove for defining active area 106 (be in the present embodiment first groove 102 and
Two grooves 104) in insert isolated material, with formed surround active area 106 isolation structure 108.Above-mentioned isolated material is, for example,
Oxide material, forming method are, for example, to carry out rotary coating manufacture craft, high-density plasma (HDP) oxide deposition
Manufacture craft or enhancing high-aspect-ratio ditch fill out manufacture craft (enhanced high aspect ratio process, eHARP).
As shown in Figure 1B, from from the point of view of upper apparent direction, in the present embodiment, since the boundary of neighbouring element region 100a has
The edge of the end of source region 106 is aligned with each other, and the width of these ends is greater than the width of other parts, therefore in neighbouring element
When stacking film layer on the active area 106 on the region boundary 100a, the stress in thin film or deposition due to pattern density difference can avoid
The thermal stress that is generated when film layer and cause the film layer on the boundary of neighbouring element region 100a to be toppled over.
In the above-described embodiments, active area 106 have in each column with the active area 106 of identical quantity in every a line
The active area 106 of identical quantity, and in each column least significant end active area 106 it is aligned with each other.In another embodiment, with array
The active area 106 that mode arranges also can have configuration below.
Fig. 2A to Fig. 2 B is to illustrate according to view on the manufacturing process of semiconductor element depicted in second embodiment of the invention
Figure.In the present embodiment, the element being identical with the first embodiment will be indicated with identical component symbol.
Firstly, A referring to figure 2., carry out with identical manufacturing process steps described in Figure 1A, form first in substrate 100
Groove 102 and second groove 104.In the present embodiment, the active area 106 defined by first groove 102 is with array manner
Arrangement wherein has the active area 106 of least significant end in the active area 106 of identical quantity and each column aligned with each other in odd column,
The active area 106 of least significant end is aligned with each other in active area 106 and each column in even column with identical quantity.In addition, in surprise
In ordered series of numbers in each column the 106 neighbouring element region 100a of active area of least significant end boundary, and in even column in each column most
The active area 106 of end is far from the boundary of element area 100a.Importantly, from from the point of view of upper apparent direction, it is each in odd column
The end of the active area 106 of least significant end has biggish width compared with other parts in column.
Then, patterning manufacture craft is carried out, one of the end with larger width of active area 106 in odd column is removed
Part.Importantly, the boundary of neighbouring element region 100a has in odd column after carrying out above-mentioned patterning manufacture craft
The end of source region 106 still needs to have biggish width compared with other parts, and the edge of the end of these active areas 106 also can
It is aligned with each other.In the present embodiment, the boundary alignment at the edge of the end of these active areas 106 and element area 100a.
Later, B referring to figure 2., carry out with identical manufacturing process steps described in Fig. 2 B, in defining active area 106
Isolated material is inserted in groove (being in the present embodiment first groove 102 and second groove 104), surrounds active area to be formed
106 isolation structure 108.
As shown in Figure 2 B, from from the point of view of upper apparent direction, in the present embodiment, due to neighbouring element region 100a in odd column
The edge of the end of the active area 106 on boundary is aligned with each other, and the width of these ends be greater than other parts width, therefore
When stacking film layer on the active area 106 on the neighbouring element region boundary 100a, it can avoid answering due to the film layer of pattern density difference
The thermal stress that is generated when power or depositional coating and cause the film layer on the neighbouring element region boundary 100a to be toppled over.Further, since even number
The active area 106 of least significant end therefore is less affected by above-mentioned pattern density difference further away from the boundary of element area 100a in column
Influence, and even if being affected, since the width of the end of the active area 106 of least significant end in even column is greater than other parts
Width, therefore also can avoid toppling over problem because of the film layer caused by stress in thin film or thermal stress.
In the above embodiments, from from the point of view of upper apparent direction, level of all flat shape of the extending direction of active area 106 in figure
Direction, as shown in Figure 1A and Fig. 2A, however, the present invention is not limited thereto.In other embodiments, such as existing DRAM manufacture craft,
Being formed by 106 extending direction of active area can also horizontal direction of the uneven shape in Figure 1A and Fig. 2A.
As shown in figure 3, in the present embodiment, it, can be by active area when forming first groove 102 to define active area 106
106 are defined as its extending direction not with the horizontal direction parallel in figure, such as upwardly extend from the side of upper left to bottom right, but this
It invents without being limited thereto.In another embodiment, active area 106 can also be upwardly extended in the side from upper right to lower-left.In this way,
After carrying out manufacturing process steps as described in Figure 2 B, the structure similar with Fig. 2 B can be formed, and the difference of the two is only that
The extending direction of active area 106.Similarly, in another embodiment, the structure similar with Figure 1B can also be formed and difference only exists
In the extending direction of active area 106.
Although disclosing the present invention in conjunction with above embodiments, it is not intended to limit the invention, any affiliated technology
Skilled person in field can make some changes and embellishment without departing from the spirit and scope of the present invention, therefore of the invention
Protection scope should be subject to what the appended claims were defined.
Claims (10)
1. a kind of semiconductor element, comprising:
Substrate, with element area and the neighboring area for surrounding the element area；
Multiple active areas, in the substrate in the element area, wherein from from the point of view of upper apparent direction, the neighbouring element
The edge of the end of the active area on the boundary in region is aligned with each other, and the boundary of the neighbouring element area is described active
The width of the end in area is greater than the width of the other parts of the active area；And
Isolation structure is configured in the substrate, and around the active area and is located in the neighboring area,
Wherein the multiple active area is a part of the substrate.
2. semiconductor element as described in claim 1, wherein from from the point of view of upper apparent direction, the side of the neighbouring element area
The shape of the end of the active area on boundary includes semicircle or polygonal.
3. semiconductor element as described in claim 1, wherein from from the point of view of upper apparent direction, the boundary of the neighbouring element area
The end of the active area is in contact with each other.
4. semiconductor element as described in claim 1, wherein the active area is arranged with array manner.
5. semiconductor element as described in claim 1, wherein the end of the active area adjacent to the boundary of the element area
The boundary alignment at the edge at end and the element area.
6. a kind of manufacturing method of semiconductor element, comprising:
Substrate is provided, the substrate has element area and surrounds the neighboring area of the element area；
The part substrate in the element area and the neighboring area is removed, with the base in the element area
It is formed in first groove and the substrate in the neighboring area in bottom and forms second groove, wherein the first groove
Multiple active areas are defined, and from from the point of view of upper apparent direction, the end of the active area on the boundary of the neighbouring element area
Edge is aligned with each other, and the width of the end of the active area on the boundary of the neighbouring element area is greater than the active area
The width of other parts；And
Isolated material is inserted in the first groove and the second groove,
Wherein the multiple active area is a part of the substrate.
7. the manufacturing method of semiconductor element as claimed in claim 6, wherein from from the point of view of upper apparent direction, the neighbouring member
The shape of the end of the active area on the boundary in part region includes semicircle or polygonal.
8. the manufacturing method of semiconductor element as claimed in claim 6, wherein from from the point of view of upper apparent direction, the neighbouring element region
The end of the active area on the boundary in domain is in contact with each other.
9. the manufacturing method of semiconductor element as claimed in claim 6, wherein the active area is arranged with array manner.
10. the manufacturing method of semiconductor element as claimed in claim 6, wherein adjacent to described in the boundary of the element area
The boundary alignment at the edge of the end of active area and the element area.
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| CN201610839780.8A CN107863377B (en) | 2016-09-22 | 2016-09-22 | Semiconductor element and its manufacturing method |
| US15/296,955 US9679901B1 (en) | 2016-09-22 | 2016-10-18 | Semiconductor device and manufacturing method thereof |
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| CN201610839780.8A CN107863377B (en) | 2016-09-22 | 2016-09-22 | Semiconductor element and its manufacturing method |
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| CN110534525B (en) | 2018-05-24 | 2022-04-19 | 联华电子股份有限公司 | Semiconductor device and method of forming the same |
| CN110707044B (en) * | 2018-09-27 | 2022-03-29 | 联华电子股份有限公司 | Method for forming semiconductor device layout |
| CN112885781B (en) * | 2019-11-29 | 2022-06-24 | 长鑫存储技术有限公司 | Preparation method of active region and semiconductor device |
| CN113314534B (en) * | 2021-05-06 | 2023-11-21 | 福建省晋华集成电路有限公司 | Semiconductor structure, manufacturing method thereof and memory |
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| CN102694024A (en) * | 2011-03-23 | 2012-09-26 | 株式会社东芝 | Semiconductor device |
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| US6492073B1 (en) | 2001-04-23 | 2002-12-10 | Taiwan Semiconductor Manufacturing Company | Removal of line end shortening in microlithography and mask set for removal |
| US7691549B1 (en) | 2007-02-15 | 2010-04-06 | Kla-Tencor Technologies Corporation | Multiple exposure lithography technique and method |
| US7927782B2 (en) | 2007-12-28 | 2011-04-19 | Texas Instruments Incorporated | Simplified double mask patterning system |
| JP5881567B2 (en) | 2012-08-29 | 2016-03-09 | 株式会社東芝 | Pattern formation method |
| KR102084954B1 (en) | 2013-05-02 | 2020-03-05 | 삼성전자주식회사 | Semiconductor device and method of fabricating the same |
| CN204144257U (en) * | 2013-10-21 | 2015-02-04 | 半导体元件工业有限责任公司 | Semiconductor device |
| US9209037B2 (en) | 2014-03-04 | 2015-12-08 | GlobalFoundries, Inc. | Methods for fabricating integrated circuits including selectively forming and removing fin structures |
| US9666665B2 (en) * | 2014-04-09 | 2017-05-30 | Infineon Technologies Ag | Semiconductor device with semiconductor mesa including a constriction |
| US9184169B2 (en) | 2014-04-10 | 2015-11-10 | Globalfoundries Inc. | Methods of forming FinFET devices in different regions of an integrated circuit product |
| KR102204387B1 (en) * | 2014-12-17 | 2021-01-18 | 삼성전자주식회사 | Semiconductor device having buried gate structure and method of fabricating the same |
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| CN102694024A (en) * | 2011-03-23 | 2012-09-26 | 株式会社东芝 | Semiconductor device |
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| CN107863377A (en) | 2018-03-30 |
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