CN107863350B - Three-dimensional memory and preparation method thereof - Google Patents
Three-dimensional memory and preparation method thereof Download PDFInfo
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- CN107863350B CN107863350B CN201711165222.9A CN201711165222A CN107863350B CN 107863350 B CN107863350 B CN 107863350B CN 201711165222 A CN201711165222 A CN 201711165222A CN 107863350 B CN107863350 B CN 107863350B
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- 150000004767 nitrides Chemical class 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
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- 238000004519 manufacturing process Methods 0.000 description 8
- 229910000449 hafnium oxide Inorganic materials 0.000 description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 3
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
The application discloses a three-dimensional memory and a preparation method thereof, the preparation method of the three-dimensional memory forms a stacked structure positioned in an array area and a step area on the surface of a substrate, forms a protective film layer on the surface of the stacked structure positioned in the step area, etches the protective film layer, and in the etching process, after the etching of the protective film layers of other steps is completed, a part of the protective film layer closest to the side wall of the first step of the substrate is remained, and the remained protective film layer becomes a protective structure attached to the side wall of the first step closest to the substrate, thereby protecting a first dielectric layer closest to the substrate and a sacrificial layer, avoiding the situation that the first dielectric layer reacts with other substrates due to the contact in the subsequent preparation process, and further avoiding the situation that an unnecessary oxidation structure is formed in the substrate, the device performance of the finally formed three-dimensional memory is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and more particularly, to a three-dimensional memory and a method for fabricating the same.
Background
Memory (Memory) is a Memory device used in modern information technology to store information. With the increasing demands of various electronic devices on integration level and data storage density, it is difficult for a common two-dimensional memory to further increase the integration level and data storage density, and thus, a three-dimensional (3D) memory has come into play.
The three-dimensional NAND memory is one of three-dimensional flash memories, in the preparation process, firstly, a stacking structure is deposited on the surface of a silicon substrate, each stacking structure comprises a plurality of first dielectric layers and sacrificial layers which are alternately stacked, the sacrificial layers are positioned between the adjacent first dielectric layers, the reference numeral 10 in figure 1 indicates the substrate, 20 indicates a step area, 30 indicates an array area, 21 indicates a sacrificial layer, 22 indicates a first dielectric layer, the stacking structures positioned at two sides of the central area of the surface of the substrate form a plurality of steps, each first dielectric layer and the sacrificial layer form a step, the step closest to the substrate is formed by two first dielectric layers and the sacrificial layer positioned between the two first dielectric layers, in the subsequent process, particularly after being subjected to annealing and thermal oxidation process, referring to figure 2, the edge part of the first dielectric layer at the lowest layer of the stacking structure forming the plurality of steps reacts with the substrate, thereby forming a bird's beak-like oxide structure BE inside the substrate, which may adversely affect the performance of the finally formed three-dimensional memory.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a three-dimensional memory and a method for fabricating the same, so as to solve the problem that a first dielectric layer closest to a substrate of a stacked structure constituting a step region reacts with the substrate in a subsequent process, thereby forming an unnecessary oxidation structure inside the substrate.
In order to achieve the technical purpose, the embodiment of the invention provides the following technical scheme:
a method for preparing a three-dimensional memory comprises the following steps:
providing a substrate, wherein the surface of the substrate is provided with a plurality of stacked structures, the plurality of stacked structures are respectively located on an array area and the surfaces of two step areas of the substrate, the two step areas are respectively located on two sides of the array area, each stacked structure comprises a plurality of layers of first dielectric layers and sacrificial layers which are stacked in a staggered mode, the sacrificial layers are located between the adjacent first dielectric layers, a first groove is formed between every two stacked structures, the first groove is exposed out of the surface of the substrate, and the stacked structures located on the surfaces of the step areas form multi-level steps;
forming a protective film layer on the surface of the stacked structure in the step area;
and etching the protective film layer to form a protective structure on the side wall of the first-stage step of the stacking structure closest to the substrate, wherein the protective structure at least covers a first dielectric layer and a sacrificial layer closest to the substrate.
Optionally, the forming a protective film layer on the surface of the stacked structure in the step area includes:
depositing a preset material on the surface of the stacked structure positioned in the step area to form the protective film layer;
the etching selection ratio of the preset material to the first dielectric layer is greater than a preset value;
and the etching selection ratio of the preset material to the sacrificial layer is greater than a preset value.
Optionally, the preset material is silicon oxynitride, polysilicon or amorphous silicon.
Optionally, the etching the protective film layer includes:
and etching the protective film layer by adopting a reactive ion etching method.
Optionally, after the etching the protective film layer, the method further includes:
growing monocrystalline silicon in the groove to obtain a monocrystalline silicon upright post;
etching the monocrystalline silicon upright column to enable the monocrystalline silicon upright column to be flush with the surface of the substrate;
etching to remove the sacrificial layer of the stacked structure, and forming a storage dielectric layer and a metal gate between the adjacent first dielectric layers;
and growing a polycrystalline silicon layer and a polycrystalline silicon medium layer on the surface of the monocrystalline silicon upright column to form a channel.
Optionally, the etching to remove the sacrificial layer of the stacked structure and form a storage dielectric layer and a metal gate between adjacent first dielectric layers includes:
etching and removing the sacrificial layer of the stacked structure to provide a space for the growth of the storage medium layer;
growing a first oxide layer on the surface of the first dielectric layer;
growing a first nitride layer on the surface of the first oxide layer;
growing a second oxide layer on the surface of the first nitride layer, wherein the first oxide layer, the first nitride layer and the second oxide layer form the storage medium layer;
and depositing a metal gate on the surface of the second oxide layer.
Optionally, growing a polysilicon layer and a polysilicon dielectric layer on the surface of the monocrystalline silicon upright, and forming a channel includes:
growing polycrystalline silicon on the surfaces of the monocrystalline silicon upright posts and the first grooves to form a polycrystalline silicon layer with second grooves;
growing a polysilicon medium layer in the second groove to fill the second groove;
etching the polysilicon medium layer to enable the height of the polysilicon medium layer to be smaller than that of the polysilicon layer;
and growing polysilicon on the surface of the polysilicon dielectric layer so that the polysilicon layer wraps the polysilicon dielectric layer.
A three-dimensional memory, comprising: the device comprises a substrate, wherein one side surface of the substrate comprises an array area and step areas positioned on two sides of the array area; the array structure comprises a substrate, an array region and a step region, wherein the array region and the step region are arranged on the substrate in a parallel mode, the step region is arranged on the substrate in a parallel mode, the array region and the step region are arranged in a parallel mode, the stacking structure comprises a plurality of layers of metal gates, a plurality of layers of first dielectric layers and a plurality of layers of storage dielectric layers, the metal gates and the first dielectric layers are located on two sides of the channels and are alternately stacked, and the storage dielectric layers are located between the metal gates and the channels and; the contact hole is positioned on the surface of one end, away from the substrate, of the channel and used for connecting a bit line and a word line; the three-dimensional memory further includes: the protective structure is positioned on the side wall of the stacking structure of the step area, at least one first dielectric layer and one storage dielectric layer which are closest to the substrate are covered by the protective structure, and the three-dimensional memory is prepared by the preparation method of the three-dimensional memory;
the protection structure is made of a preset material, and the etching selection ratio of the preset material to the first medium layer is greater than a preset value;
and the etching selection ratio of the preset material to the sacrificial layer is greater than a preset value.
Optionally, the first dielectric layer is a silicon oxide layer;
the first nitride layer is a silicon nitride layer;
the first oxide layer is a silicon oxide layer;
the second oxide layer is a silicon oxide layer or an aluminum oxide layer or a hafnium oxide layer.
It can be seen from the above technical solutions that, in the method for manufacturing a three-dimensional memory according to the embodiments of the present invention, after a stacked structure located in an array region and a step region is formed on a surface of a substrate, a protective film layer is formed on a surface of the stacked structure located in the step region, and the protective film layer is etched, because requirements of a process and device parameters of the three-dimensional memory require that a thickness of a step closest to the substrate is much greater than thicknesses of other steps, a height of the protective film layer closest to a sidewall of the step closest to the substrate is greater than that of the protective film layers of the sidewalls of the other steps, during an etching process, after etching of the protective film layers of the other steps is completed, a portion of the protective film layer closest to the sidewall of the step closest to the substrate remains, and the remaining portion of the protective film layer becomes a protective structure attached to the sidewall of the step closest to the substrate, therefore, the first dielectric layer and the sacrificial layer which are closest to the substrate are protected, the condition that the first dielectric layer reacts due to contact with other substrates in the subsequent preparation process is avoided, the condition that an unnecessary oxidation structure is formed in the substrate is avoided, and the device performance of the finally formed three-dimensional memory is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic cross-sectional view of a three-dimensional memory in the prior art;
FIG. 2 is a cross-sectional view of a prior art three-dimensional memory device forming a bird's beak shaped oxide structure in a substrate;
fig. 3 is a schematic flowchart of a method for manufacturing a three-dimensional memory according to an embodiment of the present application;
fig. 4-6 are schematic diagrams illustrating a process for manufacturing a three-dimensional memory according to an embodiment of the present application;
fig. 7 is a schematic flowchart of a method for manufacturing a three-dimensional memory according to another embodiment of the present application;
fig. 8 is a schematic flow chart illustrating a method for fabricating a three-dimensional memory according to another embodiment of the present application;
FIG. 9 is a schematic flow chart illustrating a method for fabricating a three-dimensional memory according to an embodiment of the present application;
FIG. 10 is a schematic flow chart illustrating a method for fabricating a three-dimensional memory according to another embodiment of the present application;
fig. 11 is a flowchart illustrating a method for manufacturing a three-dimensional memory according to another embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the application provides a method for preparing a three-dimensional memory, as shown in fig. 3, the method includes:
s101: providing a substrate, wherein the surface of the substrate is provided with a plurality of stacked structures, the plurality of stacked structures are respectively located on an array area and the surfaces of two step areas of the substrate, the two step areas are respectively located on two sides of the array area, each stacked structure comprises a plurality of layers of first dielectric layers and sacrificial layers which are stacked in a staggered mode, the sacrificial layers are located between the adjacent first dielectric layers, a first groove is formed between every two stacked structures, the first groove is exposed out of the surface of the substrate, and the stacked structures located on the surfaces of the step areas form multi-level steps;
referring to fig. 4, fig. 4 is a schematic cross-sectional structure diagram of the substrate provided in step S101, where reference numeral 100 in fig. 4 denotes the substrate, 200 denotes the stacked structure, 210 denotes a sacrificial layer, and 220 denotes the first dielectric layer;
it should be noted that, in order to ensure the requirements of the subsequent preparation process of the three-dimensional memory and the performance parameters of the device, the thickness of the first dielectric layer located in the first step of the stacked structure in the step region, which is far away from the substrate, is much greater than the thickness of the first dielectric layers in the other steps, and generally, the thickness of the first dielectric layer is five to six times that of the other first dielectric layers.
S102: forming a protective film layer on the surface of the stacked structure in the step area;
referring to fig. 5, fig. 5 is a schematic cross-sectional view of the substrate and the surface structure thereof after step S102, where reference numeral 230 in fig. 5 denotes the protection film layer;
as shown in fig. 5, in the first step of the stacked structure located in the step region, the thickness of the first dielectric layer far away from the substrate is much greater than the thickness of the first dielectric layers in other steps, so that after the protective film layer is formed, the thickness of the protective film layer covering the sidewall of the first step in the vertical direction is greater, and thus, in the subsequent etching process of the protective film layer, after the protective film layers covering other steps are all etched, the protective film layer covering the sidewall of the first step is partially retained, so as to protect the first step in the subsequent process.
S103: and etching the protective film layer to form a protective structure on the side wall of the first-stage step of the stacking structure closest to the substrate, wherein the protective structure at least covers a first dielectric layer and a sacrificial layer closest to the substrate.
Referring to fig. 6, fig. 6 is a schematic cross-sectional view of the stacked structure on the surface of the step region after step S103, and reference numeral 231 in fig. 6 denotes the protection structure.
The preparation method of the three-dimensional memory comprises the steps of forming a stacked structure positioned in an array area and a step area on the surface of a substrate, forming a protective film layer on the surface of the stacked structure positioned in the step area, and etching the protective film layer, wherein the thickness of a step closest to the substrate is far larger than the thickness of other steps due to the requirements of the process and device parameters of the three-dimensional memory, so that the height of the protective film layer closest to the side wall of the step closest to the substrate is larger than that of the protective film layers of the side walls of other steps, and in the etching process, after the etching of the protective film layers of other steps is finished, a part of the protective film layer closest to the side wall of the step closest to the substrate is reserved, and the reserved protective film layer becomes a protective structure attached to the side wall of the step closest to the substrate, so that the protection of a first dielectric layer and a sacrificial layer closest to the substrate is realized, the situation that the first dielectric layer reacts due to contact with other substrates in the subsequent preparation process is avoided, so that the situation that an unnecessary oxidation structure is formed in the substrate is avoided, and the device performance of the finally formed three-dimensional memory is improved.
On the basis of the above embodiments, in an embodiment of the present application, as shown in fig. 7, the forming a protective film layer on a surface of the stacked structure located in the step area includes:
s1021: depositing a preset material on the surface of the stacked structure positioned in the step area to form the protective film layer;
the etching selection ratio of the preset material to the first dielectric layer is greater than a preset value;
and the etching selection ratio of the preset material to the sacrificial layer is greater than a preset value.
The material with the larger etching selection Ratio (Selective Ratio) can be used for etching only the protective film layer in the subsequent etching process of the protective film layer, and the etching rate of the first dielectric layer and the sacrificial layer is reduced as much as possible, so that most of the protective film layer is finally etched and removed without damaging the first dielectric layer and the sacrificial layer.
Optionally, the predetermined material is silicon oxynitride (SiON) or Polysilicon (Polysilicon) or amorphous silicon (a-Si). In a preferred embodiment of the present application, the predetermined material is silicon oxynitride, that is, the protective film layer is a silicon oxynitride film layer, and the protective structure is a silicon oxynitride protective structure. However, the present application is not limited thereto, and the details may be determined according to actual circumstances.
On the basis of the foregoing embodiment, in another embodiment of the present application, as shown in fig. 8, the etching the protection film layer includes:
s1031: and etching the protective film layer by adopting a reactive ion etching method.
Reactive Ion Etching (RIE) is one of dry Etching methods, and Etching of the protective film can be completed only by one rf source. In other embodiments of the present application, an Inductively Coupled Plasma (ICP) process may also be used to etch the protective film. The present application does not limit this, which is determined by the actual situation.
On the basis of the foregoing embodiment, in another embodiment of the present application, as shown in fig. 9, after the etching the protection film layer, the method further includes:
s104: growing monocrystalline silicon in the groove to obtain a monocrystalline silicon upright post;
s105: etching the monocrystalline silicon upright column to enable the monocrystalline silicon upright column to be flush with the surface of the substrate;
s106: etching to remove the sacrificial layer of the stacked structure, and forming a storage dielectric layer and a metal gate between the adjacent first dielectric layers;
s107: and growing a polycrystalline silicon layer and a polycrystalline silicon medium layer on the surface of the monocrystalline silicon upright column to form a channel.
Specifically, referring to fig. 10, the etching to remove the sacrificial layer of the stacked structure and form a storage dielectric layer and a metal gate between adjacent first dielectric layers includes:
s1061: etching and removing the sacrificial layer of the stacked structure to provide a space for the growth of the storage medium layer;
s1062: growing a first oxide layer on the surface of the first dielectric layer;
s1063: growing a first nitride layer on the surface of the first oxide layer;
s1064: growing a second oxide layer on the surface of the first nitride layer, wherein the first oxide layer, the first nitride layer and the second oxide layer form the storage medium layer;
s1065: and depositing a metal gate on the surface of the second oxide layer.
The sacrificial layer is preferably a silicon nitride layer, and the first dielectric layer is preferably a silicon oxide layer; the sacrificial layer needs to be removed by an etching process in the subsequent manufacturing steps to provide a preparation space for structures such as a metal gate and a storage medium layer, and therefore the difficulty of the process for removing the sacrificial layer can be reduced by selecting silicon nitride which is easy to remove. The first dielectric layer generally exists as an insulating layer, so that a silicon oxide layer with good isolation performance is selected as the first dielectric layer, and in addition, silicon nitride and silicon oxide are common semiconductor materials, so that the preparation process is mature, and the cost is low.
Optionally, the first nitride layer is a silicon nitride layer;
the first oxide layer is a silicon oxide layer;
the second oxide layer is a silicon oxide layer or an aluminum oxide layer or a hafnium oxide layer.
In this embodiment, the storage medium layer is also referred to as an ONO (oxide-nitride-oxide) storage structure. The reason why the ONO memory structure is used as the memory structure layer is that the combination of silicon oxide and the substrate is better than that of silicon nitride, and the silicon nitride layer is centered, so the three-layer structure can be complemented, and the device performance can be improved.
On the basis of the above embodiments, in other embodiments of the present application, the storage medium layer further includes: and the high-K (high dielectric constant) dielectric layer is positioned on the surface of the second oxide layer.
In this embodiment, the storage medium layer is formed by a four-layer composite structure, and the specific structure of the storage medium layer is not limited in this application and is determined according to the actual situation.
On the basis of the foregoing embodiment, in another specific embodiment of the present application, as shown in fig. 11, the growing a polysilicon layer and a polysilicon dielectric layer on the surface of the single-crystal silicon pillar, and forming a channel includes:
s1071: growing polycrystalline silicon on the surfaces of the monocrystalline silicon upright posts and the first grooves to form a polycrystalline silicon layer with second grooves;
s1072: growing a polysilicon medium layer in the second groove to fill the second groove;
s1073: etching the polysilicon medium layer to enable the height of the polysilicon medium layer to be smaller than that of the polysilicon layer;
s1074: and growing polysilicon on the surface of the polysilicon dielectric layer so that the polysilicon layer wraps the polysilicon dielectric layer.
In summary, the embodiment of the present application provides a method for manufacturing a three-dimensional memory, in which after a stacked structure located in an array region and a step region is formed on a surface of a substrate, a protective film layer is formed on a surface of the stacked structure located in the step region, and the protective film layer is etched, because the thickness of a step closest to the substrate is much greater than the thickness of other steps due to requirements of a process and device parameters of the three-dimensional memory, the height of the protective film layer closest to the sidewall of the step closest to the substrate is greater than the height of the protective film layers of the sidewalls of other steps, and during an etching process, when the etching of the protective film layers of other steps is completed, a part of the protective film layer closest to the sidewall of the step closest to the substrate remains, and the remaining part of the protective film layer becomes a protective structure attached to the sidewall of the step closest to the substrate, therefore, the first dielectric layer and the sacrificial layer which are closest to the substrate are protected, the condition that the first dielectric layer reacts due to contact with other substrates in the subsequent preparation process is avoided, the condition that an unnecessary oxidation structure is formed in the substrate is avoided, and the device performance of the finally formed three-dimensional memory is improved.
Correspondingly, an embodiment of the present application further provides a three-dimensional memory, including: the device comprises a substrate, wherein one side surface of the substrate comprises an array area and step areas positioned on two sides of the array area; the array structure comprises a substrate, an array region and a step region, wherein the array region and the step region are arranged on the substrate in a parallel mode, the step region is arranged on the substrate in a parallel mode, the array region and the step region are arranged in a parallel mode, the stacking structure comprises a plurality of layers of metal gates, a plurality of layers of first dielectric layers and a plurality of layers of storage dielectric layers, the metal gates and the first dielectric layers are located on two sides of the channels and are alternately stacked, and the storage dielectric layers are located between the metal gates and the channels and; the contact hole is positioned on the surface of one end, away from the substrate, of the channel and used for connecting a bit line and a word line; the three-dimensional memory further includes: the protective structure is positioned on the side wall of the stacking structure of the step area, at least one first dielectric layer and one storage dielectric layer which are closest to the substrate are covered by the protective structure, and the three-dimensional memory is prepared by the preparation method of the three-dimensional memory in any embodiment;
the protection structure is made of a preset material, and the etching selection ratio of the preset material to the first medium layer is greater than a preset value;
and the etching selection ratio of the preset material to the sacrificial layer is greater than a preset value.
Optionally, the first dielectric layer is preferably a silicon oxide layer;
the first nitride layer is a silicon nitride layer;
the first oxide layer is a silicon oxide layer;
the second oxide layer is a silicon oxide layer or an aluminum oxide layer or a hafnium oxide layer.
In this embodiment, the storage medium layer is also referred to as an ONO (oxide-nitride-oxide) storage structure. The reason why the ONO memory structure is used as the memory structure layer is that the combination of silicon oxide and the substrate is better than that of silicon nitride, and the silicon nitride layer is centered, so the three-layer structure can be complemented, and the device performance can be improved.
On the basis of the above embodiments, in other embodiments of the present application, the storage medium layer further includes: and the high-K (high dielectric constant) dielectric layer is positioned on the surface of the second oxide layer.
In this embodiment, the storage medium layer is formed by a four-layer composite structure, and the specific structure of the storage medium layer is not limited in this application and is determined according to the actual situation.
Preferably, the substrate is a P-type substrate
In summary, the embodiment of the present application provides a three-dimensional memory and a method for manufacturing the same, in which after a stacked structure located in an array region and a step region is formed on a surface of a substrate, a protective film layer is formed on a surface of the stacked structure located in the step region, and the protective film layer is etched, because the thickness of a step closest to the substrate is much greater than the thickness of other steps due to requirements of a process and device parameters of the three-dimensional memory, the height of the protective film layer closest to the sidewall of the step closest to the substrate is greater than the height of the protective film layers of the other step sidewalls, and during etching, when the etching of the protective film layers of the other steps is completed, a part of the protective film layer closest to the sidewall of the step closest to the substrate remains, and the remaining part of the protective film layer becomes a protective structure attached to the sidewall of the step closest to the substrate, therefore, the first dielectric layer and the sacrificial layer which are closest to the substrate are protected, the condition that the first dielectric layer reacts due to contact with other substrates in the subsequent preparation process is avoided, the condition that an unnecessary oxidation structure is formed in the substrate is avoided, and the device performance of the finally formed three-dimensional memory is improved.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A method for preparing a three-dimensional memory is characterized by comprising the following steps:
providing a substrate, wherein the surface of the substrate is provided with a plurality of stacked structures, the plurality of stacked structures are respectively located on an array area and the surfaces of two step areas of the substrate, the two step areas are respectively located on two sides of the array area, each stacked structure comprises a plurality of layers of first dielectric layers and sacrificial layers which are stacked in a staggered mode, the sacrificial layers are located between the adjacent first dielectric layers, a first groove is formed between every two stacked structures, the first groove is exposed out of the surface of the substrate, and the stacked structures located on the surfaces of the step areas form multi-level steps;
forming a protective film layer on the surface of the stacked structure in the step area;
etching the protective film layer to form a protective structure on the side wall of the first-stage step of the stacked structure closest to the substrate, wherein the protective structure at least covers a first dielectric layer and a sacrificial layer closest to the substrate;
the forming of the protective film layer on the surface of the stacked structure in the step area comprises:
depositing a preset material on the surface of the stacked structure positioned in the step area to form the protective film layer;
the etching selection ratio of the preset material to the first dielectric layer is greater than a preset value;
and the etching selection ratio of the preset material to the sacrificial layer is greater than a preset value.
2. The method of claim 1, wherein the predetermined material is silicon oxynitride or polysilicon or amorphous silicon.
3. The method of claim 1, wherein the etching the protective film layer comprises:
and etching the protective film layer by adopting a reactive ion etching method.
4. The method of claim 1, wherein after the etching the protective film layer, further comprising:
growing monocrystalline silicon in the groove to obtain a monocrystalline silicon upright post;
etching the monocrystalline silicon upright column to enable the monocrystalline silicon upright column to be flush with the surface of the substrate;
etching to remove the sacrificial layer of the stacked structure, and forming a storage dielectric layer and a metal gate between the adjacent first dielectric layers;
and growing a polycrystalline silicon layer and a polycrystalline silicon medium layer on the surface of the monocrystalline silicon upright column to form a channel.
5. The method of claim 4, wherein the etching to remove the sacrificial layer of the stacked structure and form a storage dielectric layer and a metal gate between adjacent first dielectric layers comprises:
etching and removing the sacrificial layer of the stacked structure to provide a space for the growth of the storage medium layer;
growing a first oxide layer on the surface of the first dielectric layer;
growing a first nitride layer on the surface of the first oxide layer;
growing a second oxide layer on the surface of the first nitride layer, wherein the first oxide layer, the first nitride layer and the second oxide layer form the storage medium layer;
and depositing a metal gate on the surface of the second oxide layer.
6. The method of claim 4, wherein growing a polysilicon layer and a polysilicon dielectric layer on the surface of the single-crystal silicon pillar and forming a channel comprises:
growing polycrystalline silicon on the surfaces of the monocrystalline silicon upright posts and the first grooves to form a polycrystalline silicon layer with second grooves;
growing a polysilicon medium layer in the second groove to fill the second groove;
etching the polysilicon medium layer to enable the height of the polysilicon medium layer to be smaller than that of the polysilicon layer;
and growing polysilicon on the surface of the polysilicon dielectric layer so that the polysilicon layer wraps the polysilicon dielectric layer.
7. A three-dimensional memory, comprising: the device comprises a substrate, wherein one side surface of the substrate comprises an array area and step areas positioned on two sides of the array area; the array region and the step region of the substrate are provided with a plurality of channels and a plurality of layers of stacked structures which are arranged in parallel, the stacked structures comprise a plurality of layers of metal gates, a plurality of layers of first dielectric layers and a plurality of layers of storage dielectric layers, the metal gates, the first dielectric layers and the storage dielectric layers are positioned on two sides of the channels and are alternately stacked, and the storage dielectric layers are positioned between the metal gates and the channels and are in contact with the surface of the substrate; the contact hole is positioned on the surface of one end, away from the substrate, of the channel and used for connecting a bit line and a word line; it is characterized in that the preparation method is characterized in that,
the three-dimensional memory further includes: a protective structure located on the side wall of the stacked structure in the step area, wherein the protective structure at least covers a first dielectric layer and a storage dielectric layer which are closest to the substrate, and the three-dimensional memory is prepared by the preparation method of the three-dimensional memory according to any one of claims 1-6;
the protection structure is made of a preset material, and the etching selection ratio of the preset material to the first medium layer is greater than a preset value;
and the etching selection ratio of the preset material to the sacrificial layer is greater than a preset value.
8. The three-dimensional memory according to claim 7, wherein the first dielectric layer is a silicon oxide layer.
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