CN107862379A - Neutral net FPGA - Google Patents

Neutral net FPGA Download PDF

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Publication number
CN107862379A
CN107862379A CN201710602634.8A CN201710602634A CN107862379A CN 107862379 A CN107862379 A CN 107862379A CN 201710602634 A CN201710602634 A CN 201710602634A CN 107862379 A CN107862379 A CN 107862379A
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unit
neuron
input
multiplication
adder
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廖永波
李红梅
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

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Abstract

Neutral net FPGA, it is related to integrated circuit technique, the present invention includes N number of neuron circuit, and each neuron circuit includes：N number of first multiplication unit, is exported respectively as one of input of the first adder unit；First adder unit, its output end are connected to the first input end of the 4th adder unit；N number of second multiplication unit, the output of each second multiplication unit is respectively as one of input of the second adder unit；Second adder unit, its output end are connected to an input of the 3rd adder unit；N number of neuron multiplication unit, the output of each neuron multiplication unit is respectively as one of input of the 3rd adder unit；3rd adder unit, it exports the second input of the 4th adder unit of termination；4th adder unit, it exports the input of termination function unit；Function unit, it exports the first input end for terminating neuron multiplication unit corresponding with the neuron circuit where it.Arithmetic speed of the present invention is fast, resource consumption is few.

Description

Neutral net FPGA
Technical field
The present invention relates to integrated circuit technique.
Background technology
Neutral net has the advantages that arithmetic speed is fast, consumption resource is few, applies to all many-sided and achieves preferable knot Fruit, there is very high research and applying value.
FPGA digital integrated electronic circuits have the advantages that the development time is short, flexibility is high, are especially suitable for a small amount of product customization.
The content of the invention
The technical problem to be solved by the invention is to provide a kind of FPGA for neural network computing, has and transports at a high speed The advantages of calculation.
It is neutral net FPGA, it is characterised in that including N that the present invention, which solves the technical scheme that the technical problem uses, Individual neuron circuit, N are the integer more than 1, wherein, each neuron circuit includes following part：
N number of first multiplication unit, each first multiplication unit include two inputs and an output end；Each first multiplies The output of method unit is respectively as one of input of the first adder unit；
First adder unit, its output end are connected to the first input end of the 4th adder unit；
N number of second multiplication unit, each second multiplication unit include two inputs and an output end；Each second multiplies The output of method unit is respectively as one of input of the second adder unit；
Second adder unit, its output end are connected to an input of the 3rd adder unit；
N number of neuron multiplication unit, each neuron multiplication unit include two inputs and an output end；Each god Output through first multiplication unit is respectively as one of input of the 3rd adder unit；Each neuron multiplication unit and each nerve First circuit corresponds；
3rd adder unit, it exports the second input of the 4th adder unit of termination；
4th adder unit, it exports the input of termination function unit；
Function unit, it exports the first input for terminating neuron multiplication unit corresponding with the neuron circuit where it End.
The invention has the advantages that neuron behavior is quantified and represents it with multiply-add operation by the present invention with digital quantity Between the relation that influences each other, have the advantages that arithmetic speed is fast, resource consumption is few with this integrated neuron circuit chip.
Brief description of the drawings
Fig. 1 be neuronal quantity be 2 when, the annexation figure of first neuron.
Fig. 2 be neuronal quantity be 2 when, the annexation figure of second neuron.
Fig. 3 be neuronal quantity be 2 when, the circuit diagram of first neuron.
Fig. 4 be neuronal quantity be 2 when, the circuit diagram of second neuron.
Fig. 5 be neuronal quantity be 3 when, the annexation figure of first neuron.
Fig. 6 be neuronal quantity be 3 when, the annexation figure of second neuron.
Fig. 7 be neuronal quantity be 3 when, the annexation figure of the 3rd neuron.
Fig. 8 be neuronal quantity be 3 when, the circuit diagram of first neuron.
Fig. 9 be neuronal quantity be 3 when, the circuit diagram of second neuron.
Figure 10 be neuronal quantity be 3 when, the circuit diagram of the 3rd neuron.
Figure 11 is neuronal quantity when being N, the annexation figure of the 1st neuron.
Figure 12 is neuronal quantity when being N, the annexation figure of the 2nd neuron.
Figure 13 is neuronal quantity when being N, the annexation figure of i-th of neuron.
Figure 14 is neuronal quantity when being N, the circuit diagram of the 1st neuron.
Figure 15 is neuronal quantity when being N, the circuit diagram of the 2nd neuron.
Figure 16 is neuronal quantity when being N, the circuit diagram of i-th of neuron.
Figure 17 is the annexation figure of the neuron of embodiment 4.
Embodiment
Neutral net FPGA, including N number of neuron circuit, wherein, each neuron circuit includes following part：
N number of first multiplication unit, each first multiplication unit include two inputs and an output end；Each first multiplies The output of method unit is respectively as one of input of the first adder unit；
First adder unit, its output end are connected to the first input end of the 4th adder unit；
N number of second multiplication unit, each second multiplication unit include two inputs and an output end；Each second multiplies The output of method unit is respectively as one of input of the second adder unit；
Second adder unit, its output end are connected to an input of the 3rd adder unit；
N number of neuron multiplication unit, each neuron multiplication unit include two inputs and an output end；Each god Output through first multiplication unit is respectively as one of input of the 3rd adder unit；Each neuron multiplication unit and each nerve First circuit corresponds；
3rd adder unit, it exports the second input of the 4th adder unit of termination；
4th adder unit, it exports the input of termination function unit；
Function unit, it exports the first input end for terminating neuron multiplication unit corresponding with this neuron circuit.
Embodiment 1：Neuronal quantity is 2 embodiment
Referring to Fig. 1~4.
Neuron, f () representative function unit are represented with X, the present embodiment includes two neurons of X1, X2, Fig. 1 first Individual neuron X1 circuit diagram, Fig. 2 are second neuron X2 circuit diagram.The circuit diagram structure of two neuron circuits is phase With.
Fig. 1,3 show first neuron circuit, including：
Two the first multiplication units (mark is and 12 in figure), each first multiplication unit includes two inputs and one Individual output end；The output of each first multiplication unit respectively as one of input of the first adder unit, the first adder unit by Formed labeled as 13,14 two adders；
First adder unit, its output end are connected to the first input end of the 4th adder unit 15；
Two the second multiplication units (mark is and 17 in figure), each second multiplication unit includes two inputs and one Individual output end；The output of each second multiplication unit is respectively as one of input of the second adder unit；
Second adder unit, it is made up of two adders (being labeled as 18,19), its output end is connected to the 3rd adder unit An input；
Two neuron multiplication units (being labeled as 23 and 24), each neuron multiplication unit includes two inputs and one Individual output end；The output of each neuron multiplication unit is respectively as one of input of the 3rd adder unit；Each neuron multiplies Method unit corresponds with each neuron circuit, such as the present embodiment has two neuron circuits, there is two nerves accordingly First multiplication unit, each neuron circuit are corresponding with a neuron multiplication unit；
3rd adder unit, it is made up of three adders (being labeled as 20,21,22), it exports the 4th adder unit of termination 15 the second input；
4th adder unit 15, it exports the input of termination function unit；
Function unit, it exports the first input for terminating neuron multiplication unit corresponding with the neuron circuit where it End.
As it was previously stated, each neuron circuit is corresponding with a neuron multiplication unit, the present embodiment has two neurons Circuit, therefore have two neuron multiplication units (being labeled as 23,24) in Fig. 1.Function unit in Fig. 1 is located at first nerve First circuit, i.e. neuron circuit where the function unit is using X1 as the neuron circuit indicated, corresponding neuron multiplication Mark is in unit figure, and the output termination of the function unit is labeled as the input of 23 neuron multiplication unit.
Embodiment 2：Neuronal quantity is 3 embodiment
Refer to Fig. 5~10.
Embodiment 3：Embodiment when neuronal quantity is N, N are the integer more than 8.
Figure 11~13 show the annexation figure of the 1st, the 2nd and i-th of neuron, and Figure 14 shows the present embodiment In first neuron circuit, Figure 15 shows that second neuron circuit, Figure 16 are shown in the present embodiment in the present embodiment I-th of neuron circuit.
Embodiment 4
By taking 2x2x1 neural network structure as an example, in fig. 17, it is real using circuit for the present invention that dotted line circle lives part Now part, is the input layer and hidden layer of neutral net, and dotted line does not enclose the output layer that part is neutral net.
Known excitation：Input stimulus, target excitation；
Purpose：Neutral net is trained, and tests neutral net.
The first step：Neutral net is initialized, using the interconnected relationship (W between random number generator generation layerin, Wback, W).
Second step：In the t times iteration, pass through the input stimulus of last iteration and the target excitation of this iteration and shape State X calculates the state X of next iteration, can obtain x (t+1)=f (Win*U(t)+W*X(t)+Wback*Ytarget(t)), f herein (x)=tanh (x) represents activation primitive.
3rd step：When training neutral net, W is calculatedout=Yout(t+1)/X(t+1)。
4th step：According to Yout(t+1)=g (Wout* X (t+1)) (g (x)=sign (x) represents activation primitive herein) calculating Yout, and calculation error function error=(Y (t+1)out-Ytarget)^2.When error function error value meets setting accuracy When, deconditioning；Or iterations is when reaching maximum iteration, deconditioning.
5th step：The neutral net now obtained just can be used for the test of new input value.

Claims (1)

1. neutral net FPGA, it is characterised in that including N number of neuron circuit, N is the integer more than 1, wherein, each god Include following part through first circuit：
N number of first multiplication unit, each first multiplication unit include two inputs and an output end；Each first multiplication list The output of member is respectively as one of input of the first adder unit；
First adder unit, its output end are connected to the first input end of the 4th adder unit；
N number of second multiplication unit, each second multiplication unit include two inputs and an output end；Each second multiplication list The output of member is respectively as one of input of the second adder unit；
Second adder unit, its output end are connected to an input of the 3rd adder unit；
N number of neuron multiplication unit, each neuron multiplication unit include two inputs and an output end；Each neuron The output of multiplication unit is respectively as one of input of the 3rd adder unit；Each neuron multiplication unit and each neuron electricity Road corresponds；
3rd adder unit, it exports the second input of the 4th adder unit of termination；
4th adder unit, it exports the input of termination function unit；
Function unit, it exports the first input end for terminating neuron multiplication unit corresponding with the neuron circuit where it.
CN201710602634.8A 2017-07-21 2017-07-21 Neutral net FPGA Pending CN107862379A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108549935A (en) * 2018-05-03 2018-09-18 济南浪潮高新科技投资发展有限公司 A kind of device and method for realizing neural network model
CN109376853A (en) * 2018-10-26 2019-02-22 电子科技大学 Echo State Networks export aixs cylinder circuit
CN110728366A (en) * 2019-10-23 2020-01-24 马卫东 Artificial neural network based on up-down counter

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN205139973U (en) * 2015-10-26 2016-04-06 中国人民解放军军械工程学院 BP neural network based on FPGA device founds
CN105488565A (en) * 2015-11-17 2016-04-13 中国科学院计算技术研究所 Calculation apparatus and method for accelerator chip accelerating deep neural network algorithm
CN106875012A (en) * 2017-02-09 2017-06-20 武汉魅瞳科技有限公司 A kind of streamlined acceleration system of the depth convolutional neural networks based on FPGA

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Publication number Priority date Publication date Assignee Title
CN205139973U (en) * 2015-10-26 2016-04-06 中国人民解放军军械工程学院 BP neural network based on FPGA device founds
CN105488565A (en) * 2015-11-17 2016-04-13 中国科学院计算技术研究所 Calculation apparatus and method for accelerator chip accelerating deep neural network algorithm
CN106875012A (en) * 2017-02-09 2017-06-20 武汉魅瞳科技有限公司 A kind of streamlined acceleration system of the depth convolutional neural networks based on FPGA

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Title
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108549935A (en) * 2018-05-03 2018-09-18 济南浪潮高新科技投资发展有限公司 A kind of device and method for realizing neural network model
CN109376853A (en) * 2018-10-26 2019-02-22 电子科技大学 Echo State Networks export aixs cylinder circuit
CN109376853B (en) * 2018-10-26 2021-09-24 电子科技大学 Echo state neural network output axon circuit
CN110728366A (en) * 2019-10-23 2020-01-24 马卫东 Artificial neural network based on up-down counter

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