CN107861295A - A kind of array base palte and preparation method thereof, display panel - Google Patents
A kind of array base palte and preparation method thereof, display panel Download PDFInfo
- Publication number
- CN107861295A CN107861295A CN201711200193.5A CN201711200193A CN107861295A CN 107861295 A CN107861295 A CN 107861295A CN 201711200193 A CN201711200193 A CN 201711200193A CN 107861295 A CN107861295 A CN 107861295A
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- China
- Prior art keywords
- array base
- base palte
- film transistor
- electrode
- layer
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Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
Abstract
The invention discloses a kind of array base palte, display panel and display device, the array base palte includes substrate；It is respectively arranged at the first public electrode on substrate, first film transistor；The pixel electrode being arranged in first film transistor；It is arranged in first film transistor, and covers the flatness layer of pixel electrode；The orientation film layer being arranged on flatness layer.The present invention enables to that the diffusion of alignment film is uniform, and display panel is flat, and display quality is more preferable.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of array base palte and preparation method thereof, display panel.
Background technology
Liquid crystal display device because its small volume, it is low in energy consumption, radiation it is low the features such as, occupy current panel display apparatus market
Leading position.Liquid crystal display device generally comprises the counter plate respectively containing pixel electrode and public electrode and is filled in
Liquid crystal between panel.When pixel electrode and public electrode are loaded certain electrical potential difference, liquid crystal can deflect under voltage effect, from
And change the polarization state for the light for inciding liquid crystal, make liquid crystal display device that respective image be presented.
Present inventor has found in long-term research and development, more with ITO (Indium tin in liquid crystal display device
Oxide, tin indium oxide) pixel electrode is used as, but ITO impedances are larger, are not appropriate for as electrode cable, therefore at present with gold
Category is used as electrode cable, is transmitted the electric signal that plain conductor carries to ITO pixel electrodes by transfer hole.But because switching
The presence in hole so that the orientation membrane diffusion being covered in transfer hole is uneven, and the marginal position of corresponding transfer hole is accumulated, and leads
Cause display panel uneven, influence display quality.
The content of the invention
The present invention provides a kind of array base palte and preparation method thereof, display panel, is turned with solving to be covered in the prior art
Connect the uneven technical problem of orientation membrane diffusion on hole.
In order to solve the above technical problems, one aspect of the present invention is to provide a kind of array base palte, including：
Substrate；
First public electrode, first film transistor, it is respectively arranged on the substrate；
Pixel electrode, it is arranged in the first film transistor；
Flatness layer, it is arranged in the first film transistor, and covers the pixel electrode；
Orientation film layer, it is arranged on the flatness layer.
In order to solve the above technical problems, another technical solution used in the present invention is to provide a kind of preparation of array base palte
Method, including：
The first public electrode and first film transistor are prepared on substrate respectively；
Pixel electrode is prepared in the first film transistor；
Flatness layer is prepared by coating and high annealing in the first film transistor, described in the flatness layer covering
Pixel electrode；
Orientation film layer is coated with the flatness layer.
In order to solve the above technical problems, another technical scheme that the present invention uses is to provide a kind of display panel, including
Above-mentioned array base palte.
The present invention realizes good planarization, enables to alignment film by setting flatness layer on thin film transistor (TFT)
Diffusion is uniform, and display panel is flat, and display quality is more preferable.
Brief description of the drawings
Technical scheme in order to illustrate the embodiments of the present invention more clearly, make required in being described below to embodiment
Accompanying drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for
For those of ordinary skill in the art, on the premise of not paying creative work, other can also be obtained according to these accompanying drawings
Accompanying drawing, wherein：
Fig. 1 is the structural representation of array base palte embodiment of the present invention；
Fig. 2 is the structural representation of array base palte embodiment of the present invention；
Fig. 3 is the schematic flow sheet of the preparation method embodiment of array base palte of the present invention；
Fig. 4 is the structural representation of display panel embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
Referring to Fig. 1 and Fig. 2, array base palte embodiment of the present invention includes：
Substrate 10；
First public electrode 20, first film transistor 30, are respectively arranged on substrate 10；
Wherein, first film transistor 30 includes grid 301, the first insulating barrier 701, source electrode 302 and drain electrode 303, grid
301 are arranged on substrate 10；First insulating barrier 701 is arranged on the public electrode 20 of grid 301 and first；Source electrode 302 is arranged at
On first insulating barrier 701；Drain electrode 303 is arranged on the first insulating barrier 701, and is connected with pixel electrode 40.
Optionally, drain electrode 303 can be connected with pixel electrode 40 by the first transfer hole 401.
Optionally, the first public electrode 20 can be connected by the second transfer hole 201.
Pixel electrode 40, it is arranged in first film transistor 30；
Scan line 801, it is arranged on substrate 10, and is located at same layer with the first public electrode 20；
Amorphous silicon layer 304, it is arranged on the first insulating barrier 701, and is located at same layer with source electrode 302, drain electrode 303；
Data wire 802, and 801 setting intersected with each other of scan line, and it is located at same layer with pixel electrode 40；
Second insulating barrier 702, it is arranged on source electrode 302, drain electrode 303 and amorphous silicon layer 304；
Optionally, amorphous silicon layer 304 includes the first amorphous silicon layer 3041 and the second amorphous silicon layer 3042, for coordinating grid
301st, the function of first film transistor 30 is realized in source electrode 302 and drain electrode 303；Raceway groove is formed in second amorphous silicon layer 3042, is made
Obtain the second insulating barrier 702 and form groove in the position of corresponding raceway groove.
Second thin film transistor (TFT) 901, is connected with first film transistor 30；
3rd thin film transistor (TFT) 902, it is connected with pixel electrode 40；
Flatness layer 50, it is arranged in first film transistor 30, and covers pixel electrode 40；
Optionally, flatness layer 50 covers the first transfer hole 401 and the second transfer hole 201, to cause flatness layer 50 away from institute
State the side planarization of the first transfer hole 401 and the second transfer hole 201.
Optionally, flatness layer 50 is transparent organic film, transparent organic film by PFA (Polytetrafluoro ethylene,
PFA plastics) it is made, PFA includes resin, multifunctional monomer, light initiator, solvent and additive.Wherein, light initiator is by benzene second
Ketone and benzophenone composition, can produce free radical under ultraviolet light；Multifunctional monomer is by a variety of mono-/bis -/multiple functional radicals
Monomer composition, interconnected under Free Radical caused by initiator, after monomer interconnection, the developer solution generation to alkalescence is supported
It is anti-；Resin is made up of polyester and epoxy acrylate, determines PFA main performance, such as developing property, mechanical property and chemistry
Performance etc.；Solvent is the lytic agent of PFA performance materials, by being evacuated and toasting volatilization in processing procedure, is seldom remained in final
In film layer；Additive is made up of the functional group of silane, for improving PFA flow leveling and adhesion property.
Optionally, flatness layer 50 can be acted on by organic coating and high-temperature annealing process levelability so that flatness layer 50
Side away from the first transfer hole 401, the second transfer hole 201 and groove planarizes.
Orientation film layer 60, it is arranged on flatness layer 50；
The embodiment of the present invention is good flat by by setting flatness layer on thin film transistor (TFT), being realized in the present invention
Change, enable to that the diffusion of alignment film is uniform, and display panel is flat, display quality is more preferable.
Referring to Fig. 1 and Fig. 3, the preparation method of array base palte of the present invention includes：
S101. the first public electrode 20 and first film transistor 30 are prepared on the substrate 10 respectively；
Specifically, prepare the first public electrode 20 and grid 301 on the substrate 10 respectively；In the first public electrode 20 and grid
The first insulating barrier 701 is covered on pole 301；Amorphous silicon layer 304 is prepared on the first insulating barrier 701；Made on the first insulating barrier 701
The standby drain electrode of source electrode 302/ 303, and the drain electrode of source electrode 302/ 303 parts covering amorphous silicon layer 304；Made in the drain electrode of source electrode 302/ 303
Standby second insulating barrier 702.Wherein, grid 301, the drain electrode of source electrode 302/ 303 and amorphous silicon layer 304 form first film transistor
30。
In the present embodiment, grid 301, the drain electrode of source electrode 302/ 303 can be prepared by the mode such as sputtering, etching；First
Insulating barrier 701, amorphous silicon layer 304 can be prepared by modes such as depositions.
S102. pixel electrode 40 is prepared in first film transistor 30；
In the present embodiment, pixel electrode 40 can be prepared by the mode such as sputtering, etching；
S103. flatness layer 50 is prepared by coating and high annealing in first film transistor 30；
In the present embodiment, flatness layer 50 covers pixel electrode 40；Wherein, flatness layer 50 can be organic film.
S104. orientation film layer 60 is coated with flatness layer 50.
In the present embodiment, orientation film layer 60 can be PI (Polyimide, polyimides) film.
The embodiment of the present invention is good flat by by setting flatness layer on thin film transistor (TFT), being realized in the present invention
Change, enable to that the diffusion of alignment film is uniform, and display panel is flat, the charging requirement of display panel reduces, and liquid crystal loading subtracts
Few, display quality is more preferable.
Referring to Fig. 4, display panel embodiment of the present invention includes above-mentioned array base palte 100, with array base palte 100 to setting
Put to row substrate 200 and be arranged at array base palte 100, to the liquid crystal 300 between row substrate 200.
Specifically, the structure of array base palte 100 is referring to above-mentioned array base palte embodiment in the embodiment of the present invention, herein no longer
Repeat.
Wherein, the second public electrode 2001 is provided with to row substrate 200, liquid crystal 300 is public in pixel electrode 40 and second
The lower deflection of voltage control formed between electrode 2001, is shown with the picture realized on display panel.Because array base palte 100 increases
Flatness layer 50 is added so that array base palte 100 to the distance between row substrate 200 with reducing, pixel electrode 40 and second public
Electric capacity between electrode 2001 reduces, and the charging requirement of display panel reduces, and liquid crystal loading also decreases in display panel.
The embodiment of the present invention is good flat by by setting flatness layer on thin film transistor (TFT), being realized in the present invention
Change, enable to that the diffusion of alignment film is uniform, and display panel is flat, the charging requirement of display panel reduces, and liquid crystal loading subtracts
Few, display quality is more preferable.
Embodiments of the present invention are the foregoing is only, are not intended to limit the scope of the invention, it is every to utilize this
The equivalent structure or equivalent flow conversion that description of the invention and accompanying drawing content are made, or directly or indirectly it is used in other correlations
Technical field, it is included within the scope of the present invention.
Claims (10)
- A kind of 1. array base palte, it is characterised in that including：Substrate；First public electrode, first film transistor, it is respectively arranged on the substrate；Pixel electrode, it is arranged in the first film transistor；Flatness layer, it is arranged in the first film transistor, and covers the pixel electrode；Orientation film layer, it is arranged on the flatness layer.
- 2. array base palte according to claim 1, it is characterised in that the thin film transistor (TFT) includes：Grid, it is arranged on the substrate；First insulating barrier, it is arranged on the grid and the first public electrode；Source electrode, it is arranged on first insulating barrier；Drain electrode, is arranged on first insulating barrier, and be connected with the pixel electrode.
- 3. array base palte according to claim 2, it is characterised in thatThe drain electrode is connected with the pixel electrode by the first transfer hole, passes through the second switching between first public electrode Hole connects.
- 4. array base palte according to claim 3, it is characterised in thatThe flatness layer covers first transfer hole and the second transfer hole, to cause the flatness layer away from the described first switching Hole and the planarization of the side of the second transfer hole.
- 5. array base palte according to claim 1, it is characterised in that the array base palte also includes：Scan line, it is arranged on the substrate, and is located at same layer with first public electrode；Amorphous silicon layer, it is arranged on first insulating barrier, and is located at same layer with the source electrode, drain electrode；Data wire, and scan line setting intersected with each other, and it is located at same layer with the pixel electrode；Second insulating barrier, it is arranged on the source electrode, drain electrode and amorphous silicon layer.
- 6. array base palte according to claim 1, it is characterised in that the array base palte also includes：Second thin film transistor (TFT), it is connected with the first film transistor；3rd thin film transistor (TFT), it is connected with the pixel electrode.
- 7. array base palte according to claim 1, it is characterised in thatThe flatness layer is transparent organic film.
- 8. array base palte according to claim 7, it is characterised in thatThe transparent organic film is made up of PFA, and the PFA includes resin, multifunctional monomer, light initiator, solvent and additive.
- A kind of 9. preparation method of array base palte, it is characterised in that including：The first public electrode and first film transistor are prepared on substrate respectively；Pixel electrode is prepared in the first film transistor；Flatness layer is prepared by coating and high annealing in the first film transistor, the flatness layer covers the pixel Electrode；Orientation film layer is coated with the flatness layer.
- 10. a kind of display panel, it is characterised in that including the array base palte as described in any one of claim 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711200193.5A CN107861295A (en) | 2017-11-24 | 2017-11-24 | A kind of array base palte and preparation method thereof, display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711200193.5A CN107861295A (en) | 2017-11-24 | 2017-11-24 | A kind of array base palte and preparation method thereof, display panel |
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| Publication Number | Publication Date |
|---|---|
| CN107861295A true CN107861295A (en) | 2018-03-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711200193.5A Pending CN107861295A (en) | 2017-11-24 | 2017-11-24 | A kind of array base palte and preparation method thereof, display panel |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109976017A (en) * | 2019-04-10 | 2019-07-05 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
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| JPH1020321A (en) * | 1996-07-09 | 1998-01-23 | Sharp Corp | Liquid crystal display device |
| US20020106839A1 (en) * | 2001-02-02 | 2002-08-08 | International Business Machines Corporation | Thin film transistor and method for manufacturing the same |
| CN101140399A (en) * | 2006-09-06 | 2008-03-12 | 索尼株式会社 | Liquid crystal device and electronic equipment |
| CN102466928A (en) * | 2010-11-09 | 2012-05-23 | Nlt科技股份有限公司 | Liquid crystal display device |
| CN104965365A (en) * | 2015-07-14 | 2015-10-07 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and array substrate thereof |
| CN105445969A (en) * | 2014-09-30 | 2016-03-30 | 群创光电股份有限公司 | Display panel |
| CN105655292A (en) * | 2016-01-05 | 2016-06-08 | 深圳市华星光电技术有限公司 | Liquid crystal display panel, array substrate and manufacturing method thereof |
| CN105655290A (en) * | 2016-01-05 | 2016-06-08 | 深圳市华星光电技术有限公司 | Liquid crystal display panel, array substrate and manufacturing method thereof |
-
2017
- 2017-11-24 CN CN201711200193.5A patent/CN107861295A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1020321A (en) * | 1996-07-09 | 1998-01-23 | Sharp Corp | Liquid crystal display device |
| US20020106839A1 (en) * | 2001-02-02 | 2002-08-08 | International Business Machines Corporation | Thin film transistor and method for manufacturing the same |
| CN101140399A (en) * | 2006-09-06 | 2008-03-12 | 索尼株式会社 | Liquid crystal device and electronic equipment |
| CN102466928A (en) * | 2010-11-09 | 2012-05-23 | Nlt科技股份有限公司 | Liquid crystal display device |
| CN105445969A (en) * | 2014-09-30 | 2016-03-30 | 群创光电股份有限公司 | Display panel |
| CN104965365A (en) * | 2015-07-14 | 2015-10-07 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and array substrate thereof |
| CN105655292A (en) * | 2016-01-05 | 2016-06-08 | 深圳市华星光电技术有限公司 | Liquid crystal display panel, array substrate and manufacturing method thereof |
| CN105655290A (en) * | 2016-01-05 | 2016-06-08 | 深圳市华星光电技术有限公司 | Liquid crystal display panel, array substrate and manufacturing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109976017A (en) * | 2019-04-10 | 2019-07-05 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN109976017B (en) * | 2019-04-10 | 2021-09-24 | 深圳市华星光电半导体显示技术有限公司 | Display panel and manufacturing method thereof |
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| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: No.9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant after: TCL Huaxing Photoelectric Technology Co.,Ltd. Address before: No.9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |
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Application publication date: 20180330 |
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| RJ01 | Rejection of invention patent application after publication |