CN107851647B - Imaging device, manufacturing method, and substrate dividing method - Google Patents

Imaging device, manufacturing method, and substrate dividing method Download PDF

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Publication number
CN107851647B
CN107851647B CN201680039846.3A CN201680039846A CN107851647B CN 107851647 B CN107851647 B CN 107851647B CN 201680039846 A CN201680039846 A CN 201680039846A CN 107851647 B CN107851647 B CN 107851647B
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substrate
chip
layer
adhesive layer
groove
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CN107851647A (en
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山口征也
高地泰三
古濑骏介
大井上昂志
池边祐希
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/1469—Assemblies, i.e. hybrid integration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H01L27/14627—Microlenses

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Laser Beam Processing (AREA)
  • Dicing (AREA)

Abstract

The invention provides a semiconductor device and a semiconductor device forming method, the semiconductor device includes: a first substrate; and a second substrate adjacent to the first substrate, wherein the sidewall of the second substrate includes one or more cuts, which may include a blade cut and a stealth cut. The present invention also provides an image pickup apparatus and an image pickup apparatus forming method, the image pickup apparatus including: a first substrate; a transparent layer; an adhesive layer between the first substrate and the transparent layer; a second substrate, wherein the first substrate is disposed between the adhesive layer and the second substrate; and a groove extending from the adhesive layer to the second substrate, wherein the groove is filled with the adhesive layer.

Description

Imaging device, manufacturing method, and substrate dividing method
Technical Field
The presently disclosed technology relates to an image pickup apparatus, a manufacturing method, and a substrate dividing method. More particularly, the present invention relates to an image pickup apparatus capable of improving moisture resistance, a manufacturing method, and a substrate dividing method.
Cross Reference to Related Applications
The present application claims the benefits of japanese priority patent applications JP 2015-147145 and JP 2016-123597, filed 24/2015 and 22/2016, respectively, and the entire contents of these two patent applications are hereby incorporated by reference.
Background
Recently, the following image pickup apparatuses are used as a digital video camera, a digital still camera, or the like: in the image pickup apparatus, a plurality of Charge Coupled Devices (CCDs), a plurality of complementary metal-oxide semiconductor (CMOS) devices, or the like are arranged in a two-dimensional shape.
As a method of realizing simultaneous accumulation of charges in a CMOS image sensor, the related art discloses a global shutter structure having a structure for temporarily storing a signal in a memory. The global shutter structure is configured to: exposure times of all pixels are synchronized with each other by arranging memories in the respective pixels, transferring charges accumulated in light receiving portions of all pixels in a batch manner, and storing the charges until reading is performed for each row (see PTL 1 and PTL 2).
Reference list
Patent document
PTL 1：JP 2012-129797 A
PTL 2：JP 2013-21533 A
Disclosure of Invention
Technical problem
The imaging device is manufactured by manufacturing a plurality of imaging devices on a substrate and dividing (dicing) the substrate at the time of manufacture. In such a division, film peeling, cracking, or other problems may occur. Since film peeling, cracking, or other problems occur, water may penetrate into the image pickup device and cause dew condensation, resulting in deterioration of image quality.
It is desirable to maintain and improve moisture resistance during and after the manufacture of the image pickup device.
The technology disclosed herein has been made in view of the above circumstances, and is designed to improve moisture resistance, among other advantages.
Technical scheme for solving problems
According to various embodiments of the present invention, there is provided a semiconductor device including: a first substrate; and a second substrate adjacent to the first substrate, wherein a sidewall of the second substrate includes a blade cut and a stealth cut.
Various embodiments may include an image pickup apparatus, wherein the first substrate is disposed between a transparent layer and the second substrate.
Various embodiments may include an image pickup device further including an adhesive layer between the first substrate and the transparent layer.
Various embodiments may include an image pickup device further including a groove extending from the adhesive layer to the second substrate.
Various embodiments may include an image pickup device, wherein the transparent layer is a cover glass layer and the adhesive layer is a resin.
Various embodiments may include an imaging device, wherein the invisible cut and the blade cut extend to the groove.
Various embodiments may include an imaging device, wherein the invisible cut is further from the groove than the blade cut.
According to further various embodiments of the present invention, there is provided an image pickup apparatus including: a first substrate; a transparent layer; an adhesive layer between the first substrate and the transparent layer; a second substrate, wherein the first substrate is disposed between the adhesive layer and the second substrate; and a groove extending from the adhesive layer to the second substrate, wherein the groove is filled with the adhesive layer.
Various embodiments may include an image capture device, wherein the adhesive layer is a resin.
Various embodiments may include an image capture device, wherein the transparent layer is a cover glass layer.
Various embodiments may include an image pickup device further including a microlens layer and a wiring layer, wherein the groove extends through the microlens layer and through the wiring layer such that the adhesive layer is in contact with the microlens layer, the wiring layer, and the first substrate.
Various embodiments may include an image pickup device, wherein the sidewall of the second substrate includes a blade cutting portion, and a width of the groove is greater than a width of a blade in contact with the blade cutting portion.
Various embodiments may include an image pickup apparatus further including a solder resist disposed on a bottom portion of the second substrate.
According to still further various embodiments of the present invention, there is provided an image pickup apparatus including: a transparent layer; a first substrate including a photoelectric conversion portion; a second substrate, wherein the first substrate is disposed between the transparent layer and the second substrate; and a microlens layer including microlenses for focusing incident light to the photoelectric conversion portions, wherein the second substrate includes first and second cut portions.
Various embodiments may include an image pickup device further including an adhesive layer between the first substrate and the transparent layer.
Various embodiments may include an image pickup device further including a groove extending from the adhesive layer to the second substrate, and the groove being filled with the adhesive layer.
Various embodiments may include an image pickup device further including a wiring layer, wherein the groove passes through the microlens layer and extends through the wiring layer.
Various embodiments may include an image pickup device, wherein the groove extends such that the adhesive layer is in contact with the microlens layer, the wiring layer, and the first substrate; and further various embodiments may include an image pickup device, wherein the adhesive layer is a resin.
Various embodiments may include a camera device, wherein the groove has a width greater than a width of a blade in contact with the first cutting portion and the second cutting portion.
The invention has the advantages of
According to various aspects of the technology disclosed herein, moisture resistance may be improved, among other advantages.
The above advantages are not limiting and other benefits may be realized.
Drawings
Fig. 1 is an explanatory block diagram showing a configuration example of a CMOS image sensor.
Fig. 2 is an explanatory diagram showing a configuration of a unit pixel.
Fig. 3 is an explanatory diagram showing the influence of moisture.
Fig. 4 is an explanatory diagram showing the configuration of the chip according to the first embodiment.
Fig. 5 is an explanatory diagram showing the configuration of the chip according to the first embodiment.
Fig. 6 is an explanatory diagram showing the manufacture of the chip according to the first embodiment.
Fig. 7 is an explanatory diagram showing the configuration of a chip according to the second embodiment.
Fig. 8 is an explanatory diagram showing the configuration of a chip according to the second embodiment.
Fig. 9 is an explanatory diagram showing the manufacture of a chip according to the second embodiment.
Fig. 10 is an explanatory diagram showing the configuration of a chip according to the third embodiment.
Fig. 11 is an explanatory diagram showing the configuration of a chip according to the third embodiment.
Fig. 12 is an explanatory diagram showing the size of the recess of the chip according to the third embodiment.
Fig. 13 is an explanatory diagram showing the manufacture of a chip according to the third embodiment.
Fig. 14 is an explanatory diagram showing the configuration of a chip according to the fourth embodiment.
Fig. 15 is an explanatory diagram showing the configuration of a chip according to the fourth embodiment.
Fig. 16 is an explanatory diagram showing the manufacture of a chip according to the fourth embodiment.
Fig. 17 is an explanatory view showing division using laser light.
Fig. 18 is an explanatory view showing the attachment of the debris.
Fig. 19 is an explanatory diagram showing a configuration of a chip divided by laser light.
Fig. 20 is an explanatory view showing the stealth dicing.
Fig. 21 is an explanatory diagram showing removal of the modified layer.
Fig. 22 is an explanatory diagram showing segmentation using stealth dicing.
Fig. 23 is an explanatory diagram showing a structure of a chip divided by stealth dicing.
Fig. 24 is an explanatory diagram showing a configuration of the electronic apparatus.
Fig. 25 is an explanatory block diagram showing an example of a schematic configuration of an internal information acquisition system to which an embodiment of the present invention is applied.
Detailed Description
Hereinafter, illustrative forms (hereinafter, referred to as embodiments) for practicing the presently disclosed technology will be described. The description will be made in the following order.
1. Structure of solid-state imaging device
2. Chip structure
3. First embodiment
4. Second embodiment
5. Third embodiment
6. Fourth embodiment
7. Splitting using optical lasers
8. Segmentation using stealth dicing
9. Electronic device
< illustrative construction of solid-State imaging device >
Fig. 1 is an explanatory block diagram showing a configuration example of a Complementary Metal Oxide Semiconductor (CMOS) image sensor as a solid-state imaging device according to an embodiment of the present invention.
In various embodiments, the CMOS image sensor 30 includes a pixel array unit 41, a vertical driving unit 42, a column processing unit 43, a horizontal driving unit 44, and a system control unit 45. The pixel array unit 41, the vertical driving unit 42, the column processing unit 43, the horizontal driving unit 44, and the system control unit 45 are formed on a semiconductor substrate (chip) not shown.
In the pixel array unit 41, unit pixels having photoelectric conversion elements that generate an amount of photoelectric charge corresponding to the intensity of incident light and store the photoelectric charge in the photoelectric conversion elements are two-dimensionally arranged in a matrix shape. In the following description, the amount of photoelectric charge corresponding to the intensity of incident light is simply referred to as "charge", and a unit pixel is simply referred to as a "pixel".
In the pixel array unit 41, for each row in a matrix-shaped pixel array, a pixel drive line 46 is formed in the left-right direction in the drawing (pixel arrangement direction in a pixel row), and for each column, a vertical signal line 47 is formed in the vertical direction in the drawing (pixel arrangement direction in a pixel column). One end of the pixel driving line 46 is connected to an output terminal of the vertical driving unit 42 corresponding to each row.
The CMOS image sensor 30 includes a signal processing unit 48 and a data storage unit 49. The signal processing unit 48 and the data storage unit 49 may be realized by an external signal processing unit (for example, a Digital Signal Processor (DSP) or software processing) disposed on a different substrate from that of the CMOS image sensor 30, or the signal processing unit 48 and the data storage unit 49 may be mounted on the same substrate as the CMOS image sensor 30.
The vertical driving unit 42 is a pixel driving unit that is constituted by a shift register, an address decoder, or the like and simultaneously drives the pixels of the pixel array unit 41 for all the pixels or for each row. Although a detailed configuration thereof is not illustrated, the vertical driving unit 42 is configured to include, for example, a reading scanning system and a clear scanning system or to have a batch clear function and a batch transfer function.
The reading scanning system sequentially and selectively scans the unit pixels of the pixel array unit 41 for each row to read signals from the unit pixels. In the row driving operation (rolling shutter operation), a clear scan operation is performed on a read row subjected to a read scan operation by the read scan system at a time earlier than the read scan operation by a time corresponding to the shutter speed. In the global exposure operation (global shutter operation), the batch clear operation may be performed at a time corresponding to the shutter speed instead of performing the batch transfer operation.
By this clearing operation, unnecessary electric charges can be cleared (reset) from the photoelectric conversion elements of the unit pixels of the read row. A so-called electronic shutter operation is performed by clearing (resetting) unnecessary electric charges. Here, the electronic shutter operation refers to an operation for discharging the photo-charges of the corresponding photoelectric conversion element and starting a new exposure (starting accumulation of the photo-charges).
The signal read by the reading operation of the reading scanning system corresponds to the incident light intensity in the previous reading operation or corresponds to the incident light intensity after the electronic shutter operation. In the row driving operation, a period from a reading timing in a previous reading operation or a clear timing in an electronic shutter operation to a reading timing in a current reading operation is a period (exposure period) in which photo-charges are accumulated in the unit pixel. In the global exposure operation, a period from the batch clear to the batch transfer is an accumulation period (exposure period).
Pixel signals output from the unit pixels in the pixel row selectively scanned by the vertical driving unit 42 are supplied to the column processing unit 43 via vertical signal lines 47, respectively. The column processing unit 43 performs predetermined signal processing on pixel signals output from the unit pixels of the selected row via the vertical signal lines 47 for each pixel column of the pixel array unit 41, and the column processing unit 43 temporarily stores the signal-processed pixel signals.
Specifically, as the signal processing, the column processing unit 43 performs at least noise canceling processing, for example, Correlated Double Sampling (CDS) processing. By the correlated double sampling processing of the column processing unit 43, it is possible to eliminate pixel-specific reset noise or fixed pattern noise such as threshold unevenness of the amplification transistor. In addition to the noise canceling process, the column processing unit 43 may be provided with, for example, an analog-to-digital (AD) conversion function, and the column processing unit 43 may output the signal level as a digital signal.
The horizontal driving unit 44 is configured by a shift register, an address decoder, or the like, and the horizontal driving unit 44 sequentially selects unit pixels corresponding to a pixel column of the column processing unit 43. The pixel signals processed by the column processing unit 43 are sequentially output to the signal processing unit 48 by selective scanning of the horizontal driving unit 44.
The system control unit 45 includes a timing generator for generating various timing signals, and the system control unit 45 controls the driving of the vertical driving unit 42, the column processing unit 43, the horizontal driving unit 44, and the like based on the various timing signals generated by the timing generator.
The signal processing unit 48 has at least an addition processing function, and performs various kinds of signal processing such as addition processing on the pixel signals output from the column processing unit 43. The data storage unit 49 temporarily stores data required for processing signals in the signal processing unit 48.
< illustrative Structure of chip >
An example of a specific structure of the unit pixels arranged in a matrix shape in the pixel array unit 41 in fig. 1 will be described below. A pixel to which the presently disclosed technology is applied may, for example, improve its moisture resistance and may improve performance as a sensor. To explain these exemplary advantageous effects, a pixel to which the presently disclosed technology is not applied will be explained first, and then a pixel to which the presently disclosed technology is applied will be explained.
Fig. 2 shows an illustrative configuration example of a chip in which a plurality of unit pixels are arranged. The chip shown in fig. 2 constitutes a backside illuminated CMOS image sensor before division.
The configuration shown in fig. 2 described below is merely an example, and the presently disclosed technology described herein may be applied to other configurations, for example, a configuration in which another layer is added or some layers are deleted from the layers described below.
In various illustrative embodiments, in the chip 70 shown in fig. 2, a wiring layer 72 formed of an insulating layer and a metal is disposed on a support substrate 71, and a silicon substrate 73 is disposed on the wiring layer 72. The support substrate 71 is formed of silicon, glass epoxy, glass, plastic, or other suitable material. A plurality of photodiodes 74 (optical elements) as photoelectric conversion portions of each pixel are formed at predetermined intervals in the silicon substrate 73.
A planarization film 75 formed of an insulator is formed on the silicon substrate 73 and the photodiode 74. In the planarization film 75, a light-shielding film 76 for preventing light from leaking into an adjacent pixel is formed between adjacent photodiodes 74.
A color filter layer 77 is formed on the planarization film 75 and the light-shielding film 76. The color filter layer 77 is provided with a plurality of color filters for each pixel, and the colors of the color filters are arranged based on a bayer array, for example.
A planarization film 78 is formed on the color filter layer 77. A microlens layer 79 is formed on the planarization film 78. In this way, the microlens layer 79 is disposed on the substrate having a plurality of layers including the photodiode 74. In the microlens layer 79, a microlens layer for focusing light on the photodiode 74 of each pixel is formed for each pixel. The microlens layer 79 is an inorganic material layer, and the microlens layer 79 is made of SiN, SiOxNy(wherein, 0 is satisfied)<x is less than or equal to 1 and 0<y is less than or equal to 1).
The cover glass 81 is bonded to the top of the microlens layer 79 using an adhesive layer 80, and the adhesive layer 80 is interposed between the cover glass 81 and the microlens layer 79. The cover glass 81 is not limited to glass, but a transparent plate of resin or the like may be employed. The adhesive layer 80 is formed of an acrylic-based resin material, a styrene-based resin material, an epoxy-based resin material, or the like.
In the chip 70 shown in fig. 2, there are a plurality of chips. Fig. 2 illustrates a state of the wafer in which three chips exist in the horizontal direction before dicing. In the wafer shown in fig. 2, the chip located at the center is referred to as a chip 70-1, the chip located at the left side is referred to as a chip 70-2, and the chip located at the right side is referred to as a chip 70-3.
A scribing part 91-1 is arranged between the chip 70-1 and the chip 70-2, and a scribing part 91-2 is arranged between the chip 70-1 and the chip 70-3. The chip shown in fig. 2 is divided into three chips by performing a dicing process on the scribe line portions 91-1 and 91-2.
Fig. 3 illustrates the chip 70-1 after singulation. The chip 70-1 shown in fig. 3 is a chip located at the center of the chip shown in fig. 2, and the chip 70-1 is the chip 70-1 divided by performing a cutting process on the scribing portion 91-1 and the scribing portion 91-2.
At the time of dicing, the edge may be peeled off due to a physical force applied to the chip 70-1 at the time of dicing. After dicing, moisture may penetrate into the sides or other areas of the chip 70-1. For example, a part of the sealing resin has a higher possibility of absorbing moisture than other parts. Moisture may also penetrate into, for example, an interface portion between the sealing resin and the glass or other interfaces.
When moisture penetrates into the chip 70-1, the metal material may corrode and cause breakage or other damage according to the penetration location, and the chip may not operate normally or optimally. For example, image unevenness or display failure may occur. Therefore, it is advantageous to perform the dicing operation in such a manner that no damage such as peeling or other damage is caused at the time of dicing, and to provide a structure that advantageously prevents or reduces the penetration of moisture into the chip 70-1.
A structure and a manufacturing process capable of preventing or reducing damage such as peeling or other damage occurring at the time of dicing to prevent or reduce moisture that may otherwise penetrate into the chip 70 will be described below. Chips according to various embodiments may have the configurations shown in fig. 2 and 3, and components useful for explaining the various embodiments are illustrated and described as appropriate.
< first embodiment >
The first embodiment is an embodiment in which damage at the time of dicing or moisture penetration into the chip is prevented or reduced by forming a groove in a predetermined layer of the chip.
Fig. 4 shows an illustrative configuration of a chip according to the first embodiment. Fig. 4 illustrates a state of the wafer in which a plurality of chips (e.g., three chips in fig. 4) exist before dicing (e.g., as shown in fig. 2). Each chip is a cavity-less Chip Size Package (CSP).
Here, the chip located at the center is referred to as a chip 100-1, the chip located at the left side is referred to as a chip 100-2, and the chip located at the right side is referred to as a chip 100-3. In the following description, when it is not necessary to distinguish the chips 100-1 to 100-3 individually, these chips are simply referred to as chips 100.
Each chip 100 may have the same configuration as the chip 70 described above with reference to fig. 2 and 3. That is, in the chip 100, the wiring layer 72 is disposed on the support substrate 71, and the silicon substrate 73 is disposed on the wiring layer 72. A plurality of photodiodes 74 (optical elements) as photoelectric conversion portions of each pixel are formed at predetermined intervals in the silicon substrate 73.
A planarization film 75 is formed on the silicon substrate 73, and a light-shielding film 76 for preventing light leakage into adjacent pixels is formed between adjacent photodiodes 74 in the planarization film 75. A color filter layer 77 is formed on the planarization film 75. A planarization film 78 is formed on the color filter layer 77. A microlens layer 79 is formed on the planarization film 78. The cover glass 81 is bonded to the top of the microlens layer 79 using an adhesive layer 80, and the adhesive layer 80 is interposed between the cover glass 81 and the microlens layer 79.
The adhesive layer 80 may be a member formed of a transparent resin and may fix the cover glass 81. The cover glass 81 may not be glass but a plate-shaped transparent member.
A solder resist 102 and connection terminals 103 for connection to an external circuit are also formed on the bottom of the support substrate 71. A through electrode 104-1 such as a Through Silicon Via (TSV) is also formed, and the through electrode 104-1, the connection terminal 103, and the wiring layer 72 are connected to each other.
The wafer shown in fig. 4 is provided with grooves 101 between the chips 100. Groove 101-1 is disposed between chip 100-1 and chip 100-2, and groove 101-2 is disposed between chip 100-1 and chip 100-3.
A scribing portion 91-1 is disposed between the chip 100-1 and the chip 100-2, and a groove 101-1 is disposed in the scribing portion 91-1. Likewise, a scribe portion 91-2 is disposed between the chip 100-1 and the chip 100-3, and a groove 101-2 is disposed in the scribe portion 91-2.
In the chip 100 shown in fig. 4, the groove 101 is arranged to dig into a part of the top of the microlens layer 79, the planarization film 78, the color filter layer 77, the planarization film 75, the silicon substrate 73, the wiring layer 72, and the support substrate 71.
As described later, since the groove 101 is formed before the adhesive layer 80 is formed and the adhesive layer 80 is formed after the groove 101 is formed, the groove 101 is filled with the same material as the adhesive layer 80. The material for the adhesive layer 80 may be a transparent resin. The groove 101 may be filled with a transparent resin.
When the wafer having the grooves 101 provided between the chips 100 is cut at the scribe line portion 91, the chip 100-1 as shown in fig. 5 is cut out. In the chip 100-1 shown in fig. 5, the microlens layer 79, the planarization film 78, the color filter layer 77, the planarization film 75, the silicon substrate 73, the wiring layer 72, and a part of the support substrate 71 are surrounded by the adhesive layer 80 so that their surfaces are not exposed.
That is, the microlens layer 79, the planarization film 78, the color filter layer 77, the planarization film 75, the silicon substrate 73, the wiring layer 72, and a part of the side surface of the support substrate 71 are covered with the same material as the adhesive layer 80.
In this way, the divided chip 100-1 has the following structure: in this structure, a portion of the stacked layers of the chip 100 is covered at the positions of the grooves 101-1 'and 101-2' (the grooves after dicing are denoted by adding a prime mark to the reference numeral to distinguish the grooves after dicing from the grooves 101-1 and 101-2 before dicing shown in fig. 4).
In this manner, in various embodiments, in order to obtain a structure in which the grooves 101-1 'and 101-2' remain in the chips 100-1 after division and the same material as the adhesive layer 80 remains in these portions, it is preferable that the width of the groove 101-1 or the groove 101-2 between the chips 100 before division be set larger than the width of the blade used for the dicing process.
In this way, by performing the cutting process in a state where the groove 101 is formed and the groove 101 is filled with the same material as the adhesive layer 80, the force applied to the interface between the films at the time of cutting can be reduced, and the possibility of occurrence of film peeling or cracking or other damage can be reduced. Since film peeling or cracking does not occur or is reduced, the moisture resistance of the chip can be improved.
Since the solder resist 102-1 is disposed on the bottom of the chip 100-1, the penetration of water into the chip 100-1 from the bottom can be prevented or reduced. An oxide film may be used instead of solder resist 102-1, and/or an oxide film may be stacked on solder resist 102-1.
< production of chip in first embodiment >
An illustrative method of manufacturing a chip (wafer) having the above-described grooves will be described. Fig. 6 is a diagram showing an illustrative process of manufacturing a chip before singulation.
For an illustrative manufacturing process to be described with reference to fig. 6, a process of forming a groove, which is a feature of the presently disclosed technology, will be described, and a manufacturing process of other parts (e.g., a process of forming a layer) may be performed using a conventional manufacturing method, and thus the description of the conventional manufacturing method will be appropriately omitted.
In step S101, a semiconductor wafer in which the photodiode 74 and other elements are formed is prepared. Thus, the semiconductor wafer has, for example, the support substrate 71, the wiring layer 72, the silicon substrate 73, the planarization film 75, the color filter layer 77, the planarization film 78, and the microlens layer 79 stacked, and the photodiode 74 is formed in the silicon substrate 73 and the light-shielding film 76 is formed in the planarization film 75.
In step S102, grooves 101-1 and grooves 101-2 are formed in the semiconductor wafer. The groove 101 is formed at a position corresponding to the scribing line part 91 as described herein. The groove 101 is formed, for example, by laser ablation or half-cutting (half-cutting). For example, the groove 101 is formed by laser ablation or half-cutting or a combination of laser ablation and half-cutting.
In step S102, the layers up to (or passing through) the wiring layer 72 are removed. For example, a layer including the wiring layer 72 may be removed, and a layer including the wiring layer 72 and a part of the support substrate 71 may be removed. By first removing the wiring layer 72 from the sensor surface (photodiode 74 side), a portion which becomes a starting point of cracking by dicing can be removed after the CSP (for example, step S104 described later). Therefore, the occurrence of cracking can be favorably suppressed, in addition to other problems.
When a low-k material (a material having a low dielectric constant) is used for the wiring layer 72, damage is easily caused when cutting with a blade, and removal needs to be performed by Laser Ablation (LA). When the LA process is performed after step S103 as a subsequent step, the resin constituting the adhesive layer 80 serving as the protective film may be modified due to the heat of the LA process. However, by performing the LA treatment before the resin is applied, the modification can be prevented.
In some illustrative embodiments, the width of the formed groove 101 is set to be greater than the width of the blade used for the cutting process. The depth of the formed groove 101 is set to a depth as follows: in the subsequent step, the depth does not expose the adhesive layer 80 filled in the groove 101 when the thickness of the support substrate 71 is reduced, and the depth of the formed groove 101 is set to the depth of the shallow portion of the support substrate 71 as described herein.
In step S103, the adhesive layer 80 is formed. In forming the adhesive layer 80, the groove 101 is filled with the same material (e.g., resin) as the material constituting the adhesive layer 80. The adhesive layer 80 is formed using a coating method or a lamination method or the like. In step S103, the semiconductor wafer is bonded to the cover glass 81. Preferably, in various embodiments, the bonding is performed using a vacuum bonder so that air bubbles do not penetrate into the bonding surface. Since the bonding is performed at a wafer level, a large lobe (flap) or the like does not occur, and the CSP processing described later is not affected by any large lobe or the like.
In step S104, the connection terminal 103-1 is formed, and CSP processing is performed. Although not fully illustrated, the through electrode 104 is formed by etching to open the wiring portion of the multilayer wiring formed on the surface of the semiconductor wafer, an insulating film such as a silicon oxide film is formed, the insulating film in the through hole is etched and opened, a through electrode is formed in the through hole by, for example, Cu plating, and a wiring is formed on the surface (rear surface) of the semiconductor wafer opposite to the light-transmitting substrate. A step of reducing the thickness of the support substrate 71 may be performed before this step.
In step S105, the semiconductor wafer is divided into chips by performing a dicing process at the scribe portion 91 (step S106).
In this way, by forming the groove 101 and forming the adhesive layer 80 (resin layer) in the groove 101, the moisture resistance can be improved.
By forming the groove 101, stacking the adhesive layer 80 on the groove 101, and performing the cutting process at the position as described above, the force applied to the interface between the films at the time of cutting can be reduced, and the possibility of occurrence of damage such as film peeling or cracking can be reduced.
Since the possibility of occurrence of film peeling or cracking or other problems can be reduced, the moisture resistance of the chip can be improved.
< second embodiment >
Fig. 7 shows another illustrative configuration of a chip according to the second embodiment. Fig. 7 illustrates a state of the wafer in which a plurality of chips (for example, three chips in fig. 7) exist as shown in fig. 4 before dicing.
The chip located at the center is referred to herein as chip 200-1, the chip located at the left side is referred to herein as chip 200-2, and the chip located at the right side is referred to herein as chip 200-3. In the following description, when it is not necessary to distinguish the chips 200-1 to 200-3 individually, these chips are simply referred to as chips 200.
Each chip 200 has the same configuration as the chip 100 described above with reference to fig. 4, but the two chips differ from each other in that: the microlens layer 79 does not have an adhesive layer 80 thereon. The chip 100 according to the first illustrative embodiment is a Chip Scale Package (CSP) having a cavity-less structure, but the chip 200 according to the second illustrative embodiment is a CSP having a cavity structure.
As shown in fig. 7, since the CSP has a cavity structure, a spacer layer 211 is disposed between the microlens layer 79 and the cover glass 81 of the chip 200.
The wafer shown in fig. 7 is provided with grooves 201 between the chips 200. Groove 201-1 is disposed between chip 200-1 and chip 200-2, and groove 201-2 is disposed between chip 200-1 and chip 200-3.
A scribing portion 91-1 is disposed between the chip 200-1 and the chip 200-2, and a groove 201-1 is disposed in the scribing portion 91-1. Likewise, a scribe portion 91-2 is disposed between the chips 200-1 and 200-3, and a groove 201-2 is disposed in the scribe portion 91-2.
In the chip 200 shown in fig. 7, the groove 201 is arranged to dig into the shallow part of the top of the microlens layer 79, the planarization film 78, the color filter layer 77, the planarization film 75, the silicon substrate 73, the wiring layer 72, and the support substrate 71.
An adhesive layer 80 formed of the same material as the adhesive layer 80 in the first embodiment is formed in the groove 201.
For the adhesive layer 80, since the chip 200 has a cavity structure, there is a spacer layer 211 instead of the adhesive layer 80, and the spacer layer 211 is formed by forming the adhesive layer 80, leaving a part of the adhesive layer 80, and forming the spacer layer 211 in the other part, the spacer layer 211 will be described later in the manufacturing process.
By forming the adhesive layer 80-1 in the groove 201-1, the adhesive layer 80-1 can be formed on the side surfaces of the spacer layer 211, the microlens layer 79, the planarization film 78, the color filter layer 77, the planarization film 75, the silicon substrate 73, the wiring layer 72, and a part of the support substrate 71.
By forming the adhesive layer 80-2 in the groove 201-2, the adhesive layer 80-2 can be formed on the side surfaces of the spacer layer 211, the microlens layer 79, the planarization film 78, the color filter layer 77, the planarization film 75, the silicon substrate 73, the wiring layer 72, and a part of the support substrate 71.
When the wafer provided with the grooves 201 between the chips 200 is cut at the scribe line portion 91, the chip 200-1 shown in fig. 8 is cut out. In the chip 200-1 shown in fig. 8, the spacer layer 211, microlens layer 79, planarizing film 78, color filter layer 77, planarizing film 75, silicon substrate 73, wiring layer 72, and part of the wall surface of the supporting substrate 71 are covered with the adhesive layer 80, and the surface is not exposed.
In this way, the divided chip 200-1 has the following structure: in this structure, part of the stacked layers of the chip 200-1 is covered with the adhesive layer 80-1 formed at the position of the groove 201-1' (the groove after dicing is denoted by adding a prime mark to the reference numeral to distinguish the groove after dicing from the groove 201-1 before dicing as shown in fig. 7).
The divided chip 200-1 has the following structure: in this structure, part of the stacked layers of the chip 200-1 is covered with the adhesive layer 80-2 formed at the position of the groove 201-2'.
In this way, both ends (or, for example, side surfaces) of the chip 200-1 are covered (or partially covered) with the adhesive layer 80. Accordingly, water may be prevented or reduced from penetrating into the chip 200-1 from the side surface of the chip 200-1.
Since the solder resist 202-1 is disposed on the bottom of the chip 200-1, the penetration of water into the chip 200-1 from the bottom can be prevented or reduced. An oxide film may be used instead of the solder resist 202-1, or an oxide film may be further stacked on the solder resist 202-1.
In this manner, in various embodiments, in order to obtain a structure in which the grooves 201-1 'and 201-2' (and/or the adhesive layers 80-1 and 80-2) remain in the chips 200-1 after division, it is preferable that the width of the groove 201-1 or the groove 201-2 between the chips 200 before division be set larger than the width of the blade for the cutting process.
In this way, by forming the groove 201 and forming the adhesive layer 80 in the groove 201, the moisture resistance can be improved.
< production of chip in second embodiment >
Next, an illustrative embodiment of manufacturing a chip (wafer) having the above-described groove will be described. Fig. 9 is an explanatory diagram showing a manufacturing process of a chip before division. As for the manufacturing process to be described with reference to fig. 9, a process of forming a groove, which is a feature of the presently disclosed technology, will be described below, and the manufacturing process of the other part (for example, a process of forming a layer) may be performed using a conventional manufacturing method, and thus the description of the conventional manufacturing method will be appropriately omitted.
Since the same steps as those of manufacturing the chip 100 according to the first embodiment are included, description of the same steps will be omitted as appropriate.
In step S201, a semiconductor wafer in which the photodiode 74 and other elements are formed is prepared. In step S202, grooves 201-1 and 201-2 are formed in the semiconductor wafer. In step S203, the adhesive layer 80 is formed.
In step S203, a final adhesive layer 80 is formed by forming the adhesive layer 80 on the microlens layer 79 and then removing unnecessary portions. Therefore, although the groove 201 is filled with the same material as that of the adhesive layer 80 at the same time as the adhesive layer 80 is formed, the adhesive layer 80 may be formed in another step.
A part of the formed adhesive layer 80 is removed in order to form a portion serving as the spacer layer 211. In this way, when the adhesive layer 80 is formed and then a portion of the adhesive layer 80 is removed, a photosensitive adhesive may be used as a material of the adhesive layer 80. The adhesive layer 80 formed in the portion serving as the spacer layer 211 is removed by patterning and etching.
The semiconductor wafer is bonded to the cover glass 81 using the adhesive layer 80 further formed in step S203. By bonding the cover glass 81 and the semiconductor wafer in this manner, the spacer layer 211 is formed.
The processing of steps S204 to S206 is the same as steps S104 to S106 of the manufacturing process of the chip 100 shown in fig. 6, and thus a description thereof will not be repeated.
In this way, by forming the groove 201 and forming the adhesive layer 80 in the groove 201, the moisture resistance can be improved.
In the second embodiment, as in the first embodiment, the layers up to (or passing through) the wiring layer 72 are removed in step S202. For example, a layer including the wiring layer 72 may be removed, and a layer including the wiring layer 72 and a part of the support substrate 71 may be removed. By first removing the wiring layer 72 from the sensor surface (photodiode 74 side), a portion that becomes a starting point of cracking by the dicing process (step S206) can be removed after the CSP process performed in step S204. Therefore, the occurrence of cracking can be suppressed.
When a low-k material (a material having a low dielectric constant) is used for the wiring layer 72, damage is easily caused at the time of blade cutting, and removal can be performed by Laser Ablation (LA). When the LA process is performed after step S203 as a subsequent step, the resin constituting the adhesive layer 80 serving as the protective film may be modified due to the heat of the LA process. However, by performing the LA treatment before the resin is applied, the resin modification due to heat can be prevented.
In this way, by forming the groove 201, laminating the adhesive layer 80 on the groove 201, and performing the cutting process at the aforementioned position, the force applied to the interface between the films at the time of cutting can be reduced, and the possibility of occurrence of problems such as film peeling or cracking can be reduced.
Since the possibility of occurrence of film peeling or cracking or other problems can be reduced, the moisture resistance of the chip can be improved.
< third embodiment >
Fig. 10 shows another illustrative configuration of a chip according to the third embodiment. Fig. 10 illustrates a state of a wafer (for example, as shown in fig. 4) in which a plurality of chips (for example, three chips in fig. 10) exist before dicing.
Herein, the chip located at the center is referred to as a chip 300-1, the chip located at the left side is referred to as a chip 300-2, and the chip located at the right side is referred to as a chip 300-3. In the following description, when it is not necessary to distinguish the chips 300-1 to 300-3 individually, these chips are simply referred to as chips 300.
Each chip 300 has the same configuration as the chip 100 described above with reference to fig. 4, and each chip 300 is a CSP having a cavity-free structure, and a groove is formed in the scribe portion 91 to further suppress occurrence of cracking at the time of dicing.
The wafer shown in fig. 10 is provided with grooves 301 between the chips 300. Recess 301-1 is disposed between chip 300-1 and chip 300-2, and recess 301-2 is disposed between chip 300-1 and chip 300-3.
A scribe line portion 91-1 is disposed between the chip 300-1 and the chip 300-2, and a groove 301-1 is disposed in the scribe line portion 91-1. Likewise, a scribe portion 91-2 is disposed between the chip 300-1 and the chip 300-3, and a groove 301-2 is disposed in the scribe portion 91-2.
A groove 311-1 is disposed in the scribe line 91-1 between the chip 300-1 and the chip 300-2. Likewise, a groove 311-2 is disposed in the scribe line 91-2 between the chip 300-1 and the chip 300-3.
In the chip 300 shown in fig. 10, like the groove 101 of the chip 100 shown in fig. 4, a groove 301 is arranged to dig into a part of the top of the microlens layer 79, the planarization film 78, the color filter layer 77, the planarization film 75, the silicon substrate 73, the wiring layer 72, and the support substrate 71.
A groove 311 is also arranged in the support substrate 71, and the groove 311 is formed to dig into the end of the adhesive layer 80 filled in the groove 301 from the bottom of the support substrate 71. The groove 301 and the groove 311 are connected in the scribe line portion 91.
As described later, the groove 301 is formed by, for example, cutting, and the groove 311 is formed by etching. The grooves 301 and 311 are formed using an appropriate processing method, respectively.
When the wafer having the grooves 301 and 311 arranged between the chips 300 is cut at the scribe line portion 91, the chip 300-1 shown in fig. 11 is cut out. In the chip 300-1 shown in fig. 11, the microlens layer 79, the planarization film 78, the color filter layer 77, the planarization film 75, the silicon substrate 73, the wiring layer 72, and a part of the support substrate 71 are surrounded by the adhesive layer 80, and their surfaces are not exposed.
That is, the side surfaces of the microlens layer 79, the planarization film 78, the color filter layer 77, the planarization film 75, the silicon substrate 73, the wiring layer 72, and the support substrate 71 are covered with the same material as the adhesive layer 80.
In this way, the divided chip 300-1 has the following structure: in this structure, a portion of the stacked layers of the chip 300-1 is covered at the positions of the grooves 301-1 'and the grooves 301-2' (the grooves after dicing are denoted by adding a prime to the reference numeral to distinguish the grooves after dicing from the grooves 301-1 and 301-2 before dicing as shown in fig. 10).
In this way, in order to obtain a structure in which the grooves 301-1 'and 301-2' are retained in the chips 300-1 after division and the same material as that of the adhesive layer 80 is retained in these portions, in various embodiments, it is preferable that the width of the groove 301-1 or the groove 301-2 between the chips 300 before division be set larger than the width of the blade used for the cutting process.
The chip 300 is provided with a groove 311, and the width of the groove 311 is set to be larger than the width of the blade. This configuration will be illustratively described below with reference to fig. 12.
As shown in a in fig. 12, when the scribing width is defined as Z, Si (support substrate 71) with the etching width defined as C, the wire-removing width defined as B, and the resin/glass cutting width defined as a, a relationship of the scribing width Z > the etching width C > the wire-removing width B > the cutting width a can be established.
When the relation is established, as shown in B in fig. 12, the thickness D of the adhesive layer 80 formed on the side surfaces of the divided chips 300 is set to (the delineation width B — the dicing width a)/2.
The etching width C, the removal line width B, and the cutting width a need to be made small because of the deviation of the positional accuracy and the width accuracy, and a step portion needs to be formed, and the structure shown in B in fig. 12 can be obtained by forming a step portion to set a width satisfying the condition.
For example, the scribe width Z is 100 μm, the etching width C is 80 to 95 μm, the scribe width B is 60 to 78 μm, and the dicing width a is 40 to 50 μm. By setting the width in this manner, the chip 300 having a resin (adhesive layer 80) protective structure of D ═ 5 μm or more can be provided.
The applicant has confirmed that improvement in the stability of the resin protective structure can be obtained by setting the thickness D of the adhesive layer 80 formed on the side surfaces of the divided chips 300 to 5 μm or more. From this confirmation, it can be seen that the chip 300 having a stable resin protective structure can be manufactured by setting the etching width C and the like to the above-described values as examples.
In this way, by performing the cutting process in a state where the grooves 301 and the grooves 311 are formed and the grooves 301 are filled with the same material as the adhesive layer 80, the force applied to the interface between the films at the time of cutting can be reduced, and the possibility of occurrence of film peeling or cracking or other problems can be reduced. Since film peeling or cracking or other problems do not occur or can be reduced, the moisture resistance of the chip can be improved.
Since the solder resist 302-1 is disposed on the bottom of the chip 300-1, the penetration of water into the chip 300-1 from the bottom can be prevented or reduced. An oxide film may be used instead of the solder resist 302-1, or an oxide film may be further stacked on the solder resist 302-1.
< production of chip in third embodiment >
Next, an illustrative method of manufacturing a chip (wafer) having the above-described groove will be described. Fig. 13 is an explanatory diagram showing a manufacturing process of a chip before division.
As for the manufacturing process to be described with reference to fig. 13, a process of forming a groove, which is a feature of the presently disclosed technology, will be described below, and the manufacturing process of the other part (for example, a process of forming a layer) may be performed using a conventional manufacturing method, and thus the description of the conventional manufacturing method will be appropriately omitted.
Since the same steps as those of manufacturing the chip 100 according to the first embodiment are included, description of the same steps will be omitted as appropriate.
The processing of steps S301 to S304 may be performed, for example, in the same manner as steps S101 to S104 in the manufacture of the chip 100 according to the first embodiment shown in fig. 6 and described elsewhere herein, and therefore the description of these steps will not be repeated. Through these steps, the groove 301 is formed, and the chip 300 in a state where the groove 301 is filled with the same material as the adhesive layer 80 is completed.
In step S305, a groove 311 is formed. The groove 311 is formed by etching the support substrate 71 with an etching width C of Si. Since the depth of the groove 311 is, for example, about 50 μm to 150 μm, the groove 311 may be formed by, for example, dry etching. In the groove 301 formed by removing the wiring in step S302, etching is performed up to the surface of the resin buried in step S303.
In step S306, the semiconductor wafer is divided into chips by performing a dicing process at the scribe portion 91 with the scribe line width Z (step S306).
In this way, by forming the groove 301 and forming the adhesive layer in the groove 301, the moisture resistance can be improved.
In the third embodiment, as in the first embodiment, the layers up to the wiring layer 72 are removed in step S302. By first removing the wiring layer 72 from the sensor surface (photodiode 74 side), a portion that becomes a crack start point by the dicing process (step S306) can be removed after the CSP process performed in step S304. Therefore, the occurrence of cracking can be suppressed.
In the third embodiment, since the cutting process is performed after the grooves 311 are formed in the support substrate 71, any occurrence of cracking can be prevented or reduced.
The adhesive having a cavity-free structure (material of the adhesive layer 80) may require light transmittance in addition to heat resistance and moisture resistance for bonding the pixel region. An adhesive satisfying such characteristics is very flexible, and thus the adhesive layer 80 can be flexibly bent by performing blade cutting. Therefore, cracks may occur in the wiring layer 72, which is a relatively hard layer.
However, in this illustrative embodiment, the wiring layer 72 located in the scribe line section 91 to be subjected to the cutting process is removed at the timing when, for example, the groove 301 is formed, and therefore, it is possible to prevent or reduce the occurrence of cracks in the wiring layer 72 at the time of cutting.
By forming the groove 311 in the portion of the scribe line portion 91 in the support substrate 71, as described in step S306, only the adhesive layer 80 (resin) is cut when the cutting process is performed. That is, even when the resin is flexible and bent, cracking does not occur or can be reduced.
When a low-k material (a material having a low dielectric constant) is used for the wiring layer 72 as in the first embodiment, damage is easily caused at the time of blade cutting, and removal by Laser Ablation (LA) may be required to be performed. When the LA process is performed after step S303 as a subsequent step, the resin constituting the adhesive layer 80 serving as the protective film may be modified due to the heat of the LA process. However, by performing the LA treatment before the resin is applied, the modification due to heat can be prevented.
In this way, by forming the groove 301, stacking the adhesive layer 80 on the groove 301, and performing the cutting process at the illustrative position, the force applied to the interface between the films at the time of cutting can be reduced, and the possibility of occurrence of film peeling or cracking or other problems can be reduced.
Since the possibility of occurrence of problems such as film peeling or cracking can be reduced, the moisture resistance of the chip can be improved.
< fourth embodiment >
Fig. 14 illustrates another configuration of a chip according to the fourth embodiment. Fig. 14 illustrates a state of the wafer in which a plurality of chips (for example, three chips as in fig. 14) exist as shown in fig. 4 before dicing.
Here, the chip located at the center is referred to as a chip 400-1, the chip located at the left side is referred to as a chip 400-2, and the chip located at the right side is referred to as a chip 400-3. In the following description, when it is not necessary to distinguish the chips 400-1 to 400-3 individually, these chips are simply referred to as chips 400.
The chip 400 is a CSP having a cavity structure, like the chip 200 according to the second embodiment, and the chip 400 is a chip having a groove in a portion of the scribe line portion 91 of the support substrate 71, like the chip 300 according to the third embodiment.
As shown in fig. 14, in the CSP having the cavity structure, a spacer layer 421 is disposed between the microlens layer 79 and the cover glass 81 of the chip 400.
The wafer shown in fig. 14 has grooves 401 disposed between the chips 400. Recess 401-1 is disposed between chip 400-1 and chip 400-2, and recess 401-2 is disposed between chip 400-1 and chip 400-3.
A scribing portion 91-1 is disposed between the chip 400-1 and the chip 400-2, and a groove 401-1 is disposed in the scribing portion 91-1. Likewise, a scribe portion 91-2 is disposed between the chip 400-1 and the chip 400-3, and a groove 401-2 is disposed in the scribe portion 91-2.
A groove 411-1 is arranged in the scribe line 91-1 between the chip 400-1 and the chip 400-2. Likewise, a notch 411-2 is disposed in scribe 91-2 between chip 400-1 and chip 400-3.
In the chip 400 shown in fig. 14, the grooves 401 are arranged to dig into shallow portions of the microlens layer 79, the planarization film 78, the color filter layer 77, the planarization film 75, the silicon substrate 73, the wiring layer 72, and the support substrate 71.
The groove 401 has disposed therein an adhesive layer 80 formed of the same material as the adhesive layer 80 of the first embodiment.
By forming the adhesive layer 80-1 in the groove 401-1, the adhesive layer 80-1 can be formed on the side surfaces of the spacer layer 421, the microlens layer 79, the planarization film 78, the color filter layer 77, the planarization film 75, the silicon substrate 73, the wiring layer 72, and a part of the support substrate 71.
By forming the adhesive layer 80-2 in the groove 401-2, the adhesive layer 80-2 can be formed on the side surfaces of the spacer layer 421, the microlens layer 79, the planarization film 78, the color filter layer 77, the planarization film 75, the silicon substrate 73, the wiring layer 72, and a part of the support substrate 71.
A groove 411 is also provided in the support substrate 71, and the groove 411 is formed to dig into the end of the adhesive layer 80 filled in the groove 401 from the bottom of the support substrate 71. Groove 401 and groove 411 connect in scribe 91.
When the wafer having the grooves 401 and 411 arranged between the chips 400 is cut at the scribe line portion 91, the chip 400-1 shown in fig. 15 is cut out. In the chip 400-1 shown in fig. 15, the end faces of the spacer layer 421, the microlens layer 79, the planarization film 78, the color filter layer 77, the planarization film 75, the silicon substrate 73, the wiring layer 72, and a part of the support substrate 71 are covered with the adhesive layer 80 so that their end faces are not exposed.
In this manner, the divided chip 400-1 has the following structure: in this structure, part of the stacked layers of the chip 400-1 is covered with the adhesive layer 80-1 formed at the position of the groove 401-1' (the groove after dicing is denoted by adding a prime mark to the reference numeral to distinguish the groove after dicing from the groove 401-1 before dicing as shown in fig. 14).
The divided chip 400-1 has the following structure: in this structure, a portion of the stacked layers of the chip 400-1 is covered with the adhesive layer 80-2 formed at the position of the groove 401-2'.
In this manner, both ends of the chip 400-1 are covered with the adhesive layer 80. Accordingly, water may be prevented or reduced from penetrating into the chip 400-1 from the side surface of the chip 400-1.
The chip 400 is provided with a recess 411, and the width of the recess 411 is set to be larger than the width of the blade. As with the groove 311 in the third embodiment, when the scribe line width is defined as Z (not shown), the etching width of Si (support substrate 71) is defined as C, the removal line width is defined as B, and the resin/glass cutting width is defined as a, the relationship of the scribe line width Z > etching width C > removal line width B > cutting width a can be established.
When this relational expression is satisfied, as described with reference to B in fig. 12, the thickness D of the adhesive layer 80 formed on the side surfaces of the divided chips 400 is set to (the cut width a/B) 2.
In this way, by performing the cutting process in a state where the grooves 401 and the grooves 411 are formed and the grooves 401 are filled with the same material as the adhesive layer 80, the force applied to the interface between the films at the time of cutting can be reduced, and the possibility of occurrence of problems such as film peeling or cracking can be reduced. Since film peeling or cracking or other problems do not occur or can be reduced, the moisture resistance of the chip can be improved.
Since the solder resist 402-1 is disposed on the bottom of the chip 400-1, the penetration of water into the chip 400-1 from the bottom can be prevented or reduced. An oxide film may be used instead of the solder resist 402-1, or an oxide film may be further stacked on the solder resist 402-1.
< production of chip in fourth embodiment >
Next, an illustrative method of manufacturing a chip (wafer) having the above-described groove will be described. Fig. 16 is an explanatory diagram showing a manufacturing process of a chip before division.
As for the manufacturing process to be illustratively described with reference to fig. 16, a process of forming a groove, which is a feature of the presently disclosed technology, will be described below, and the manufacturing process of other parts (e.g., a process of forming a layer) may be performed using a conventional manufacturing method, and thus the description of the conventional manufacturing method will be appropriately omitted.
Since the same steps as those of manufacturing the chip 200 according to the second embodiment are included, description of the same steps will be omitted as appropriate.
The processing of steps S401 to S404 may be performed, for example, in the same manner as steps S201 to S204 in the manufacture of the chip 200 according to the second embodiment shown in fig. 9, and therefore, the description of these steps will not be repeated. Through these steps, the groove 401 is formed, and the chip 400 in a state where the groove 401 is filled with the same material as the adhesive layer 80 is completed.
In step S405, the recess 411 is formed. The groove 411 is formed by etching the support substrate 71 with an etching width C of Si, as with the groove 311 of the chip 300 according to the third embodiment. Since the depth of the groove 411 is, for example, about 50 μm to 150 μm, the groove 411 is formed by, for example, dry etching. In the groove 401 formed by removing the wiring in step S402, etching is performed up to the surface of the resin buried in step S403.
In step S406, the semiconductor wafer is divided into chips by performing a dicing process at the scribe portion 91 (step S406).
In this way, by forming the groove 401 and forming the adhesive layer in the groove 401, the moisture resistance can be improved.
In the fourth embodiment, as in the first embodiment, the layers up to (and passing through) the wiring layer 72 are removed in step S402. For example, a layer including the wiring layer 72 may be removed, and a layer including the wiring layer 72 and a part of the support substrate 71 may be removed. By first removing the wiring layer 72 from the sensor surface (photodiode 74 side), a portion which becomes a starting point of cracking by the dicing process (step S406) can be removed after the CSP process performed in step S404. Therefore, the occurrence of cracking can be suppressed.
In the fourth embodiment, since the cutting process is performed after the grooves 411 are formed in the support substrate 71, any occurrence of cracking can be prevented or reduced.
When a low-k material (a material having a low dielectric constant) is used for the wiring layer 72 as in the first embodiment, damage is easily caused at the time of blade cutting, and removal can be performed by Laser Ablation (LA). When the LA process is performed after step S404 as a subsequent step, the resin constituting the adhesive layer 80 serving as the protective film may be modified due to the heat of the LA process. However, by performing the LA treatment before the resin is applied, the modification due to heat can be prevented.
In this way, by forming the groove 401, stacking the adhesive layer 80 on the groove 401, and performing the cutting process at the position, the force applied to the interface between the films at the time of cutting can be reduced, and the possibility of occurrence of film peeling or cracking or other problems can be reduced.
Since the possibility of occurrence of film peeling or cracking or other problems can be reduced, the moisture resistance of the chip can be improved.
As described above, according to the illustrative embodiments of the presently disclosed technology, in order to eliminate damage of the wiring layer, the wiring layer is removed by Laser Ablation (LA), half-cutting using a blade, or the like, and Si is removed by etching to obtain a structure in which no crack or other damage occurs (or is reduced) in the Si/wiring layer.
By setting the removal width of the wiring layer, the Si etching width, and the cutting width of the resin and glass to appropriate dimensions, the following resin protection structure can be realized: in this resin protection structure, a resin (adhesive) for glass bonding is appropriately left in a part of the wiring layer located on the side surface of the package (chip). Therefore, mechanical contact damage to the sensor unit or the influence of high temperature and high humidity on the sensor unit can be reduced, and thus a structure with higher reliability can be obtained.
By performing a process of removing the wiring layer before glass bonding, a portion which may become a starting point of the crack can be removed in advance. When a low-k layer is used for the wiring layer, damage is easily caused when cutting with a blade, and thus it may be necessary to remove the damage by Laser Ablation (LA). However, according to the embodiments of the presently disclosed technology, it is possible to prevent the resin used as the protective film from being modified due to the heat of LA, and thus it is possible to make the function of the resin protective film more stable.
< division Using optical laser >
In the first to fourth embodiments, although the division is performed using a cutting blade, the division may be performed in other ways without using a cutting blade.
Here, an illustrative example of performing division using an optical laser will be described. Since this example can be applied to any one of the chip 100, the chip 200, the chip 300, and the chip 400 according to the first to fourth embodiments, the chip 100 will be exemplified here.
Next, division using optical laser light will be illustratively described with reference to fig. 17. Fig. 17 illustrates a state of the chip 100 (shown in fig. 4, for example) before division. The dividing step corresponds to step S105 (e.g., fig. 6). When the chip 200 is processed, the dividing step corresponds to step S205 (e.g., fig. 9). The dividing step corresponds to step S306 (e.g., fig. 13) when the chip 300 is processed, and corresponds to step S406 (e.g., fig. 16) when the chip 400 is processed.
When the chip 100-1 and the chip 100-3 are cut at the scribing portion 91-2 to divide the wafer, the optical laser light 502 is focused by the focusing lens 501 and applied to the scribing portion 91-2.
The optical laser 502 is applied to the cover glass 81, the cover glass 81 is removed, and the adhesive layer 80 is also removed after the cover glass 81 is removed. Therefore, the division is performed by removing the cover glass 81 and the adhesive layer 80.
For example, an optical laser 502 using a 1060nm YAG laser beam and having 10ps and a peak power of 100 μ J is used, and the optical laser 502 is applied to the cover glass 81. The NA (numerical aperture) of the focusing lens 501 is set to, for example, about 0.8. The optical laser 502 is focused on the surface of the cover glass 81, causing a refractive index difference in the glass at the center of the beam, and the laser beam does not spread but travels straight in a thin state (thin state).
As shown in a in fig. 18, the cover glass 81 closer to the surface is ablated, and a hole is slowly formed and deepened. When the processing is performed, the layers of the cover glass 81 are completely removed, and the underlying resin (adhesive layer 80) is exposed (a in fig. 18). Subsequently, when the resin is also ablated by the optical laser 502, as illustratively shown by B in fig. 18, the material of the adhesive layer 80 may sublimate and attach to the side wall of the cover glass 81.
As shown by a in fig. 18, the side wall of the cover glass 81 is damaged by ablation and exposed as a damaged layer. When the side wall of the cover glass 81 is damaged, the cover glass 81 may be overlooked, causing dust generation due to mechanical contact damage or the like, for example, when mounting.
However, by sublimating the adhesive layer 80 using the optical laser 502 and attaching the adhesive layer 80 (resin) to the damaged layer (sidewall) of the cover glass 81, a coating film can be formed on the damaged layer. By applying the damaged layer, the possibility that the cover glass 81 is overlooked to cause dust can be reduced.
That is, in this case, when the adhesive layer 80 is processed by the optical laser 502, a part of the adhesive layer 80 is attached to the side wall of the cover glass 81, and a coating film is formed on the side wall of the cover glass 81. The coating film is a coating film having adhesiveness such that the coating film is not easily removed. By reducing the roughness by covering the damaged layer of the glass end face with a coating film, the external force can be dispersed to prevent or reduce the generation of dust.
Fig. 19 illustratively shows the chip 100 (chip 100-1) divided by the optical laser 502. A coating layer of debris (e.g., deposition material) 80' is formed on the sidewalls of the cover glass 81. In this case, as described above, the chips 80 'are the same material as the adhesive layer 80, and the chips 80' are formed by sublimating the adhesive layer 80 and attaching the adhesive layer 80 to the cover glass 81 at, for example, processing.
In this way, in order to facilitate attachment of the chips 80' to the side wall of the cover glass 81, there may be a difference between the irradiation condition of the optical laser 502 when processing the cover glass 81 and the irradiation condition of the optical laser 502 when processing the adhesive layer 80 (e.g., resin). In other words, the irradiation condition of the optical laser 502 at the time of processing the adhesive layer 80 (e.g., resin) may be set to a condition of actively generating the chips 80 'and attaching the chips 80' to the side wall of the cover glass 81.
In this way, the optical laser 502 may be used to start the processing from the surface of the cover glass 81. When this process is performed, the scribe line portions 91 of the chips 100, 200, 300, and 400 are filled with resin, and therefore, occurrence of cracks at the time of the process can be suppressed or prevented.
In the chips 300 and 400, since the groove 311 and the groove 411 are formed before the process using the optical laser 502 is performed, the occurrence of cracking at the time of the process can be further suppressed.
< segmentation Using stealth dicing >
In the first to fourth embodiments, although the division is performed using the cutting blade, the division may be performed in another manner without using the cutting blade.
Here, an illustrative example of performing segmentation using stealth dicing will be described. Stealth dicing is, for example, a technique such as: the dicing process is performed by focusing a laser beam of a transmission wavelength on the inside of a semiconductor wafer using an objective optical system and scanning the semiconductor wafer along a dicing line.
For example, in the third embodiment, although the groove 311 is formed in the chip 300 before dicing to prevent or reduce the occurrence of cracking, stealth dicing may be applied to the formation of the groove 311. For example, the dividing process of the chip 300 is explained above with reference to fig. 13, and the groove 311 is formed in step S305. In step S305, a groove 311 may be formed in the support substrate 71 using stealth dicing.
Also, for example, in the fourth embodiment, although the groove 411 is formed in the chip 400 before dicing to prevent or reduce the occurrence of cracking, stealth dicing may be applied to the formation of the groove 411. For example, the dividing process of the chip 400 is explained above with reference to fig. 16, and the recess 411 is formed in step S405. In step S405, a groove 411 may be formed in the support substrate 71 using stealth dicing.
An illustrative example of dividing the chip 300 or the chip 400 using the stealth dicing will be described later, and the stealth dicing will be briefly described first with reference to fig. 20. Referring to fig. 20, in step S601, when the following plate is divided using stealth dicing: in the board, a circuit board 602 is stacked on an Si substrate 601 and a logic circuit or a photodiode or the like is formed in the circuit board 602, a laser beam 603 of a transmission wavelength is focused on the inside of the Si substrate 601 using an objective lens 604.
By using the optimized laser beam 603 and the objective lens 604, it is possible to perform a local and selective laser process only on the inside of the Si substrate 601 without damaging the surface or the back surface of the Si substrate 601. In the Si substrate 601 subjected to the laser processing, as shown in step S602 of fig. 20, the modified layer 631 is formed in the Si substrate 601, and the vertical crack 632 is formed to the front surface and the back surface of the Si substrate 601 with the modified layer 631 as the starting point.
In step S601 of fig. 20, although the laser processing is performed from the circuit board 602 side, the laser processing may be performed from the Si substrate 601 side as shown in step S601' of fig. 20. That is, the modified layer 631 may be formed by performing laser beam irradiation from the circuit board 602 side (upper side in the figure), or the modified layer 631 may be formed by performing laser beam irradiation from the Si substrate 601 side (lower side in the figure). Regardless of from which side the laser beam irradiation is performed, the modified layer 631 may be formed in the Si substrate 601 as shown in step S602.
Although not illustrated in fig. 20, a DC tape may be attached to the bottom of the Si substrate 601, for example, and the DC tape may be separated by stretching the DC tape after performing the laser processing. That is, when the DC tape is stretched in the state shown in step S602 of fig. 20, the Si substrate is divided into two substrates, i.e., the Si substrate 601-1 and the Si substrate 601-2, as shown in step S603.
When the substrate is divided using stealth dicing, the modified layer 631-1 or the modified layer 631-2 remains on the processed end face after the division, and separated particles may be formed due to touch, impact, or other action applied to the modified layer 631. For example, when an image pickup device is formed in the circuit board 602, there is a possibility that image pickup failure occurs due to separated particles. Therefore, when the division is performed using the stealth dicing, it is advantageous to prevent or reduce formation of separated particles from the modified layer 631 to prevent or reduce occurrence of problematic effects.
Accordingly, as illustratively shown in fig. 21, the modified layer 631 may be removed by blade cutting. After the modified layer 631 and the crack 632 are formed inside the Si substrate 601 by steps S601 and S602 shown in fig. 20, half-cutting is performed up to a position deeper than the bottom surface of the modified layer 631 using blade cutting in step S611 (fig. 21). In step S611, the modified layer 631 is removed. In other words, blade cutting is performed up to the depth at which the modified layer 631 is removed.
By performing the process of step S603 (e.g., fig. 20) after removing the modification layer 631, division can be performed. When the modified layer 631 is removed, stress is applied to the crack 632 located below the modified layer 631, and the crack 632 is propagated. At this time, division of the Si substrate 601 is established. After the modified layer 631 is removed, the Si substrate may be divided by stretching.
By removing the modified layer 631 in this manner, formation of separated particles from the modified layer 631 can be prevented or reduced, and problematic effects can be prevented or reduced.
In step S611 of fig. 21, blade cutting is performed from the circuit substrate 602 side, but as shown in step S611' of fig. 21, blade cutting may also be performed from the Si substrate 601 side. That is, the modified layer 631 may be removed by performing blade dicing from the circuit board 602 side (upper side in the figure), or the modified layer 631 may be removed by performing blade dicing from the Si substrate 601 side (lower side in the figure). Regardless of from which side the blade cutting is performed, the division may be performed as shown in step S603.
When blade cutting is performed from the Si substrate 601 side, as shown in step S612 of fig. 21, before or after blade cutting is performed, grooves may be formed in portions that are cut to divide the circuit board 602 by laser ablation or half cutting or a combination of laser ablation and half cutting.
As shown in steps S612' and S612 ″ of fig. 21, a V-shaped groove may be further formed in the groove formed in the circuit board 602. The shape can be stabilized by forming a V-shaped groove in the bottom of the groove (Si substrate 601) of the circuit board 602. That is, the division may be performed so that the shape of the side surface of the Si substrate 601 becomes as flat as possible after the division instead of being roughened.
As shown in step S612', the V-shaped groove may be formed smaller than the groove formed in the circuit board 602 on the Si substrate 601 side. As shown in step S612 ″, a V-shaped groove may be formed on the Si substrate 601 side to have the same size as the groove formed in the circuit board 602.
The V-shaped groove formed in the Si substrate 601 may be formed at the time of forming the groove of the circuit board 602, or the V-shaped groove formed in the Si substrate 601 may be formed at a timing other than the time of forming the groove of the circuit board 602 (in a step other than the step of forming the groove of the circuit board 602).
For example, the V-shaped groove formed on the Si substrate 601 side may be formed by a laser ablation process, a liquid crystal anisotropic wet etching process, a dry etching process, or the like.
As described above, stealth dicing may be used to singulate chip 300 or chip 400, for example. When the chip 300 or the chip 400 is divided using stealth dicing, stealth dicing may be applied to the formation of the groove 311 or 411 in the support substrate 71. Therefore, this case will be explained below.
Next, an illustrative example of stealth dicing for dicing the chip 300 will be described with reference to fig. 22. In step S651, CSP processing is executed. Although not illustrated in the drawings, for example, the groove 301 may be formed and the groove 301 may be filled with resin by performing the same processing as steps S301 to S303 illustrated in fig. 13, and then performing the processing of step S651.
In step S652, the support substrate 71 is irradiated with the laser beam 603 to perform stealth dicing. As shown in step S653, the modified layer 631 and the crack 632 are formed by irradiation of the laser beam 603. In step S654, half-cutting is performed by blade cutting up to a position deeper than the bottom of the modification layer 631. In this way, the groove 311 is formed in the support substrate 71.
In step S655, the substrate is divided by performing dicing. Fig. 23 illustratively shows the chip 300 after singulation.
The chip 300 shown in fig. 23 has the same configuration as the chip 300 shown in fig. 11, but the two chips are different in that: a part of the crack formed in the stealth dicing remains in the support substrate 71. The side walls of the support substrate 71 of the chip 300 include side walls formed by blade dicing and side walls formed by stealth dicing. In various embodiments, the roughness of the sidewalls formed by the blade cut is different than the roughness of the sidewalls formed by the stealth cut. For example, the side wall formed by stealth dicing (e.g., the portion of the support substrate 71 cut by stealth dicing) is rougher than the side wall formed by blade dicing. Also, the sidewall formed by the blade cut is flatter and smoother than the sidewall formed by the stealth cut (e.g., the sidewall formed by the blade cut has a flatter, more uniform, or smoother edge in the depth direction, as compared to the sidewall formed by the stealth cut having an uneven surface or uneven edge in the depth direction). Further, the stealth dicing may form a crack growth in the area of the stealth dicing portion such that a crack is formed and grows or propagates within the support substrate as a result of the stealth dicing. In various embodiments, the crack growth portion and the region surrounding the crack growth portion may include a discolored portion generated due to heat of laser irradiation. The crack growth portion may extend in a depth direction of the support substrate. The crack growth portion and/or the discoloration portion may extend to the blade cutting portion within the support substrate or through the support substrate. Further, with fig. 23, since the side wall does not include the modification layer 631, particles separated from the modification layer 631 are not generated, and thus image pickup failure is not caused.
Although the division is performed in the above-described flow, these steps may be changed. For example, the stealth dicing process (steps S652 to S654) may be performed before step S651. The support substrate 71 may be divided by a stretching process appropriately including the stealth dicing in the above-described illustrative process. The segmentation may be performed by a stretching process of stealth dicing.
In this way, a groove can be formed in the support substrate 71 by stealth dicing. When this process is performed, the scribe portions 91 of the chips 300 and 400 are filled with resin, and therefore, it is possible to prevent or reduce the occurrence of cracks at the time of the process.
< electronic apparatus >
The presently disclosed technology is not limited to being applied to an image pickup apparatus, and may be applied to all electronic apparatuses that use an image pickup apparatus as an image input section (e.g., a photoelectric conversion section), for example, an image pickup apparatus such as a digital still camera or a video camera, a mobile terminal apparatus having an image pickup function such as a mobile phone, a copying machine that uses an image pickup apparatus as an image reading unit, and the like. Also, the type of module mounted on the electronic apparatus (i.e., camera module) may employ an image pickup apparatus.
Fig. 24 is a block diagram illustratively showing a configuration example of an image pickup apparatus as an example of an electronic apparatus according to an embodiment of the present invention. As shown in fig. 24, an image capturing apparatus 1000 according to an embodiment of the present invention includes: an optical unit 1001 including a lens group and the like; a solid-state imaging device 1002; a DSP circuit 1003 that is a camera signal processing unit; a frame memory 1004; a display unit 1005; a recording unit 1006; an operation unit 1007; and a power supply unit 1008.
The DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, the operation unit 1007, and the power supply unit 1008 are connected to each other via a bus 1009.
The lens group 1001 receives incident light (e.g., image light) from an object and focuses the incident light on an image pickup surface of the solid-state image pickup device 1002. The solid-state imaging device 1002 converts the light intensity of incident light focused on the imaging surface by the lens group 1001 into an electric signal of a pixel and outputs a pixel signal. The image pickup device according to the above-described embodiment can be used as the solid-state image pickup device 1002.
The display unit 1005 includes a panel-type display device such as a liquid crystal display device or an organic Electroluminescence (EL) display device, and the display unit 1005 displays a moving image or a still image captured by the solid-state imaging device 1002. The recording unit 1006 records a moving image or a still image captured by the solid-state imaging device 1002 on a recording medium such as a Digital Versatile Disc (DVD).
The operation unit 1007 issues operation commands for various functions of the image pickup apparatus under operation of a user. The power supply unit 1008 appropriately supplies various powers to the supply target as the operation powers of the DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, and the operation unit 1007.
The image pickup apparatus 1000 is applied to a camera module of a video camera, a digital still camera, or a mobile apparatus such as a mobile phone. In the image pickup apparatus 1000, the solid-state image pickup device according to the above-described embodiment can be used as the solid-state image pickup device 1002.
The technology according to the embodiment of the present invention can be applied to various electronic devices including products. For example, the technique according to the embodiment of the present invention can be applied to an internal information acquisition system for a patient using an endoscope capsule.
Fig. 25 is an explanatory diagram showing an example of a schematic configuration of an internal information acquisition system 2500 to which the technique according to the embodiment of the present invention can be applied. Referring to fig. 25, the internal information acquisition system 2500 includes an endoscope capsule 2501 and an external control device 2523, and the external control device 2523 centrally controls the operation of the internal information acquisition system 2500. During examination, the patient swallows the endoscope capsule 2501. The endoscope capsule 2501 has an image capturing function and a wireless communication function. The endoscope capsule 2501 moves inside organs such as the stomach and the intestine by, for example, peristaltic movement or the like until the endoscope capsule 2501 is naturally discharged by the patient, while the endoscope capsule 2501 also continuously captures images of the inside of the relevant organ (hereinafter, also referred to as internal images) at predetermined intervals and continuously wirelessly transmits information on the internal images to the external control device 2523 outside the body. Based on the received information on the internal image, the external control device 2523 generates image data for displaying the internal image on a display device (not shown). In this way, with the internal information acquisition system 2500, images that can depict the internal condition of the patient can be obtained continuously from the time when the endoscope capsule 2501 is swallowed to the time when the endoscope capsule 2501 is expelled.
The construction and function of endoscope capsule 2501 and external control device 2523 will be described in further detail. As shown in fig. 25, the endoscope capsule 2501 has functions of a light source unit 2505, an image capturing unit 2507, an image processing unit 2509, a wireless communication unit 2511, a power supply unit 2515, a power supply unit 2517, a state detection unit 2519, and a control unit 2521, and the light source unit 2505, the image capturing unit 2507, the image processing unit 2509, the wireless communication unit 2511, the power supply unit 2515, the power supply unit 2517, the state detection unit 2519, and the control unit 2521 are all built in the capsule-type housing 2503.
The light source unit 2505 includes, for example, a light source such as a light-emitting diode (LED), and irradiates an imaging field of the image capturing unit 2507 with light.
The image capturing unit 2507 includes an image sensor such as the one disclosed herein, and an optical system composed of a plurality of lenses disposed in front of the image sensor. Reflected light from light for irradiating body tissue as an observation target (hereinafter, referred to as observation light) is condensed by an optical system and is incident on an image sensor. The image sensor receives observation light and photoelectrically converts the observation light, thereby generating an electrical signal corresponding to the observation light, or in other words, an image signal corresponding to an observation image. An image signal generated by the image capturing unit 2507 is supplied to the image processing unit 2509. The advantages of the image sensor disclosed herein are also advantageous when used with such an internal information acquisition system 2500. For example, the reduced thickness image sensor disclosed herein may advantageously reduce the size of the endoscope capsule 2501.
The image processing unit 2509 includes a processor such as a Central Processing Unit (CPU) or a Graphics Processing Unit (GPU), and the image processing unit 2509 performs various types of signal processing on the image signal generated by the image capturing unit 2507. The signal processing may be a minimum degree of processing (e.g., image data compression, frame rate conversion, data rate conversion, and/or format conversion) for transmitting the image signal to the external control device 2523. For example, configuring the image processing unit 2509 to perform only a minimum necessary degree of processing makes it possible to realize the image processing unit 2509 in a lower power consumption and more compact form, which is advantageous for the endoscope capsule 2501. However, if there is additional space or available power inside the housing 2503, the image processing unit 2509 may also perform additional signal processing (such as noise cancellation processing or other image quality improvement processing). The image processing unit 2509 supplies the image signal subjected to the signal processing as raw data to the wireless communication unit 2511. It is to be noted that, if the state detection unit 2519 acquires information on the state (such as movement or orientation) of the endoscope capsule 2501, the image processing unit 2509 may also supply an image signal to the wireless communication unit 2511 in association with the information. This makes it possible to associate the position within the body of the captured image, the direction in which the image is captured, and other information with the captured image.
The wireless communication unit 2511 includes a communication device capable of transmitting various types of information to the external control device 2523 and capable of receiving various types of information from the external control device 2523. The communication device includes, for example, an antenna 2513 and a processing circuit that performs processing such as modulation processing for transmitting and receiving signals. The wireless communication unit 2511 performs predetermined processing such as modulation processing on the image signal subjected to the signal processing by the image processing unit 2509, and the wireless communication unit 2511 transmits the image signal to the external control device 2523 via the antenna 2513. Further, the wireless communication unit 2511 receives a control signal related to drive control of the endoscope capsule 2501 from the external control device 2523 via the antenna 2513. The wireless communication unit 2511 supplies the received control signal to the control unit 2521.
The power supply unit 2515 includes, for example, an antenna coil for receiving electric power, a power regeneration circuit for regenerating electric power from a current generated in the antenna coil, and a booster circuit. In the power supply unit 2515, electric power is generated using the principle of so-called contactless or wireless charging. For example, an external magnetic field (electromagnetic wave) of a predetermined frequency supplied to the antenna coil of the power supply unit 2515 generates an induced electromotive force in the antenna coil. For example, the electromagnetic wave may be a carrier wave transmitted from external control apparatus 2523 via antenna 2525. The power regeneration circuit regenerates electric power from the induced electromotive force, and the potential of the electric power is appropriately adjusted in the voltage boost circuit, thereby generating electric power for storage. The power generated by the power supply unit 2515 is stored in the power supply unit 2517.
The power supply unit 2517 includes a secondary battery, and stores electric power generated by the power supply unit 2515. Although an arrow or the like indicating a recipient receiving power from the power supply unit 2517 is omitted in fig. 25 for simplicity, power stored in the power supply unit 2517 is supplied to the light source unit 2505, the image capturing unit 2507, the image processing unit 2509, the wireless communication unit 2511, the state detection unit 2519, and the control unit 2521, and the power stored in the power supply unit 2517 may be used to drive these components.
The state detection unit 2519 includes a sensor for detecting the state of the endoscope capsule 2501, such as an acceleration sensor and/or a gyro sensor. The state detection unit 2519 can acquire information on the state of the endoscope capsule 2501 from the detection result of the sensor. The state detection unit 2519 supplies the acquired information about the state of the endoscope capsule 2501 to the image processing unit 2509. As previously discussed, in the image processing unit 2509, information about the state of the endoscope capsule 2501 may be associated with the image signal.
The control unit 2521 includes a processor such as a Central Processing Unit (CPU), and centrally controls the operation of the endoscope capsule 2501 by operating according to a predetermined program. The control unit 2521 appropriately controls driving of the light source unit 2505, the image capturing unit 2507, the image processing unit 2509, the wireless communication unit 2511, the power supply unit 2515, the power supply unit 2517, and the state detection unit 2519 according to a control signal transmitted from the external control device 2523, thereby realizing the functions of the respective components as described above.
The external control device 2523 may be a processor such as a CPU or GPU, or may be a device such as a microcontroller or a control board on which the processor and a storage element such as a memory are mounted. The external control device 2523 includes an antenna 2525, and the external control device 2523 is capable of transmitting various types of information to the endoscope capsule 2501 via the antenna 2525 and capable of receiving various types of information from the endoscope capsule 2501 via the antenna 2525. For example, the external control device 2523 controls the operation of the endoscope capsule 2501 by sending control signals to the control unit 2521 of the endoscope capsule 2501. For example, the lighting condition in which the light source unit 2505 irradiates the observation target with light may be changed by a control signal from the external control device 2523. Further, image capturing conditions (such as the frame rate and exposure level of the image capturing unit 2507) may be changed by a control signal from the external control device 2523. Further, the processing contents in the image processing unit 2509 and the conditions (such as the transmission interval and the number of images to be transmitted) under which the wireless communication unit 2511 transmits image signals can be changed by control signals from the external control device 2523.
Further, the external control device 2523 performs various types of image processing on the image signal transmitted from the endoscope capsule 2501, and the external control device 2523 generates image data for displaying the captured internal image on the display device. For the image processing, various known signal processes such as a development process (demosaicing process), an image quality improvement process (such as a band enhancement process, a super-resolution process, a Noise Reduction (NR) process, and/or a shake correction process, etc.), and/or an enlargement process (electronic zoom process), etc. may be performed. The external control device 2523 controls driving of a display device (not shown), and causes the display device to display a captured internal image based on the generated image data. Alternatively, the external control device 2523 may also cause a recording device (not shown) to record the generated image data, or cause a printing device (not shown) to print out the generated image data.
The above describes an example of the internal information acquisition system 2500 to which the technology according to the embodiment of the present invention can be applied.
In this specification, a system refers to an entire apparatus including a plurality of devices.
The advantageous effects described in the present specification are merely exemplary, not restrictive, and other advantageous effects may be achieved.
Embodiments of the presently disclosed technology are not limited to the above-described embodiments, and may be modified in various forms without departing from the spirit of the presently disclosed technology.
The present technology may have the following configuration.
(1) A semiconductor device, comprising: a first substrate; and a second substrate adjacent to the first substrate, wherein a sidewall of the second substrate includes a blade cut and a stealth cut.
(2) The semiconductor device according to (1), wherein the first substrate is arranged between a transparent layer and the second substrate.
(3) The semiconductor device according to any one of (1) to (2), further comprising an adhesive layer between the first substrate and the transparent layer.
(4) The semiconductor device according to any one of (1) to (3), further comprising a groove extending from the adhesive layer to the second substrate.
(5) The semiconductor device according to any one of (1) to (4), wherein the transparent layer is a cover glass layer, and the adhesive layer is a resin.
(6) The semiconductor device according to any one of (1) to (5), wherein the invisible cutting portion and the blade cutting portion extend to the groove.
(7) The semiconductor device according to any one of (1) to (6), wherein the invisible cutting portion is farther from the groove than the blade cutting portion.
(8) An image pickup apparatus, comprising: a first substrate; a transparent layer; an adhesive layer between the first substrate and the transparent layer; a second substrate, wherein the first substrate is disposed between the adhesive layer and the second substrate; and a groove extending from the adhesive layer to the second substrate, wherein the groove is filled with the adhesive layer.
(9) The image pickup apparatus according to (8), wherein the adhesive layer is a resin.
(10) The imaging apparatus according to any one of (8) to (9), wherein the transparent layer is a cover glass layer.
(11) The image pickup device according to any one of (8) to (10), further comprising a microlens layer and a wiring layer, wherein the groove extends through the microlens layer and through the wiring layer so that the adhesive layer is in contact with the microlens layer, the wiring layer, and the first substrate.
(12) The image pickup apparatus according to any one of (8) to (11), wherein the side wall of the second substrate includes a blade cutting portion, and a width of the groove is larger than a width of a blade in contact with the blade cutting portion.
(13) The image pickup apparatus according to any one of (8) to (12), further comprising a solder resist disposed on a bottom portion of the second substrate.
(14) An image pickup apparatus, comprising: a transparent layer; a first substrate including a photoelectric conversion portion; a second substrate, wherein the first substrate is disposed between the transparent layer and the second substrate; and a microlens layer including microlenses for focusing incident light to the photoelectric conversion portions, wherein the second substrate includes first and second cut portions.
(15) The image pickup apparatus according to (14), further comprising an adhesive layer between the first substrate and the transparent layer.
(16) The image pickup apparatus according to any one of (14) to (15), further comprising a groove extending from the adhesive layer to the second substrate, wherein the groove is filled with the adhesive layer.
(17) The imaging device according to any one of (14) to (16), further comprising a wiring layer, wherein the groove extends through the microlens layer and through the wiring layer.
(18) The image pickup device according to any one of (14) to (17), wherein the groove extends such that the adhesive layer is in contact with the microlens layer, the wiring layer, and the first substrate.
(19) The imaging apparatus according to any one of (14) to (18), wherein the adhesive layer is a resin.
(20) The image pickup apparatus according to any one of (14) to (19), wherein a width of the groove is larger than a width of a blade that contacts the first cutting portion and the second cutting portion.

Claims (14)

1. A semiconductor device comprising one or more chips, each of the chips comprising:
a first substrate;
a transparent layer;
an adhesive layer between the first substrate and the transparent layer; and
a second substrate, wherein the first substrate is disposed between the adhesive layer and the second substrate,
wherein the adhesive layer extends to the second substrate on a side surface of the chip.
2. The semiconductor device according to claim 1, wherein the transparent layer is a cover glass layer, and the adhesive layer is a resin.
3. The semiconductor device according to claim 1 or 2, wherein the side wall of the second substrate includes a blade cut portion and a stealth cut portion.
4. The semiconductor device according to claim 3, wherein the invisible cut and the blade cut extend to a portion where the adhesive layer extends toward the second substrate.
5. The semiconductor device of claim 4, wherein the invisible cut is further from the portion of the adhesive layer extending toward the second substrate than the blade cut.
6. The semiconductor device according to claim 1, further comprising a microlens layer and a wiring layer, wherein the adhesive layer extends through the microlens layer and through the wiring layer such that the adhesive layer is in contact with the microlens layer, the wiring layer, and the first substrate.
7. The semiconductor device according to claim 1, wherein the side wall of the second substrate includes a blade cut portion, and a width of a portion of the adhesive layer extending toward the second substrate is larger than a width of a blade in contact with the blade cut portion.
8. The semiconductor device according to claim 6 or 7, further comprising a solder resist disposed on a bottom portion of the second substrate.
9. An image capture device comprising one or more chips, each of the chips comprising:
a transparent layer;
a first substrate including a photoelectric conversion portion;
an adhesive layer between the first substrate and the transparent layer;
a second substrate, wherein the first substrate is disposed between the adhesive layer and the second substrate; and
a microlens layer including microlenses for focusing incident light to the photoelectric conversion portions,
wherein the adhesive layer extends to the second substrate on a side surface of the chip.
10. The image pickup apparatus according to claim 9, wherein the second substrate includes a first cut portion and a second cut portion.
11. The image pickup device according to claim 9, further comprising a wiring layer, wherein the adhesive layer extends through the microlens layer and through the wiring layer.
12. The image pickup device according to claim 11, wherein the adhesive layer extends so that the adhesive layer is in contact with the microlens layer, the wiring layer, and the first substrate.
13. The image pickup apparatus according to any one of claims 9 to 12, wherein the adhesive layer is a resin.
14. The image pickup apparatus according to claim 10, wherein a width of a portion of the adhesive layer extending toward the second substrate is larger than a width of a blade in contact with the first cutting portion and the second cutting portion.
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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6727948B2 (en) * 2015-07-24 2020-07-22 ソニーセミコンダクタソリューションズ株式会社 Imaging device and manufacturing method
JP6817822B2 (en) * 2017-01-18 2021-01-20 株式会社ディスコ Processing method
JP2018206795A (en) * 2017-05-30 2018-12-27 株式会社ディスコ Wafer processing method
US11538843B2 (en) * 2018-04-09 2022-12-27 Sony Semiconductor Solutions Corporation Imaging unit, method for manufacturing the same, and electronic apparatus
US20210273000A1 (en) * 2018-06-29 2021-09-02 Sony Semiconductor Solutions Corporation Solid-state imaging device, electronic apparatus, and method for producing solid-state imaging device
JP7164411B2 (en) * 2018-11-15 2022-11-01 株式会社ディスコ Laminate processing method
JP7164412B2 (en) * 2018-11-16 2022-11-01 株式会社ディスコ Laminate processing method
CN113169192A (en) * 2018-12-19 2021-07-23 奥林巴斯株式会社 Imaging device and method for manufacturing imaging device
JP7396346B2 (en) 2019-02-26 2023-12-12 Ａｇｃ株式会社 Optical filter, optical filter transport support, optical filter manufacturing method
TW202142344A (en) * 2020-05-04 2021-11-16 力成科技股份有限公司 Laser cutting method for a wafer
JP7135029B2 (en) * 2020-06-30 2022-09-12 キヤノン株式会社 Display devices, modules and equipment
JP2022034898A (en) 2020-08-19 2022-03-04 キオクシア株式会社 Method for manufacturing semiconductor device and semiconductor device
CN114512412B (en) * 2022-04-20 2022-07-12 苏州科阳半导体有限公司 Surface acoustic wave filter wafer packaging method and chip

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101582416A (en) * 2008-05-14 2009-11-18 夏普株式会社 Electronic element wafer module and method for manufacturing the same
CN102138215A (en) * 2009-01-30 2011-07-27 松下电器产业株式会社 Optical device and method for manufacturing same
CN102569194A (en) * 2010-12-22 2012-07-11 台湾积体电路制造股份有限公司 Protecting T-contacts of chip scale packages from moisture
CN103077951A (en) * 2013-01-09 2013-05-01 苏州晶方半导体科技股份有限公司 Wafer-level packaging method of BSI (Backside Illumination) image sensor
CN103258831A (en) * 2012-02-21 2013-08-21 索尼公司 Solid-state imaging device and manufacturing method thereof, and camera system

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01125565A (en) 1987-11-11 1989-05-18 Toyota Motor Corp Ignition timing controller of multicylinder internal combustion engine for vehicle
JPH01125565U (en) * 1988-02-22 1989-08-28
EP1635390B1 (en) * 2002-03-12 2011-07-27 Hamamatsu Photonics K. K. Substrate dividing method
TWI326626B (en) * 2002-03-12 2010-07-01 Hamamatsu Photonics Kk Laser processing method
US7452743B2 (en) * 2005-09-01 2008-11-18 Aptina Imaging Corporation Microelectronic imaging units and methods of manufacturing microelectronic imaging units at the wafer level
JP2009016405A (en) * 2007-06-30 2009-01-22 Zycube:Kk Solid-state imaging apparatus
JP5159192B2 (en) * 2007-07-06 2013-03-06 株式会社東芝 Manufacturing method of semiconductor device
US7923298B2 (en) * 2007-09-07 2011-04-12 Micron Technology, Inc. Imager die package and methods of packaging an imager die on a temporary carrier
JP4799543B2 (en) * 2007-12-27 2011-10-26 株式会社東芝 Semiconductor package and camera module
JP5344336B2 (en) * 2008-02-27 2013-11-20 株式会社ザイキューブ Semiconductor device
JP5318634B2 (en) * 2009-03-30 2013-10-16 ラピスセミコンダクタ株式会社 Chip size packaged semiconductor chip and manufacturing method
JP5673063B2 (en) 2010-12-15 2015-02-18 ソニー株式会社 Solid-state imaging device, driving method, and electronic apparatus
KR101712630B1 (en) * 2010-12-20 2017-03-07 삼성전자 주식회사 Method of forming semiconductor device
JP2013021533A (en) 2011-07-12 2013-01-31 Sony Corp Solid-state image pickup device, driving method of solid-state image pickup device, and electronic apparatus
JP5842735B2 (en) 2012-05-29 2016-01-13 日本精機株式会社 Light source driving device and head-up display device
JPWO2013179766A1 (en) * 2012-05-30 2016-01-18 オリンパス株式会社 Imaging device, semiconductor device, and imaging unit
JP2014045142A (en) * 2012-08-28 2014-03-13 Sony Corp Semiconductor device and semiconductor device manufacturing method
JP6727948B2 (en) * 2015-07-24 2020-07-22 ソニーセミコンダクタソリューションズ株式会社 Imaging device and manufacturing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101582416A (en) * 2008-05-14 2009-11-18 夏普株式会社 Electronic element wafer module and method for manufacturing the same
CN102138215A (en) * 2009-01-30 2011-07-27 松下电器产业株式会社 Optical device and method for manufacturing same
CN102569194A (en) * 2010-12-22 2012-07-11 台湾积体电路制造股份有限公司 Protecting T-contacts of chip scale packages from moisture
CN103258831A (en) * 2012-02-21 2013-08-21 索尼公司 Solid-state imaging device and manufacturing method thereof, and camera system
CN103077951A (en) * 2013-01-09 2013-05-01 苏州晶方半导体科技股份有限公司 Wafer-level packaging method of BSI (Backside Illumination) image sensor

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