JP2013021533A - Solid-state image pickup device, driving method of solid-state image pickup device, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide images of a wide dynamic range and little noise using global exposure.SOLUTION: In a pixel array part, a plurality of unit pixels having a first charge storage part comprising a photoelectric conversion part for generating and storing optical charges corresponding to a received light quantity and a buried MOS capacitor and a second charge storage part are arranged, and batch exposure of the plurality of unit pixels is possible. A vertical drive part and a system control part perform first drive of storing the optical charges generated by the photoelectric conversion part during an exposure period in the photoelectric conversion part, the first charge storage part and the second storage part, or second drive of storing the optical charges generated by the photoelectric conversion part during the exposure period in the photoelectric conversion part and the first charge storage part. This technique is applicable to a solid-state imaging device, for instance.

Description

  The present technology relates to a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic device, and more particularly, to a solid-state imaging device that performs global exposure, a driving method of the solid-state imaging device, and an electronic device.

  In a solid-state imaging device, for example, a CMOS image sensor which is a kind of XY address type solid-state imaging device, an operation of sequentially scanning and reading out photoelectric charges generated and accumulated in a photoelectric conversion unit for each pixel or row is performed. Is called. In the case of this sequential scanning, that is, when a rolling shutter is used as the electronic shutter, the start time and end time of exposure for accumulating photocharges cannot be made consistent for all pixels. Therefore, in the case of sequential scanning, there is a problem that a captured image is distorted when a moving subject is imaged.

  In sensing applications that require high-speed moving subjects that cannot tolerate this type of image distortion or the simultaneousness of captured images, exposure starts for all pixels in the pixel array unit at the same timing as an electronic shutter. And a global shutter that executes the exposure end. In order to realize this global shutter, for example, an embedded MOS capacitor is provided as a region for accumulating photoelectric charges, that is, a charge accumulating unit, separately from the photodiode that is a photoelectric conversion unit (see, for example, Patent Document 1). .

  However, in order to receive all the photoelectric charges generated and accumulated by photoelectric conversion in the photodiode with the embedded MOS capacitor at the time of the global shutter, the embedded MOS capacitor requires a saturation charge amount equal to or higher than that of the photodiode. To do. Conversely, considering the same unit pixel size, the area of the photodiode is significantly reduced by the presence of the embedded MOS capacitor in the unit pixel, so that the saturation charge amount of the photodiode is reduced. is there.

  As a countermeasure, a technique has been proposed in which photocharges generated by photoelectric conversion in a photodiode are stored in both the photodiode and the embedded MOS capacitor (see, for example, Patent Document 2). According to this prior art, the saturation charge amount is the sum of the saturation charge amount of the photodiode and the saturation charge amount of the embedded MOS capacitor.

Japanese Patent No. 3874135 JP 2009-268083 A

  However, even in the prior art described in Patent Document 2, the saturation charge amount is greatly inferior to that of a CMOS image sensor without a global shutter function. This is because, in order to realize global exposure, it is necessary to add not only a charge storage unit (in the case of the prior art, an embedded MOS capacitor) but also a transistor in a unit pixel. As a result, the dynamic range of the image is reduced.

  In addition to the above-described conventional technology that realizes the global exposure, it can be easily imagined that a capacitor having a larger capacitance value per unit area is used as the charge storage unit instead of the embedded MOS capacitor. However, a capacitor having a large capacitance value per unit area generally has a large leakage current, and there is a problem that deterioration of dark characteristics such as dark current and white point becomes remarkable.

  Therefore, the present technology enables to obtain an image having a wide dynamic range and less noise by using global exposure.

  The solid-state imaging device according to the first aspect of the present technology includes a photoelectric conversion unit that generates and accumulates a photocharge according to a received light amount, a first charge accumulation unit including an embedded MOS capacitor, and a second charge. A plurality of unit pixels having an accumulation unit are arranged, a pixel array unit capable of performing batch exposure of the plurality of unit pixels, and a photoelectric charge generated by the photoelectric conversion unit during an exposure period, the photoelectric conversion unit, First charge accumulated in the second charge accumulation unit and the second accumulation unit, or the photoelectric charge generated by the photoelectric conversion unit during the exposure period is accumulated in the photoelectric conversion unit and the first charge accumulation unit. And a driving unit that performs the second driving.

  The driving unit performs driving for outputting the photoelectric charges accumulated in the photoelectric conversion unit and the first charge accumulating unit as an electrical signal a predetermined number of times during the exposure period as the second driving. be able to.

  An integration unit that integrates the value of the electrical signal output during the exposure period for each pixel and a holding unit that holds the integration value for each pixel can be further provided.

  The driving unit can switch between the first driving and the second driving according to the length of the exposure period.

  In the drive unit, as the first drive, during the exposure period, a photoelectric charge equal to or less than a saturation charge amount of the photoelectric conversion unit is accumulated in the photoelectric conversion unit, and exceeds a saturation charge amount of the photoelectric conversion unit. A drive for accumulating photoelectric charges in the first charge accumulation unit and the second charge accumulation unit is performed, and as the second drive, light having a saturation charge amount equal to or less than the saturation charge amount of the photoelectric conversion unit during the exposure period. It is possible to perform driving for accumulating charges in the photoelectric conversion unit and accumulating photocharges exceeding the saturation charge amount of the photoelectric conversion unit in the first charge accumulation unit.

  The unit pixel is formed under the first transfer gate, the first transfer gate unit transferring the photoelectric charge accumulated in the photoelectric conversion unit to the first charge accumulation unit, and the photoelectric conversion And a first overflow path for transferring the photocharge overflowing from the first portion to the first charge storage portion.

  The unit pixel is formed below the second transfer gate, a second transfer gate unit that transfers the photocharge accumulated in the first charge accumulation unit to the second charge accumulation unit, A second overflow path for transferring photocharges overflowing from the first charge accumulation unit to the second charge accumulation unit may be further provided.

  When the photocharge is transferred from the photoelectric conversion unit to all pixels at the same time, the drive unit accumulates a photocharge less than or equal to the saturation charge amount of the first charge accumulation unit in the first charge accumulation unit, It is possible to drive to accumulate photocharges exceeding the saturation charge amount of the first charge accumulation unit in the second charge accumulation unit.

  The unit pixel may be provided with a charge discharge gate portion that selectively discharges charges in the photoelectric conversion portion during a period in which photoelectric charge is not accumulated in the photoelectric conversion portion.

  The unit pixel is provided with a floating diffusion portion that outputs electric charge as an electric signal, and the second charge accumulation portion is constituted by a capacitor having a larger capacitance value per unit area than the first charge accumulation portion. Can do.

  The unit pixel includes a first transfer gate unit that transfers the photocharge accumulated in the photoelectric conversion unit to the first charge accumulation unit, and the photocharge accumulated in the first charge accumulation unit. A second transfer gate portion for transferring to the floating diffusion portion can be further provided.

  The unit pixel may further include a third transfer gate unit that transfers the photocharge accumulated in the first charge accumulation unit to the second charge accumulation unit.

  The unit pixel includes a reset gate unit that resets the photocharge of the floating diffusion unit, an amplification transistor that converts the photocharge of the floating diffusion unit into an electric signal, and a selection that is connected to the amplification transistor and performs pixel selection A transistor can be further provided.

  The unit pixel further includes a reset gate portion that resets the floating diffusion portion, and an amplification transistor that converts the photoelectric charge of the floating diffusion portion into an electric signal, and applies a driving voltage to the reset gate portion. Thus, pixel selection can be performed.

  The first charge storage unit has a saturation charge amount smaller than the saturation charge amount of the photoelectric conversion unit, and the second charge storage unit has a saturation charge amount of the first charge storage unit and It is possible to provide a saturation charge amount in which the sum of the saturation charge amounts is equal to or greater than the saturation charge amount of the photoelectric conversion unit.

  The second charge accumulating unit can be constituted by a floating diffusion unit that outputs electric charge as an electric signal.

  The unit pixel includes a first transfer gate unit that transfers the photocharge accumulated in the photoelectric conversion unit to the first charge accumulation unit, and the photocharge accumulated in the first charge accumulation unit. A second transfer gate portion that transfers to the floating diffusion portion can be provided.

  The unit pixel includes a reset gate unit that resets the photocharge of the floating diffusion unit, an amplification transistor that converts the photocharge of the floating diffusion unit into an electric signal, and a selection that is connected to the amplification transistor and performs pixel selection A transistor can be further provided.

  In the driving method of the solid-state imaging device according to the first aspect of the present technology, a photoelectric conversion unit that generates and accumulates a photocharge according to the received light amount, a first charge accumulation unit including an embedded MOS capacitor, and A plurality of unit pixels each having a second charge accumulation unit are arranged, and a solid-state imaging device including a pixel array unit capable of performing batch exposure of the plurality of unit pixels has a photoelectric charge generated by the photoelectric conversion unit during an exposure period. The photoelectric conversion unit, the first drive that accumulates the first charge accumulation unit and the second accumulation unit, or the photoelectric charge generated by the photoelectric conversion unit during an exposure period, and the photoelectric conversion unit A second drive for accumulating in the first charge accumulator is performed.

  The electronic device according to the second aspect of the present technology includes a photoelectric conversion unit that generates and accumulates a photocharge according to a received light amount, a first charge accumulation unit including an embedded MOS capacitor, and a second charge accumulation. A plurality of unit pixels having a unit, a pixel array unit capable of performing batch exposure of the plurality of unit pixels, and a photoelectric charge generated by the photoelectric conversion unit during an exposure period, the photoelectric conversion unit, The first drive stored in the charge storage unit and the second storage unit, or the photoelectric charge generated by the photoelectric conversion unit during the exposure period is stored in the photoelectric conversion unit and the first charge storage unit. A solid-state imaging device including a driving unit that performs second driving; and a signal processing unit that performs signal processing on a signal output from the unit pixel.

  In the first aspect or the second aspect of the present technology, is the photocharge generated by the photoelectric conversion unit during the exposure period accumulated in the photoelectric conversion unit, the first charge accumulation unit, and the second accumulation unit? Or, it is stored in the photoelectric conversion unit and the first charge storage unit.

  According to the first aspect or the second aspect of the present technology, an image with a wide dynamic range and less noise can be obtained using global exposure.

1 is a system configuration diagram illustrating an outline of a configuration of a CMOS image sensor to which the present technology is applied. It is a system configuration | structure figure (the 1) which shows the other system configuration | structure of the CMOS image sensor to which this technique is applied. It is a system configuration figure (the 2) showing other system composition of a CMOS image sensor to which this art is applied. It is explanatory drawing about a buried type MOS capacitor and a surface side MOS capacitor. It is explanatory drawing about the combination of a several capacitor structure. It is sectional drawing (the 1) which shows the other structural example of the 2nd electric charge storage part. It is sectional drawing (the 2) which shows the other structural example of the 2nd charge storage part. It is a circuit diagram which shows the circuit structure of a unit pixel. It is the schematic which shows the pixel structure of a unit pixel. 6 is a timing chart for explaining circuit operations of a unit pixel. FIG. 6 is a potential diagram (part 1) for explaining a circuit operation of a unit pixel. It is a potential diagram (the 2) with which it uses for description of the circuit operation | movement of a unit pixel. FIG. 10 is a potential diagram (part 3) for explaining the circuit operation of the unit pixel. FIG. 10 is a potential diagram (part 4) for explaining the circuit operation of the unit pixel. FIG. 10 is a potential diagram (part 5) for explaining the circuit operation of the unit pixel. FIG. 10 is a potential diagram (part 6) for explaining the circuit operation of the unit pixel. FIG. 10 is a potential diagram (part 7) for explaining the circuit operation of the unit pixel. It is a potential diagram (the 8) with which it uses for description of the circuit operation | movement of a unit pixel. It is a circuit diagram which shows the circuit structure of the modification 1 of a unit pixel. It is a circuit diagram which shows the circuit structure of the modification 2 of a unit pixel. It is a timing chart with which it uses for description of the circuit operation | movement of the modification 2 of a unit pixel. It is a circuit diagram which shows the circuit structure concerning the specific example 1 of pixel sharing. It is a circuit diagram which shows the circuit structure concerning the specific example 2 of pixel sharing. FIG. 5 is a potential diagram in the substrate depth direction for explaining the requirements for pinning the substrate surface and for combining the potentials of the FD portion, the first charge accumulation portion, and the second charge accumulation portion. 6 is a timing chart for explaining signal processing in the case of processing example 1 and processing example 2 in the signal processing unit. FIG. 11 is a characteristic diagram (part 1) of an incident light amount—output for explaining signal processing in the case of a processing example 3; FIG. 12 is a characteristic diagram (part 2) of the incident light amount—output for explaining the signal processing in the case of the processing example 3; It is a timing chart with which it uses for description of the circuit operation | movement of the unit pixel which concerns on a modification. It is operation | movement explanatory drawing about the unit pixel which concerns on a reference example. 2 shows a configuration example around a column processing unit, a signal processing unit, and a data storage unit for realizing a circuit operation during long exposure. It is a timing chart (the 1) with which it uses for description of the circuit operation | movement at the time of long time exposure of a unit pixel. It is a timing chart (the 2) with which it uses for description of the circuit operation | movement at the time of long time exposure of a unit pixel. FIG. 6 is a potential diagram (part 1) for explaining circuit operation during long exposure of a unit pixel. FIG. 6 is a potential diagram (part 2) for explaining a circuit operation during long exposure of a unit pixel. FIG. 6 is a potential diagram (part 3) for explaining circuit operation during long exposure of a unit pixel. FIG. 10 is a potential diagram (part 4) for explaining the circuit operation at the time of long exposure of a unit pixel. It is a modification of the timing chart used for description of circuit operation at the time of long exposure of a unit pixel. It is a timing chart (the 1) with which it uses for description of the circuit operation | movement at the time of long exposure of the modification 2 of a unit pixel. It is a timing chart (the 2) with which it uses for description of the circuit operation | movement at the time of long exposure of the modification 2 of a unit pixel. It is a circuit diagram which shows the circuit structure of the unit pixel which abbreviate | omitted the 2nd charge storage part. It is the schematic which shows the pixel structure of the unit pixel which abbreviate | omitted the 2nd charge storage part. It is a timing chart with which it uses for description of the circuit operation | movement of the unit pixel which abbreviate | omitted the 2nd charge storage part. FIG. 6 is a potential diagram (part 1) for explaining a circuit operation of a unit pixel in which a second charge accumulation unit is omitted. FIG. 10 is a potential diagram (part 2) for explaining the circuit operation of the unit pixel in which the second charge accumulation unit is omitted. FIG. 10 is a potential diagram (part 3) for explaining the circuit operation of the unit pixel in which the second charge accumulation unit is omitted. FIG. 10 is a potential diagram (part 4) for explaining the circuit operation of the unit pixel in which the second charge accumulation unit is omitted. FIG. 10 is a potential diagram (part 5) for explaining the circuit operation of the unit pixel in which the second charge accumulation unit is omitted. FIG. 10 is a potential diagram (part 6) for explaining the circuit operation of the unit pixel in which the second charge accumulation unit is omitted. FIG. 14 is a potential diagram (part 7) for explaining the circuit operation of the unit pixel in which the second charge accumulation unit is omitted. FIG. 10 is a potential diagram (part 8) for explaining the circuit operation of a unit pixel in which the second charge accumulation unit is omitted. It is a timing chart (the 1) with which it uses for description of the circuit operation | movement at the time of long-time exposure of the unit pixel which abbreviate | omitted the 2nd charge storage part. FIG. 10 is a timing chart (part 2) for explaining a circuit operation during long-time exposure of a unit pixel in which a second charge accumulation unit is omitted. FIG. 10 is a potential diagram (part 1) for explaining circuit operation during long-time exposure of a unit pixel in which a second charge accumulation unit is omitted. FIG. 10 is a potential diagram (part 2) for explaining a circuit operation during long-time exposure of a unit pixel in which a second charge accumulation unit is omitted. FIG. 12 is a potential diagram (part 3) for explaining circuit operation during long-time exposure of a unit pixel in which a second charge accumulation unit is omitted. FIG. 12 is a potential diagram (part 4) for explaining circuit operation during long-time exposure of a unit pixel in which a second charge accumulation unit is omitted. It is a block diagram which shows an example of a structure of the electronic device which concerns on this technique, for example, an imaging device.

Hereinafter, modes for carrying out the invention (hereinafter referred to as “embodiments”) will be described in detail with reference to the drawings. The description will be given in the following order.
1. 1. Solid-state imaging device to which the present technology is applied 1-1. Basic system configuration 1-2. Other system configurations 2. Description of Embodiment 2-1. Reasons why the total capacity value of the charge storage unit can be increased by dividing the charge storage unit 2-2. 2. Description of a capacitor having a large capacitance value per unit area Example 4 4. Explanation on noise removal processing and arithmetic processing Reference Example 6 Modification 6-1. Example of accumulating photocharge with only photodiode 6-2. Example of switching operation between short exposure and long exposure 6-3. Example in which second charge storage unit is omitted 6-4. 6. Other modified examples Electronic equipment (imaging device)

<1. Solid-state imaging device to which the present technology is applied>
[1-1. Basic system configuration]
FIG. 1 is a system configuration diagram showing an outline of a configuration of a solid-state imaging device to which the present technology is applied, for example, a CMOS image sensor which is a kind of XY address type solid-state imaging device. Here, the CMOS image sensor is an image sensor created by applying or partially using a CMOS process.

  A CMOS image sensor 10 according to this application example includes a pixel array unit 11 formed on a semiconductor substrate (chip) (not shown), and a peripheral circuit unit integrated on the same semiconductor substrate as the pixel array unit 11. It has a configuration. The peripheral circuit unit includes, for example, a vertical drive unit 12, a column processing unit 13, a horizontal drive unit 14, and a system control unit 15.

  The CMOS image sensor 10 further includes a signal processing unit 18 and a data storage unit 19. The signal processing unit 18 and the data storage unit 19 may be mounted on the same substrate as the CMOS image sensor 10 or may be disposed on a different substrate from the CMOS image sensor 10. Each processing of the signal processing unit 18 and the data storage unit 19 may be processing by an external signal processing unit provided on a substrate different from the CMOS image sensor 10, for example, a DSP (Digital Signal Processor) circuit or software. Absent.

  The pixel array unit 11 includes unit pixels (hereinafter also simply referred to as “pixels”) having a photoelectric conversion unit that generates and accumulates photoelectric charges according to the received light amount in the row direction and the column direction. The configuration is two-dimensionally arranged in a matrix. Here, the row direction refers to the pixel arrangement direction (that is, the horizontal direction) of the pixel row, and the column direction refers to the pixel arrangement direction (that is, the vertical direction) of the pixel column. Details of the specific circuit configuration and pixel structure of the unit pixel will be described later.

  In the pixel array unit 11, the pixel drive lines 16 are wired along the row direction for each pixel row, and the vertical signal lines 17 are wired along the column direction for each pixel column in the matrix pixel array. . The pixel drive line 16 transmits a drive signal for driving when reading a signal from the pixel. In FIG. 1, the pixel drive line 16 is shown as one wiring, but is not limited to one. One end of the pixel drive line 16 is connected to an output end corresponding to each row of the vertical drive unit 12.

  The vertical drive unit 12 includes a shift register, an address decoder, and the like, and drives each pixel of the pixel array unit 11 at the same time or in units of rows. That is, the vertical drive unit 12 constitutes a drive unit that drives each pixel of the pixel array unit 11 together with the system control unit 15 that controls the vertical drive unit 12. The vertical drive unit 12 is not shown in the figure for its specific configuration, but generally has a configuration having two scanning systems, a reading scanning system and a sweeping scanning system.

  The readout scanning system selectively scans the unit pixels of the pixel array unit 11 sequentially in units of rows in order to read out signals from the unit pixels. The signal read from the unit pixel is an analog signal. The sweep-out scanning system performs sweep-out scanning with respect to the readout row on which readout scanning is performed by the readout scanning system, preceding the readout scanning by a time corresponding to the shutter speed.

  By the sweep scanning by the sweep scanning system, unnecessary charges are swept out from the photoelectric conversion unit of the unit pixel in the readout row, thereby resetting the photoelectric conversion unit. A so-called electronic shutter operation is performed by sweeping (resetting) unnecessary charges by the sweep scanning system. Here, the electronic shutter operation refers to an operation in which the photoelectric charge of the photoelectric conversion unit is discarded and exposure is newly started (photocharge accumulation is started).

  The signal read by the reading operation by the reading scanning system corresponds to the amount of light received after the immediately preceding reading operation or electronic shutter operation. The period from the read timing by the immediately preceding read operation or the sweep timing by the electronic shutter operation to the read timing by the current read operation is the exposure period of the photo charge in the unit pixel.

  A signal output from each unit pixel of the pixel row selectively scanned by the vertical driving unit 12 is input to the column processing unit 13 through each of the vertical signal lines 17 for each pixel column. The column processing unit 13 performs predetermined signal processing on signals output from the pixels in the selected row through the vertical signal line 17 for each pixel column of the pixel array unit 11, and temporarily outputs the pixel signals after the signal processing. Hold on.

  Specifically, the column processing unit 13 performs at least noise removal processing, for example, CDS (Correlated Double Sampling) processing as signal processing. The CDS processing by the column processing unit 13 removes pixel-specific fixed pattern noise such as reset noise and threshold variation of amplification transistors in the pixel. In addition to noise removal processing, the column processing unit 13 may have, for example, an AD (analog-digital) conversion function to convert an analog pixel signal into a digital signal and output the digital signal.

  The horizontal drive unit 14 includes a shift register, an address decoder, and the like, and sequentially selects unit circuits corresponding to the pixel columns of the column processing unit 13. By the selective scanning by the horizontal driving unit 14, pixel signals subjected to signal processing for each unit circuit in the column processing unit 13 are sequentially output.

  The system control unit 15 includes a timing generator that generates various timing signals, and the vertical driving unit 12, the column processing unit 13, and the horizontal driving unit 14 based on various timings generated by the timing generator. Drive control is performed.

  The signal processing unit 18 has at least an arithmetic processing function, and performs various signal processing such as arithmetic processing on the pixel signal output from the column processing unit 13. The data storage unit 19 temporarily stores data necessary for the signal processing in the signal processing unit 18.

  The CMOS image sensor 10 having the above configuration employs global exposure for executing exposure start and exposure end at the same timing for all the pixels in the pixel array unit 11. That is, the CMOS image sensor 10 can perform batch exposure of all pixels. This global exposure is executed under the drive of the drive unit including the vertical drive unit 12 and the system control unit 15. The global shutter function that realizes global exposure is a shutter operation that is suitable for use in sensing applications that require high-speed imaging of a subject that moves at high speed and that the captured images need to be synchronized.

[1-2. Other system configurations]
The CMOS image sensor 10 to which the present technology is applied is not limited to the system configuration described above. Examples of other system configurations include the following system configurations.

  For example, as shown in FIG. 2, the data storage unit 19 is arranged at the subsequent stage of the column processing unit 13, and the pixel signal output from the column processing unit 13 is supplied to the signal processing unit 18 via the data storage unit 19. And a CMOS image sensor 10A having a system configuration.

  Further, as shown in FIG. 3, the column processing unit 13 is provided with an AD conversion function for performing AD conversion for each column or a plurality of columns of the pixel array unit 11, and a data storage unit is provided for the column processing unit 13. 19 and a CMOS image sensor 10B having a system configuration in which the signal processing unit 18 is provided in parallel.

<2. Description of Embodiment>
In realizing global exposure, the solid-state imaging device (for example, a CMOS image sensor) according to the embodiment deteriorates the image quality of a captured image in a dark time or low illuminance as compared with the conventional technology that realizes global exposure. In order to secure a larger saturation charge amount, the first and second charge storage units are provided in the unit pixel. An embedded MOS capacitor is used as the first charge storage unit, and a capacitor having a larger capacitance value per unit area than the first charge storage unit is used as the second charge storage unit.

  Preferably, for the first charge storage unit and the second charge storage unit, the magnitude relationship between the saturation charge amounts may be set as follows. That is, it is preferable that the first charge accumulation unit has a saturation charge amount smaller than the saturation charge amount of the photoelectric conversion unit.

  When the saturation charge amount of the first charge accumulation unit is made smaller than the saturation charge amount of the photoelectric conversion unit, the small amount is compensated by the second charge accumulation unit. Therefore, the second charge accumulation unit must have a saturation charge amount such that the sum of the saturation charge amount of the first charge accumulation unit is equal to or greater than the saturation charge amount of the photoelectric conversion unit.

  As described above, the unit pixel has the first and second charge accumulation units, the embedded MOS capacitor is used as the first charge accumulation unit, and the first charge accumulation unit is used as the second charge accumulation unit. By using a capacitor having a capacitance value per unit area larger than that of the portion, the following operational effects can be obtained.

  That is, the capacitance value capable of accumulating photocharges is greatly increased compared to the case where the embedded MOS capacitor is formed in the same area as the total area of the first charge accumulation unit and the second charge accumulation unit. In other words, it is possible to secure a larger amount of saturation charge. In addition, embedded MOS capacitors are used for signals at low illuminance, making them less susceptible to interface states, defects, etc., and worsening dark characteristics compared to conventional technologies that have achieved global exposure. Therefore, the image quality of the captured image at low illuminance is not deteriorated.

  As a result, it is possible to realize a CMOS image sensor having a global shutter function that exhibits the same characteristics as a CMOS image sensor having the same unit pixel size and not having a global shutter function. In addition, a CMOS image sensor with a greatly expanded dynamic range can be realized as compared with a conventional CMOS image sensor having a global shutter function having the same unit pixel size.

[2-1. The reason why the total capacity value of the charge storage part can be increased by dividing the charge storage part]
In this way, by using an embedded MOS capacitor as the first charge storage unit and using a capacitor having a larger capacitance value per unit area than the first charge storage unit as the second charge storage unit, the charge storage unit The total capacitance value can be increased. Here, the reason why the total capacitance value of the charge storage section can be increased will be described with a numerical example.

For example, consider a case where a capacitor having an area of 1 μm ² is formed. As 10 fF / [mu] m ² the capacitance value per unit area of 1 fF / [mu] m ^2, the second charge accumulation portion the capacitance value per unit area of the first charge accumulation portion, all capacitors of the area of 1 [mu] m ² first The capacitance value of a capacitor having an area of 1 μm ² is 1 fF.

In this case, replacing half of the area of 1 [mu] m ² by the second charge accumulation portion, the capacitance value of the capacitor of the area of 1 [mu] m ^2, the ^{5.5fF (= 1 / 2μm 2 ×} 1fF + 1 / 2μm 2 × 10fF) . That is, when the half area is replaced with the second charge storage unit, the capacitance value of the capacitor having the area of 1 μm ² is 5.5 times as compared with the case where the half area is not replaced.

Further, when the area of 3/4 of 1 μm ² is replaced with the second charge storage portion, the capacitance value of the capacitor having the area of 1 μm ² is 7.75 fF, which is 7.75 times that in the case where the capacitor is not replaced. In addition, when replacing the half area of 1 μm ² with the second charge storage unit, if the capacitance value per unit area of the second charge storage unit is 20 fF / μm ² , the capacitance value of the capacitor having the area of 1 μm ² is 10.5 fF, which is 10.5 times that in the case of no replacement.

  On the other hand, a capacitor having a large capacitance value per unit area generally has a large leakage current, and the second charge storage section has a problem that the dark characteristics such as dark current and white point are significantly deteriorated. Therefore, when the photocharge is transferred simultaneously from all the pixels from the photoelectric conversion unit, the photocharge at the time of low illuminance is accumulated in the first charge accumulation unit. Here, the “photocharge at low illuminance” refers to a photocharge that is less than or equal to the saturation charge amount of the first charge storage portion. Since the first charge accumulating portion is composed of an embedded capacitor, it is less susceptible to the influence of interface states, defects, etc., and has better dark characteristics than the second charge accumulating portion.

  In addition, the photocharge at the time of high illuminance is accumulated in both the first charge accumulation unit and the second accumulation capacitor. Here, the “photocharge at high illuminance” refers to a photocharge that exceeds the saturation charge amount of the first charge storage unit. At high illuminance with a large amount of charge to be handled, a high S / N can be ensured, so that it is difficult to be affected by dark characteristics such as dark current and white spot. Therefore, even if photocharges at high illuminance are accumulated in the second charge accumulating portion having a large leakage current, the influence on the image quality is extremely low.

  As is apparent from the above description, an embedded MOS capacitor is used as the first charge storage unit, and a capacitor having a larger capacitance value per unit area than the first charge storage unit is used as the second charge storage unit. Thus, a larger amount of saturation charge can be secured. On the contrary, if the saturation charge amount is equal, the unit pixel size can be reduced by the amount that can save space.

  In addition, when all pixels are read simultaneously, the photocharge at the time of low illuminance is accumulated in the first charge accumulating section having good dark characteristics such as dark current and white point, while the second having poor dark characteristics. By storing photocharges at high illuminance in the charge accumulating unit, the image quality of the captured image at dark or low illuminance does not deteriorate as compared with the conventional technology that realizes global exposure.

  As an example of a capacitor having a capacitance value per unit area larger than that of the first charge storage unit, that is, a capacitor having a capacitance value per unit area larger than that of the embedded MOS capacitor, a surface-type MOS capacitor can be cited.

[2-2. Description of capacitor with large capacitance per unit area]
Here, the difference between the embedded MOS capacitor constituting the first charge accumulation unit and the surface side MOS capacitor constituting the second charge accumulation unit will be described.

  FIG. 4 shows the embedded MOS capacitor A and the surface-side MOS capacitor B. 4A and 4B, (a) shows a cross-sectional structure of each MOS capacitor, and (b) shows an equivalent circuit.

  As shown in FIGS. 4A and 4B, in each MOS capacitor, a gate electrode 23 is disposed on a semiconductor substrate 21 with a gate oxide film 22 interposed therebetween. In the case of the embedded MOS capacitor A, a charge storage region 24 for storing signal charges is formed deep in the semiconductor substrate 21, and in the case of the surface MOS capacitor B, the charge storage region 25 is formed on the substrate surface of the semiconductor substrate 21. The structure is formed.

  4A and 4B, Cox represents the capacitance value of the gate oxide film 22, Cch represents the capacitance value between the substrate surface and the charge accumulation region, and Csi represents the capacitance value between the charge accumulation region and the substrate. Each is shown.

(For embedded capacitors)
When the capacitance value per unit area of the charge storage region 24 is Cb, the capacitance value Cb is expressed by the following equation (1).
Cb = Cox · Cch / (Cox + Cch) + Csi
= Cox · {1 / (1 + Cox / Cch)} + Csi (1)

Here, if it is considered that the capacitance value Csi between the charge storage region and the substrate is sufficiently small, the equation (1) can be approximated by the following equation (2).
Cb≈Cox · {1 / (1 + Cox / Cch)} (2)

(For surface type capacitors)
When the capacitance value per unit area of the charge storage region is Cs, the capacitance value Cs is expressed by the following equation (3).
Cs = Cox + Csi (3)

Here, if it is considered that the capacitance value Csi between the charge storage region and the substrate is sufficiently small, it can be approximated by the capacitance value Cox of the gate oxide film 22 as shown in the following equation (4).
Cs≈Cox (4)

  That is, the magnitude relationship between the capacitance value Cb per unit area of the charge storage region 24 and the capacitance value Cs per unit area of the charge storage region 25 is Cb <Cs, and the charge storage region is embedded from the substrate surface into the substrate. This reduces the capacitance value. In other words, the capacitance value is increased by bringing the charge accumulation region from the substrate to the substrate surface.

(Explanation on how to increase the capacity value per unit area in terms of material)
The capacitance value Cox of the gate oxide film 22 per unit area is expressed by the following equation (5).
Cox = εox / tox (5)
Here, εox is the dielectric constant of the gate oxide film 22, and tox is the film thickness of the gate oxide film 22.

The film thickness tox of the gate oxide film 22 is important from the viewpoint of the withstand voltage and the leak amount, but the capacitance value Cox per unit area can be increased by using a material having a high dielectric constant even with the same film thickness. Examples of the material having a high dielectric constant include the following materials.
Si ₃ N ₄ : relative dielectric constant 7
Ta ₂ O ₅ : relative dielectric constant 26
HfO ₂ : relative dielectric constant 25
ZrO ₂ : relative dielectric constant 25

Since the product of the vacuum dielectric constant and the relative dielectric constant is the dielectric constant of each material, the capacitance value per unit area increases when the ratio of the relative dielectric constant to SiO ₂ (relative dielectric constant 3.9) is considered. You can estimate the minutes. For example, assuming a surface MOS capacitor, if Si ₃ N ₄ having the same film thickness is used instead of SiO ₂ , the capacitance value per unit area is 1.8 times, and if Ta ₂ O ₅ is used, per unit area The capacity value of 6.7 increases by 6.7 times.

(Explanation on how to structurally increase the capacitance per unit area)
Moreover, structurally, the capacitance value per unit area can be increased by combining a plurality of capacitor structures. As an example of the combination structure, the structure shown in FIG. 5, that is, the structure A in which a planar type MOS capacitor and a junction type capacitor are combined, and the structure B in which a planar type MOS capacitor and a stack type capacitor are combined can be cited. .

  First, the combination structure A will be described. For example, a P-type well 52 is formed on the N-type semiconductor substrate 51. An N + type semiconductor region 41 serving as an intermediate electrode is formed in the surface layer portion of the P type well 52, and a junction type MOS capacitor is formed between the P type well 52 serving as a lower electrode. Furthermore, the upper electrode 42 is disposed on the substrate surface via the insulating film 53, whereby a planar type MOS capacitor is formed in parallel with the junction type MOS capacitor. That is, the second charge storage unit 40 is formed by parallel connection of a planar type MOS capacitor and a junction type capacitor.

  Next, the combination structure B will be described. The first charge storage unit 30 is the same planar type MOS capacitor as in the combination structure A. As for the second charge storage section 40, a planar type MOS capacitor is formed in a region divided by the element isolation insulating films 55 and 56, and a stack type capacitor is formed in an upper layer in parallel connection.

  Specifically, a P + (or N +) type semiconductor region 43 serving as a lower electrode is formed on the surface layer portion of the P type well 52, and an intermediate electrode 45 is formed on the semiconductor region 43 via a capacitive insulating film 44. Has been. This structure is a planar MOS capacitor structure. Further, an upper electrode 47 is formed on the intermediate electrode 45 via a capacitive insulating film 46. This structure is a stacked capacitor structure. The intermediate electrode 45 is electrically connected to the N + type semiconductor region 41 by a wiring 57.

  According to this combination structure B, that is, according to the combination structure of a planar type MOS capacitor and a stack type capacitor, a capacitor having a larger capacitance value per unit area can be formed.

(Another structure example of the second charge storage unit)
6 and 7 show other structural examples of the second charge storage unit 40. FIG. 6 and 7, the same parts as those in FIG. 5 are denoted by the same reference numerals.

  FIG. 6A is a cross-sectional view showing the structure of a planar MOS capacitor. In the planar type MOS capacitor constituting the second charge storage unit 40, a P + (or N +) type semiconductor region 43 serving as a lower electrode is formed in the surface layer portion of the P type well 52, and a capacitance is formed on the semiconductor region 43. The upper electrode 45 is formed through the insulating film 44.

  FIG. 6B is a cross-sectional view showing the structure of the stacked capacitor 1. In the stack type capacitor 1 constituting the second charge storage section 40, a lower electrode 45 is formed on the element isolation insulating film 55, and an upper electrode 47 is formed on the lower electrode 45 via a capacitive insulating film 46. It has a structured.

  FIG. 7A is a cross-sectional view showing the structure of the stacked capacitor 2. In the stack type capacitor 2 constituting the second charge storage unit 40, a lower electrode 45 having a U-shaped cross section is electrically connected to the N + type semiconductor region 41, and a capacitive insulating film 46 is formed inside the lower electrode 45. Thus, the upper electrode 47 is inserted.

  In the case of this stacked capacitor 2 structure, a power supply voltage is applied to the upper electrode 47 or grounded. According to the stacked capacitor 2 including the lower electrode 45 having a U-shaped cross section and the upper electrode 47 embedded inside the lower electrode 45, the capacitance is higher than that of a normal stacked capacitor, for example, the stacked capacitor 1. There is an advantage that the opposing area that contributes to can be increased.

  FIG. 7B is a cross-sectional view showing the structure of the trench capacitor. In the trench type capacitor constituting the second charge accumulating unit 40, a trench 48 is formed so as to penetrate the P-type well 52 and reach the substrate 51, and the capacitor is formed in the trench 48. ing.

  Specifically, an N + (or P +) type semiconductor region 43 serving as a lower electrode is formed on the inner wall of the trench 48, and the capacitor insulating film 44 is covered on the inner wall of the semiconductor region 43, and the capacitor insulating film 44 is interposed therebetween. Thus, the upper electrode 45 is embedded.

Further, for the second charge storage section 40, a planar type MOS capacitor, a junction type capacitor, a stack type capacitor, a trench, in which a part or all of the capacitive insulating film is made of a material having a higher dielectric constant than that of the silicon oxide film. Type capacitors or a combination thereof. Examples of the material having a dielectric constant higher than that of the silicon oxide film (SiO ₂ ) include Si ₃ N ₄ , Ta ₂ 0 ₅ , HfO ₂ , and ZrO ₂ .

  As described above, an example of the structure of the second charge storage unit 40 has been described with reference to FIGS. 6 and 7. However, the structure of the second charge storage unit 40 is not limited to these structural examples. Various methods developed so far can be used to increase the capacity of the memory capacitor.

<3. Example>
Hereinafter, specific examples of the unit pixel having the first charge accumulation unit 30 and the second charge accumulation unit 40 in the pixel will be described.

(Circuit configuration of unit pixel 60A)
FIG. 8 is a circuit diagram illustrating a circuit configuration of a unit pixel 60A to which the present technology is applied. As shown in FIG. 8, the unit pixel 60 </ b> A includes, for example, a PN junction photodiode 61 as a photoelectric conversion unit that receives light to generate and store photoelectric charges. The photodiode 61 generates and accumulates photocharges corresponding to the received light quantity.

  The unit pixel 60A further includes, for example, a first transfer gate unit 62, a second transfer gate unit 63, a third transfer gate unit 64, a reset gate unit 65, a first charge storage unit 66, and a second charge storage unit. A section 67, an amplification transistor 68, a selection transistor 69, and a charge discharge gate section 70.

  In the unit pixel 60A having the above configuration, the first and second charge accumulation units 66 and 67 correspond to the first and second charge accumulation units described above. That is, the first charge storage unit 66 is provided as an embedded MOS capacitor between the first transfer gate unit 62 and the second transfer gate unit 63 in terms of a circuit. A drive signal SG (hereinafter also referred to as a transfer signal SG) is applied to the gate electrode of the first charge storage section 66. The second charge accumulation unit 67 is configured by a capacitor having a larger capacitance value per unit area than the first charge accumulation unit 66. Details of the layout and cross-sectional structure of the first and second charge storage portions 66 and 67 will be described later.

For the unit pixel 60A, a plurality of drive lines are wired, for example, for each pixel row as the pixel drive lines 16 in FIG. Various drive signals TG, SG, FG, CG, RST, SEL, and PG are supplied from the vertical drive unit 12 of FIG. 1 through a plurality of drive lines of the pixel drive line 16. These drive signals TG, SG, FG, CG, RST, SEL, and PG are active in the high level (for example, power supply voltage V _DD ) because each transistor is an NMOS transistor in the above configuration. This is a pulse signal in which a low level state (for example, a negative potential) becomes an inactive state.

  The drive signal TG is applied as a transfer signal to the gate electrode of the first transfer gate unit 62. The first transfer gate unit 62 is connected between the photodiode 61 and the first charge storage unit 66 in terms of a circuit. The first transfer gate unit 62 is turned on in response to a drive signal TG (hereinafter also referred to as a transfer signal TG) being in an active state, so that the photocharge accumulated in the photodiode 61 is obtained. Is transferred to the first charge storage section 66. The photocharge transferred by the first transfer gate unit 62 is temporarily stored in the first charge storage unit 66.

  The drive signal FG is applied as a transfer signal to the gate electrode of the second transfer gate unit 63. The second transfer gate unit 63 includes a circuit between the first charge storage unit 66 and a floating diffusion unit (hereinafter referred to as “FD unit”) 71 to which the gate electrode of the amplification transistor 68 is connected. It is connected to the. The FD unit 71 converts the photoelectric charge into an electric signal, for example, a voltage signal, and outputs it. The second transfer gate unit 63 is stored in the first charge storage unit 66 by being turned on in response to the drive signal FG (hereinafter also referred to as the transfer signal FG) being activated. The photocharges being transferred are transferred to the FD unit 71.

  The drive signal CG is applied as a transfer signal to the gate electrode of the third transfer gate unit 64. The third transfer gate unit 64 is connected between the first charge storage unit 66 and the second charge storage unit 67 in terms of a circuit. The third transfer gate unit 64 becomes conductive in response to the drive signal CG (hereinafter also referred to as the transfer signal CG) being in an active state. The potentials of the charge storage portions 67 are coupled.

The drive signal RST is applied as a reset signal to the gate electrode of the reset gate unit 65. In the reset gate portion 65, one source / drain region is connected to the reset voltage _VDR and the other source / drain region is connected to the FD portion 71 in terms of a circuit. Then, when the drive signal RST (hereinafter also referred to as a reset signal RST) becomes active, the reset gate unit 65 becomes conductive in response to this, thereby bringing the potential of the FD unit 71 to the level of the reset voltage _VDR . Reset.

The amplification transistor 68 has a circuit in which a gate electrode is connected to the FD unit 71 and a drain electrode is connected to the power supply voltage V _DD , and is a readout circuit that reads out photoelectric charges obtained by photoelectric conversion in the photodiode 61, so-called It becomes the input part of the source follower circuit. That is, the amplification transistor 68 forms a source follower circuit with a constant current source 80 connected to one end of the vertical signal line 17 by connecting the source electrode to the vertical signal line 17 through the selection transistor 69.

  The drive signal SEL is applied as a selection signal to the gate electrode of the selection transistor 69. The selection transistor 69 is connected in circuit between the source electrode of the amplification transistor 68 and the vertical signal line 17. When the drive signal SEL (hereinafter also referred to as a selection signal SEL) becomes active, the selection transistor 69 becomes conductive in response to the pixel signal output from the amplification transistor 68 with the unit pixel 60A selected. Connect to the vertical signal line 17.

The drive signal PG is applied as a charge discharge control signal to the gate electrode of the charge discharge gate unit 70. The charge discharge gate unit 70 is connected between the photodiode 61 and the charge discharge unit (for example, the power supply voltage V _DD ) in circuit. Then, when the drive signal PG (hereinafter also referred to as a charge discharge control signal PG) becomes active, the charge discharge gate unit 70 becomes conductive in response to this, and a predetermined amount from the photodiode 61 or a photodiode. All the photocharges accumulated in 61 are selectively discharged to the charge discharging unit.

  The charge discharge gate unit 70 is provided for the following purpose. That is, by making the charge discharge gate unit 70 conductive during a period in which photocharge accumulation is not performed, the photodiode 61 is saturated with photocharge, and charges exceeding the saturation charge amount are the first and second charges. This is to avoid overflowing the storage units 66 and 67 and surrounding pixels.

(Pixel structure of unit pixel 60A)
FIG. 9 is a schematic diagram showing the pixel structure of the unit pixel 60A, and in the figure, the same parts as those in FIG. 8 are denoted by the same reference numerals. FIG. 9 shows a plane pattern showing a pixel layout, an AA ′ arrow section and a BB ′ arrow section in the plane pattern, respectively.

  In FIG. 9, the photodiode (PD) 61 has a PN junction in which an N-type semiconductor region 611 is formed in a P-type well 52 on a semiconductor substrate 51, as is apparent from the sectional view taken along the line BB ′. It has a diode configuration. The photodiode 61 is a buried photodiode (so-called HAD (Hole Accumulation Diode) sensor structure) in which a depletion end is separated from the interface by forming a P-type semiconductor region 612 in the surface layer portion thereof.

  The first transfer gate portion 62 has a gate electrode 621 disposed on a substrate surface via a gate insulating film (not shown), and a P − type semiconductor region 622 formed on the substrate surface layer portion. It has become. The P − type semiconductor region 622 slightly deepens the potential below the gate electrode 621 as compared to the case where the semiconductor region 622 is not formed. As a result, as is clear from the cross-sectional view taken along the line B-B ′, the P− type semiconductor region 622 has a predetermined amount or more of photocharges overflowing from the photodiode 61, specifically, the saturation charge amount of the photodiode 61. An overflow path is formed to transfer photocharges exceeding 1 to the first charge storage section 66.

  The first charge storage section 66 has a gate electrode 661 disposed on the substrate surface via a gate insulating film (not shown), and is formed as an embedded MOS capacitor under the gate electrode 661. That is, the first charge accumulating portion 66 is an embedded region composed of an N-type semiconductor region 662 formed in the P-type well 52 below the gate electrode 661 and a P-type semiconductor region 663 formed in the surface layer portion. A type MOS capacitor is used.

  The second transfer gate portion 63 has a gate electrode 631 disposed on the substrate surface via a gate insulating film (not shown). The second transfer gate unit 63 uses the N-type semiconductor region 662 of the first charge storage unit 66 as one source / drain region and the N + type semiconductor region 711 serving as the FD unit 71 as the other source / drain region. .

  Accordingly, the unit pixel 60A includes a pixel in which the first charge storage portion 66 is formed as an embedded MOS capacitor under the gate electrode 661 formed adjacent to the first and second transfer gate portions 62 and 63. It has a structure.

  The third transfer gate portion 64 has a gate electrode 641 disposed on the substrate surface via a gate insulating film (not shown). The third transfer gate unit 64 uses the N-type semiconductor region 662 of the first charge storage unit 66 as one source / drain region and the N + type semiconductor region 642 formed in the substrate surface layer as the other source / drain region. It is said.

  One end of the second charge storage unit 67 is electrically connected to the N + type semiconductor region 642 of the third transfer gate unit 64. The other end of the second charge storage unit 67 is connected to a negative power source (for example, ground).

  The second transfer gate unit 63, the gate electrode 661 of the first charge storage unit 66, and the third transfer gate unit 64 include the FD unit 71, the first charge storage unit 66, and the second transfer gate unit 66. The function of combining or dividing the potential of the charge storage section 67 is performed.

  Further, the third transfer gate portion 64 has a structure in which an N − type semiconductor region 643 is formed in the surface layer portion of the channel portion. The N − type semiconductor region 643 slightly deepens the potential below the gate electrode 641 as compared to the case where the semiconductor region 643 is not formed. Thereby, as is clear from the cross-sectional view taken along the line AA ′, the N− type semiconductor region 643 causes the photocharge exceeding the saturation charge amount of the first charge accumulation unit 66 to the second charge accumulation unit 67. It forms an overflow path to transfer.

  Here, regarding the overflow path formed under the first and third transfer gate portions 62 and 64, the photocharge accumulated in the first accumulated charge portion 66 does not leak into the photodiode 61. It is important that the second accumulated charge portion 67 is formed so as to be transferred.

  As described above, in the unit pixel 60A, by having an overflow path under the gate electrode 641 of the third transfer gate portion 64, the photoelectric charge overflowing from the photodiode 61 at the time of high illuminance is transferred to the second charge accumulation portion 67. Can also accumulate. Specifically, even when the third transfer gate unit 64 is in a non-conducting state, a predetermined amount or more of the photocharge overflowing from the first charge storage unit 66 is transferred to the second charge storage unit 67, It can be stored in the charge storage section 67. Thereby, the saturation charge amount of the first charge storage unit can be set smaller than the saturation charge amount of the photodiode 61.

(Circuit operation of unit pixel 60A)
Next, the circuit operation of the unit pixel 60A will be described with reference to the timing chart of FIG. 10 and the potential diagrams of FIGS.

  FIG. 10 shows a timing chart of the selection signal SEL, the reset signal RST, the transfer signal TG, the charge discharge control signal PG, the transfer signal CG, the transfer signal SG, and the transfer signal FG of the unit pixel 60A. FIGS. 11 to 18 show the potential state of the unit pixel 60A in the Nth row at times ta to th in the timing chart of FIG. 10, respectively.

  First, at time t1, the selection signal SEL, the reset signal RST, the transfer signal CG, the transfer signal SG, and the transfer signal FG are simultaneously activated in all the pixels while the charge discharge control signal PG remains active. Accordingly, the selection transistor 69, the reset gate unit 65, the third transfer gate unit 64, the gate electrode 661 of the first charge storage unit 66, the second transfer gate unit 63, and the charge discharge gate unit 70 are in a conductive state. become.

  FIG. 11 shows the potential state of the unit pixel 60A at time ta between time t1 and time t2. In this way, the potentials of the FD unit 71, the first charge storage unit 66, and the second charge storage unit 67 are combined, and the combined region is reset.

  Thereafter, all the pixels simultaneously become inactive in the order of the reset signal RST, the selection signal SEL, the transfer signal FG, the transfer signal SG, and the transfer signal CG. At time t2, the charge discharge control signal PG becomes inactive at the same time for all the pixels. As a result, an exposure period common to all pixels is entered.

  FIG. 12 shows the potential state of the unit pixel 60A at time tb between time t2 and time t3. As described above, the photocharge is accumulated in the photodiode 61 and, at the time of high illuminance, the photocharge overflowing from the photodiode 61 passes through the overflow path of the first transfer gate portion 62 and becomes the first charge. Accumulated in the accumulation unit 66. Furthermore, when the first charge accumulation unit 66 is saturated, the photocharge overflowing from the first charge accumulation unit 66 passes through the overflow path of the third transfer gate unit 64 to the second charge accumulation unit 67. Accumulated. In the case of low illuminance, photocharge is stored only by the photodiode 61.

  Next, at time t3, the transfer signal TG and the transfer signal SG are in an active state, and the first transfer gate unit 62 and the gate electrode 661 of the first charge storage unit 66 are in a conductive state.

  FIG. 13 shows the potential state of the unit pixel 60A at time tc between time t3 and time t4. As described above, the photocharge accumulated in the photodiode 61 is transferred to the first charge accumulation unit 66 and accumulated in the first charge accumulation unit 66.

  Next, at time t4, the transfer signal TG becomes inactive at the same time for all the pixels, and at the same time, the charge discharge control signal PG becomes active. Then, at the same time as the first transfer gate portion 62 becomes non-conductive, the charge discharge gate portion 70 becomes conductive. Thereby, the exposure period common to all pixels ends.

  Thereafter, the transfer signal SG is also inactivated, the gate electrode 661 of the first charge storage unit 66 is turned off, and the potential of the first charge storage unit 66 is restored. At this time, when the accumulated charge amount of the first charge accumulation unit 66 exceeds the saturation charge amount, the photocharge overflowing from the first charge accumulation unit 66 passes through the overflow path of the third transfer gate unit 64. Then, it is transferred to the second charge storage portion 67.

  Then, after the exposure period common to all the pixels is completed, reading of the photocharges accumulated one by one in order is performed.

  Specifically, at time t5, the selection signal SEL in the Nth row is activated, and the selection transistor 69 in the Nth row is turned on, so that the unit pixel 60A in the Nth row is selected. At the same time, the reset signal RST becomes active and the reset gate unit 65 becomes conductive, whereby the FD unit 71 is reset. At time t6, the reset signal RST becomes inactive.

  FIG. 14 shows the potential state of the unit pixel 60A at time td between time t6 and time t7. The potential of the FD unit 71 in this state is output to the vertical signal line 17 through the amplification transistor 68 and the selection transistor 69 as the first reset level N1.

  Next, at time t7, the transfer signal FG becomes active, so that the second transfer gate portion 63 becomes conductive.

  FIG. 15 shows the potential state of the unit pixel 60A at time te between time t7 and time t8. As described above, the photocharge accumulated in the first charge accumulation unit 66 is transferred to the FD unit 71.

  Next, at time t8, the transfer signal FG becomes inactive, and the second transfer gate unit 63 becomes non-conductive.

  FIG. 16 shows the potential state of the unit pixel 60A at time tf between time t8 and time t9. In this state, the potential of the FD unit 71 is output to the vertical signal line 17 through the amplification transistor 68 and the selection transistor 69 as the first signal level S1 corresponding to the amount of charge stored in the first charge storage unit 66.

  Next, at time t <b> 9, the transfer signals CG, SG, and FG are simultaneously activated, and the third transfer gate unit 64, the gate electrode 661 of the first charge storage unit 66, and the second transfer gate unit 63. Are both conductive.

  FIG. 17 shows the potential state of the unit pixel 60A at time tg between time t9 and time t10. In this way, the potentials of the FD unit 71, the first charge storage unit 66, and the second charge storage unit 67 are combined, and photocharges are stored over the entire combined region. Then, this photoelectric charge is output to the vertical signal line 17 through the amplification transistor 68 and the selection transistor 69 as the second signal level S2.

  Next, at time t10, the reset signal RST becomes active, and the reset gate unit 65 becomes conductive. As a result, the region where the potentials of the FD unit 71, the first charge storage unit 66, and the second charge storage unit 67 are combined is reset.

  Next, at time t11, the reset signal becomes inactive, and the reset gate unit 65 becomes non-conductive.

  FIG. 18 shows the potential state of the unit charge 60A at time th between time t11 and time t12. The potential in the region where the potentials in this state are combined is output to the vertical signal line 17 through the amplification transistor 68 and the selection transistor 69 as the second reset level N2.

  Next, at time t12, the selection signal SEL in the N-th row becomes inactive, and the selection transistor 69 in the N-th row becomes non-conductive, so that the unit pixel 60A in the N-th row becomes non-selected. .

  Thereafter, the transfer signal FG, the transfer signal SG, and the transfer signal CG are made inactive in the order of the second transfer gate unit 63, the gate electrode 661 of the first charge storage unit 66, and the third transfer gate unit 64. Is turned off.

  Note that the inactive state in the order of the transfer signal FG, the transfer signal SG, and the transfer signal CG is caused by the channel charge accumulated on the substrate surface when the gate electrode 661 of the first charge accumulation unit 66 is conductive. This is because the charge is accumulated in the second charge accumulation unit 67. Unlike the FD unit 71, the reset is not performed only by the second charge storage unit 67, and thus there is no concern that the pixel charge is offset by resetting the channel charge.

  Through the series of circuit operations described above, the first reset level N1, the first signal level S1, the second signal level S2, and the second reset level N2 are sequentially output from the unit pixel 60A to the vertical signal line 17. Will be. For the first reset level N1, the first signal level S1, the second signal level S2, and the second reset level N2 that are sequentially output in this way, a predetermined signal is output from the subsequent signal processing unit. Processing is performed. Details of the signal processing will be described later.

  As described above, according to the unit pixel 60 </ b> A, an embedded MOS capacitor is used as the first charge accumulation unit 66, and the capacitance value per unit area is larger than that of the first charge accumulation unit 66 as the second charge accumulation unit 67. A larger amount of saturation charge can be ensured by using a capacitor having a large value. On the contrary, if the saturation charge amount is equal, the unit pixel size can be reduced by the amount that can save space.

  In addition, when all the pixels are simultaneously read, the photocharge at the time of low illuminance is accumulated in the first charge storage section 66 having good characteristics at the time of darkness, while the photocharge at the time of high illuminance is the second having poor characteristics at the time of darkness. It is stored in the charge storage unit 67. Therefore, the image quality of the captured image at the time of darkness or low illuminance does not deteriorate as compared with the prior art that realizes global exposure.

(Modification 1)
FIG. 19 is a circuit diagram showing a circuit configuration of a unit pixel 60A1 according to Modification 1 of the unit pixel 60A. In FIG. 19, parts that are the same as those in FIG. 8 are given the same reference numerals.

  The unit pixel 60A1 according to Modification 1 is different from the unit pixel 60A in that the charge discharge gate unit 70 is omitted.

  For example, when the photodiode 61 is not saturated by another method during the period in which the photocharge is not accumulated, or when there is no fear that the photodiode 61 is saturated with the photocharge, the charge discharge gate portion 70 is thus formed. Can be omitted.

(Modification 2)
FIG. 20 is a circuit diagram illustrating a circuit configuration of a unit pixel 60A2 according to Modification 2 of the unit pixel 60A. In FIG. 20, the same components as those in FIG. 8 are denoted by the same reference numerals.

  The unit pixel 60A2 according to Modification 2 is different from the unit pixel 60A in that the selection transistor 69 is omitted. In the unit pixel 60A2, the pixel selection function by the selection transistor 69 is realized by making the drain voltage DRN applied to the drain electrode of the reset gate portion 65 variable.

  Specifically, by applying a high voltage as the drain voltage DRN to the drain electrode of the reset gate portion 65, the amplification transistor 68 is activated and performs a signal output operation. That is, the amplification transistor 68 acts as a selection transistor in combination with the switching operation of the drain voltage DRN. By omitting the selection transistor 69, there is an advantage that one circuit element constituting the unit pixel 60 can be reduced per pixel.

  FIG. 21 is a timing chart showing the state of each signal regarding the circuit operation of the unit pixel 60A2, similarly to FIG.

  In terms of circuit operation, only the timing of the reset signal RST is different from the case of the circuit operation of the unit pixel 60A, which is basically the same.

(Pixel sharing)
In the unit pixels 60A, 60A1, and 60A2, circuit elements constituting the pixel can be shared among a plurality of pixels.

  FIG. 22 is a circuit diagram showing a circuit configuration according to specific example 1 of pixel sharing. Here, a case where a part of the pixel constituent elements is shared between four adjacent pixels 60A-1 to 60A-4 is taken as an example. However, the number of shared pixels is not limited to four pixels. The relationship between the four adjacent pixels 60A-1 to 60A-4 may be shared by, for example, four pixels each having two pixels in the matrix direction, or may be shared by four pixels in the column direction.

  In the first specific example, pixel sharing in the case of the pixel configuration of the unit pixel 60A is taken as an example. The circuit elements after the FD section 71 including the reset gate section 65, that is, the three circuit elements of the reset gate section 65, the amplification transistor 68, and the selection transistor 69 are shared among the four pixels.

  FIG. 23 is a circuit diagram illustrating a circuit configuration according to a specific example 2 of pixel sharing. Here, a case where a part of the pixel constituent elements is supplied between the four pixels 60A-1 to 60A-4 adjacent to each other is described as an example. However, the number of shared pixels is not limited to four pixels. The relationship between the four adjacent pixels 60A-1 to 60A-4 may be shared by, for example, four pixels each having two pixels in the matrix direction, or may be shared by four pixels in the column direction.

  In the specific example 2, pixel sharing in the case of the pixel configuration of the unit pixel 60A2 according to the modification 2 is taken as an example. In addition, the circuit elements after the FD section 71 including the reset gate section 65, that is, the two circuit elements of the reset gate section 65 and the amplification transistor 68 are shared among the four pixels.

  As described above, by combining the circuit element sharing technique among a plurality of pixels, it is possible to obtain the same operation effect as that of the unit pixel 60A, and to reduce the unit pixel size. . In addition, a larger amount of saturation charge can be secured by saving space. On the contrary, if the saturation charge amount is equal, the unit pixel size can be reduced by the amount that can save space.

  Here, each potential of the first to third transfer gate portions 62 to 64 and the gate electrode 661 of the first charge storage portion 66 will be described. FIG. 24 shows the substrate depth direction for pinning the substrate surface and for explaining the requirements for coupling the potentials of the FD portion 71, the first charge storage portion 66, and the second charge storage portion 67. FIG.

  The potential of the gate electrode in the non-conducting state of the first to third transfer gate portions 62 to 64 and the gate electrode 661 of the first charge storage portion 66 is the substrate regardless of the conductive layer directly under the gate oxide film. It is set to a potential (for example, negative potential) that brings the surface into a pinning state. In this way, the substrate surface can be brought into a pinning state, and an effect of improving dark characteristics such as dark current and white spot can be obtained.

The substrate surface potential in the conductive state of the second and third transfer gate portions 63 and 64 and the gate electrode 661 of the first charge storage portion 66 is applied to the reset voltage V _DR , that is, the drain of the reset gate portion 65. The potential is set to be higher than the applied potential. By doing so, the potentials of the FD unit 71, the first charge storage unit 66, and the second charge storage unit 67 can be coupled.

<4. Explanation regarding noise removal processing and arithmetic processing>
From the unit pixel 60A described above and the unit pixel according to the modified example, the first reset level N1, the first signal level S1, the second signal level S2, and the second reset level N2 are vertically arranged in this order. A signal is output to the signal line 17. In the subsequent signal processing unit, for example, the column processing unit 13 or the signal processing unit 18 illustrated in FIGS. 1 to 3, the first reset level N1, the first signal level S1, the second signal level S2, and A predetermined noise removal process and a signal process are performed on the second reset level N2. Hereinafter, the noise removal processing in the column processing unit 13 in the subsequent stage and the arithmetic processing in the signal processing unit 18 will be described.

  First, for example, processing in a CDS circuit as noise removing means built in the column processing unit 13 will be described. As the CDS circuit, a circuit having a known circuit configuration can be used, and the circuit configuration is not limited.

  FIG. 25 is a timing chart for explaining the noise removal processing in the case of the processing example 1 and the case of the processing example 2 in the column processing unit 13.

(Processing example 1)
First, the difference between the voltage signal S1 based on the photocharge transferred to the FD unit 71 at the time of signal reading and the voltage signal N1 based on the reset level before the photocharge is transferred to the FD unit 71 is obtained. Furthermore, the voltage signal S2 based on the photocharge accumulated in the FD unit 71, the first charge accumulation unit 66, and the second charge accumulation unit 67, the FD unit 71, the first charge accumulation unit 66, and A difference from the voltage signal N2 based on the reset level after resetting the second charge storage unit 67 is obtained. When the first difference is SN1, and the second difference is SN2, SN1 = S1-N1 and SN2 = S2-N2.

  As described above, in the processing example 1, the signals S1 and N1 that are output first are subjected to CDS processing in which pixel-specific fixed pattern noise such as reset noise and threshold variation of the amplification transistors in the pixel is removed. For the signals S2 and N2 that are output later, CDS processing is performed in which fixed pattern noise unique to the pixel such as threshold variation of amplification transistors in the pixel is removed but reset noise is not removed. However, since the arithmetic processing does not require the use of a frame memory, there are advantages that the circuit configuration can be simplified and the cost can be reduced.

(Processing example 2)
In the processing example 2, in order to use the information of the previous frame, a storage unit, for example, a frame memory is required. Accordingly, the arithmetic processing of the processing example 2 is performed, for example, by using the data storage unit 19 as a storage unit in the signal processing unit 18 or using a frame memory in an external DSP circuit.

  Specifically, first, the difference between the voltage signal S1 based on the photocharge transferred to the FD unit 71 at the time of signal reading and the voltage signal N1 based on the reset level before the photocharge is transferred to the FD unit 71 is calculated. Take. Next, the difference between the voltage signal S2 based on the photocharge accumulated in the FD unit 71, the first charge accumulation unit 66, and the second charge accumulation unit 67 and the voltage signal N2A in the previous frame is obtained. The voltage signal N2A is a signal based on a reset level after resetting the photocharges accumulated in the FD unit 71, the first charge accumulation unit 66, and the second charge accumulation unit 67 in the previous frame. When the first difference is SN1, and the second difference is SN2, SN1 = S1-N1 and SN2 = S2-N2A.

  As described above, in the processing example 2, the CDS process for removing the fixed pattern noise unique to the pixel such as the reset noise and the threshold variation of the amplification transistor in the pixel is performed on the signals S2 and N2 output later. In the case of this processing example 2, although a storage means such as a frame memory is required, there is an advantage that the reset noise can be greatly suppressed as compared with the processing example 1.

(Processing example 3)
Next, arithmetic processing in the signal processing unit 18 will be described. First, when the first difference falls within a predetermined range, the ratio of the first difference and the second difference is set for each pixel, for each of a plurality of pixels, for each color, and for each specific pixel in the shared pixel unit. Alternatively, the gain table is generated by calculating the gain uniformly for all pixels. Then, the product of the second difference and the gain table is calculated as the calculated value of the second difference.

Here, assuming that the first difference is SN1, the second difference is SN2, the gain is G, and the calculated value of the second difference SN2 is SN2 ′, the gain G based on the following equations (6) and (7), And the operation value SN2 ′ of the second difference SN2 can be obtained.
G = SN1 / SN2
= (Cfd + Cgs + Ccap) / Cfd (6)
SN2 ′ = G × SN2 (7)
Here, Cfd is a capacitance value of the FD unit 71, Cgs is a capacitance value of the first charge storage unit 66, and Ccap is a capacitance value of the second charge storage unit 67. The gain G is equivalent to the capacity ratio.

  FIG. 26 shows the relationship between the first difference SN1, the second difference SN2, and the calculated value SN2 ′ of the second difference SN2 with respect to the incident light amount.

  Next, as shown in FIG. 27A, a predetermined threshold value Vt set in advance is used. The predetermined threshold Vt is set in advance in a region where the first difference SN1 is not saturated and the optical response characteristic is linear in the optical response characteristic.

  When the first difference SN1 does not exceed the predetermined threshold value Vt, the first difference SN1 is output as the pixel signal SN of the processing target pixel. That is, when SN1 <Vt, SN = SN1 (substitute SN1 for SN). When the first difference SN1 exceeds the predetermined threshold value Vt, the calculated value SN2 ′ of the second difference SN2 is output as the pixel signal SN of the processing target pixel. That is, when Vt ≦ SN1, SN = SN2 ′ (substitute SN2 ′ for SN).

(Processing example 4)
In the next calculation process, as shown in FIG. 27B, the first difference SN1 is within a predetermined range, and the value of the first difference SN1 and the calculation value SN2 ′ of the second difference SN2 are set at a preset ratio. Combined and output as a pixel signal SN.

  For example, in the range before and after the predetermined threshold value Vt as a reference, the composite ratio of the calculated value SN2 ′ of the first difference SN1 and the second difference SN2 is changed stepwise as follows. As described above, the predetermined threshold value Vt is a value set in advance in a region where the first difference SN1 is not saturated and the optical response characteristic is linear in the optical response characteristic.

When SN1 <SN1 × 0.90, SN = SN1
When Vt × 0.90 ≦ SN1 <Vt × 0.94,
SN = 0.9 × SN1 + 0.1 × SN2 ′
When Vt × 0.94 ≦ SN1 <Vt × 0.98,
SN = 0.7 × SN1 + 0.3 × SN2 ′
When Vt × 0.98 ≦ SN1 <Vt × 1.02,
SN = 0.5 × SN1 + 0.5 × SN2 ′
When Vt × 1.02 ≦ SN1 <Vt × 1.06,
SN = 0.3 × SN1 + 0.7 × SN2 ′
When Vt × 1.06 ≦ SN1 <Vt × 1.10.
SN = 0.1 × SN1 + 0.9 × SN2 ′
When Vt × 1.10 ≦ SN1, SN = SN2 ′

  By performing such arithmetic processing, it is possible to switch more smoothly from a signal at low illuminance to a signal at high illuminance.

<5. Reference example>
In the embodiment described above, two charge storage units 66 and 67 are provided in a unit pixel, and the second charge storage unit 67 is a capacitor having a larger capacitance value per unit area than the first charge storage unit 66. The main feature is. However, even if the capacitance values per unit area of the two charge storage units 66 and 67 are equal, an effect that the dynamic range can be expanded can be obtained. This will be described with reference to FIG.

  Within the exposure period of the photodiode 61, the second transfer gate unit 63 is turned on during a period set at a predetermined ratio with respect to the exposure period of the photodiode 61, thereby causing the photodiode 61 to overflow a predetermined amount or more. To discharge the photo charge.

  Here, an exposure period in the photodiode 61 is Tpd, and a period in which the photocharge overflowing from the photodiode 61 is accumulated in the second charge accumulation unit 67 is Tcap. The unit pixel is operated according to the timing chart shown in FIG. 28, and the exposure period Tcap in the second charge storage unit 67 is limited. By this operation, information on the high illuminance side can be compressed, and the dynamic range can be expanded even if the capacitance value of the second charge storage unit 67 is as small as that of the first charge storage unit 66.

  After reading out the noise component and the signal component at the time of low illuminance, the FD unit 71 is reset once, and the photocharge overflowing from the photodiode 61 accumulated in the second charge accumulation unit 67 is used as a signal on the high illuminance side. read out. Unlike the other embodiments, the signal on the high illuminance side once resets the FD unit 71 does not include the photocharge accumulated in the first charge accumulation unit 66.

At the time of signal reading, the voltage signal based on the photocharge transferred to the FD unit 71 is S1, the voltage signal based on the reset level before the photocharge is transferred to the FD unit 71 is N1, and the first difference is SN1. . In addition, a voltage signal based on the photocharges accumulated in the FD unit 71, the first charge storage unit 66, and the second charge storage unit 67 when the FD unit 71 is reset immediately before reading is represented by S3. Further, the voltage signal of the reset level or reset equivalent level of the FD unit 71, the first charge storage unit 66, and the second charge storage unit 67 is N2, the third difference is SN3, the gain is G, the third The calculated value of the difference SN3 is SN3 ′. Then, it can be calculated as follows.
SN1 = S1-N1
SN3 = S3-N2
G = SN1 / SN3
= (Cfd + Csg + Ccap) / Cfd
SN3 ′ = G × SN3 × Tpd / Tcap

In the optical response characteristic, when the first threshold value SN1 is saturated and the predetermined threshold value set in advance in the linear region of the optical response characteristic is Vt and the pixel signal of the pixel to be processed is SN, the pixel signal is as follows: Output SN.
When SN1 <Vt, SN = SN1 (substitute SN1 for SN)
When Vt ≦ SN1, SN = SN3 ′ (substitute SN3 ′ for SN)

<6. Modification>
[6-1. Example of accumulating photocharge only with photodiode 61]
In the above embodiments and modifications, the photoelectric charge overflowing from the photodiode 61 at high illuminance is accumulated in the first accumulated charge portion 66 through the overflow path of the first transfer gate portion 62, and the third The charge is accumulated in the second charge accumulation section 67 through the overflow path of the transfer gate section 64. That is, the feature of this embodiment is that photocharge overflowing from the photodiode 61 at high illuminance is accumulated in the photodiode 61, and in addition to the photodiode 61, the first and second accumulated charge portions 66 and 67 are also accumulated.

  However, in the pixel configuration described above, as is apparent from the operation explanatory diagram of FIG. 29A, exposure cannot be performed during the readout period of photocharge. In view of this, a pixel configuration in which photoelectric charges are stored only by the photodiode 61 is proposed as a modified example.

  Even in this case, there is no change in the gist of the present technology in which the photocharges read from the photodiode 61 are stored separately using the first charge storage unit 66 and the second charge storage unit 67. That is, after the photocharge is read from the photodiode 61, the photocharge overflowing from the first charge accumulation unit 66 is accumulated in the second charge accumulation unit 67. For this purpose, it is needless to say that an overflow path is required between the first charge storage unit 66 and the second charge storage unit 67.

  In this manner, by adopting a pixel configuration in which the photocharge is accumulated only by the photodiode 61, as shown in the operation explanatory diagram of FIG. 29B, exposure can be performed during the readout period of the photocharge. It is possible to realize a seamless operation without a continuous exposure period. However, since the photocharge is accumulated only by the photodiode 61, the dynamic range is limited by the saturation charge amount of the photodiode 61. Therefore, a large dynamic range cannot be expected.

  However, the total area of the charge storage unit that stores the photocharge is reduced by storing the photocharge by using the first charge storage unit 66 and the second charge storage unit 67, which is the gist of the present technology. be able to. Therefore, since the area of the photodiode 61 can be increased by the amount that can reduce the total area, the dynamic range can be indirectly increased.

[6-2. Example of switching circuit operation between short exposure and long exposure]
As described above, the second charge storage unit 67 has high capacity area efficiency, but has a large leakage current. Then, since the photocharge is accumulated in the second charge accumulating portion 67 even during the exposure period, the deterioration of the image quality due to the leakage current increases as the exposure period becomes longer.

  Therefore, for example, the circuit operation of the unit pixel may be switched between when the exposure time is short and when the exposure time is long. Specifically, the above-described circuit operation is performed during short-time exposure. On the other hand, during long exposure, the photodiode 61 and the first charge are not accumulated in the second charge accumulation unit 67 by, for example, periodically reading out the accumulated photocharge during the exposure period. Photocharges may be stored only in the storage unit 66.

(Configuration example for realizing circuit operation during long exposure)
FIG. 30 shows a configuration example around the column processing unit 13, the signal processing unit 18, and the data storage unit 19 for realizing a circuit operation during long exposure.

  A switch 101 is provided between the column processing unit 13, the signal processing unit 18, and the data storage unit 19. By switching the state of the switch 101, the supply destination of the pixel signal output from the column processing unit 13 can be switched to either the signal processing unit 18 or the data storage unit 19.

  The signal processing unit 18 is configured to include memories 111a and 111b, an adding unit 112, and other signal processing units 113.

  The memory 111 a stores the pixel signal supplied from the data storage unit 19, and the memory 111 b stores the pixel signal supplied from the column processing unit 13 via the switch 101. The adder 112 adds the pixel signal stored in the memory 111 a and the pixel signal stored in the memory 111 b and supplies the added pixel signal to the data storage unit 19.

  The memories 111a and 111b only need to have a capacity capable of holding a pixel signal for at least one pixel. For example, the memories 111a and 111b are set to have a capacity capable of holding a pixel signal for one line.

  The other signal processing unit 113 performs various other signal processing on the pixel signal stored in the data storage unit 19.

(Example of circuit operation during long exposure of unit pixel 60A)
Next, an example of the circuit operation of the unit pixel 60A during long exposure will be described with reference to the timing charts of FIGS. 31 and 32 and the potential diagrams of FIGS.

FIG. 31 is a timing chart of the selection signal SEL, reset signal RST, transfer signal TG, charge discharge control signal PG, transfer signal CG, transfer signal SG, and transfer signal FG of the unit pixel 60A during long exposure. Show. FIG. 32 shows a detailed timing chart of a period surrounded by a dashed-dotted line in FIG. Further, FIGS. 33 to 36 respectively show the state of the potential of the unit pixel 60A of the N-th row at time Ta to Td ₁ of Figure 32.

  Note that the circuit operation in the period surrounded by the one-dot chain line in FIGS. 31 and 32, that is, the period from the time t2 to the time t3, differs between the short-time exposure and the long-time exposure. Hereinafter, circuit operation during this period will be described.

Figure 33 shows the state of the potential of the unit pixel 60A at time Ta between time t2 and time T1 _1. In this way, photocharge is accumulated in the photodiode 61. In the case of high illuminance, the photocharge overflowing from the photodiode 61 is accumulated in the first charge accumulation unit 66 through the overflow path of the first transfer gate unit 62. In the case of low illuminance, photocharge is stored only by the photodiode 61.

At time T1 _1, the N-th row of the selection signal SEL is changed to an active state, the N-th row of the selection transistor 69 is turned on, the unit pixel 60A of the N-th row is selected. At the same time, the reset signal RST becomes active and the reset gate unit 65 becomes conductive, whereby the FD unit 71 is reset. Then, at time T2 _1, the reset signal RST is placed into an inactive state.

Then, during the time T2 ₁ and the time T3 _1, the potential of the FD portion 71 as a reset level NL1, is output to the vertical signal line 17 through the amplification transistor 68 and selection transistor 69.

Next, at time T3 _1, transfer signal TG, the transfer signal SG and transfer signal FG becomes active state, the first transfer gate portion 62, the gate electrode 661 of the first charge accumulation portion 66, and, in the second The transfer gate unit 63 becomes conductive.

Figure 34 is a diagram showing the potential state of the unit pixel 60A at time Tb ₁ between times T3 ₁ and the time T4 _1. Thus, the transfer with the potential of the FD portion 71 and the first charge accumulation portion 66 are coupled, during the period from time t2 to time T3 ₁ photocharge accumulated in the photodiode 61, the combined area Is done. Further, the light charge generated by the photodiode 61 during the time T3 ₁ and the time T4 ₁ also transferred to the bonded area.

The time from time t2 to time T3 _1, the amount of accumulated charge is set so as not to exceed the sum of the photodiode 61 the saturation charge amount of the first charge accumulation portion 66. Therefore, during this period, photocharges may overflow from the photodiode 61 and may be accumulated in the first charge accumulation unit 66 via the overflow path of the first transfer gate unit 62. The photocharge overflows from the charge storage section 66 and is not stored in the second charge storage section 67 via the overflow path of the third transfer gate section 64.

Next, at time T4 _1, transfer signal TG, and the transfer signal SG becomes inactive state, the gate electrode 661 of the first transfer gate portion 62 and the first charge accumulation portion 66 is nonconducting. Then, the charge transfer to the photodiode 61 is resumed when the first transfer gate portion 62 is turned off.

Figure 35 is a diagram showing the potential state of the unit pixel 60A at time Tc ₁ between times T4 ₁ and the time T5 _1. As described above, all the photocharges transferred from the photodiode 61 to the region where the potentials of the FD unit 71 and the first charge storage unit 66 are combined are transferred to the FD unit 71.

Then, at time T5 _1, the transfer signal FG becomes inactive state, the second transfer gate portion 63 is nonconducting.

Figure 36 is a diagram showing a state of a potential of a unit pixel 60A at time Td ₁ between times T5 ₁ and the time T6 _1. The potential of the FD portion 71 in this state, as the signal level SL1 corresponding to the accumulated charge amount of the photodiode 61 and the first charge accumulation portion 66 in the period from time t2 to time T4 _1, the amplification transistor 68 and selection transistor 69 To the vertical signal line 17.

  The column processing unit 13 calculates a difference between the signal level SL1 and the signal level NL1. Then, the column processing unit 13 supplies the difference value SNL1 (= SL1-NL1) to the data storage unit 19 via the switch 101 and holds it.

Then, at time T6 _1, the selection signal SEL becomes inactive state, that N-th row of the selection transistor 69 becomes non-conducting state, the unit pixel 60A of the N-th row is non-selected state.

  These processes are performed for each row, and as a result, the image data including the difference value SNL1 of each pixel is held in the data storage unit 19.

Next, at time T1 ₂ to T6 _2, times T1 ₁ to T6 ₁ and a similar operation is performed, the reset level NL2, the order of the signal level SL2, is output to the vertical signal line 17 through the amplification transistor 68 and selection transistor 69 The

The time from the time T4 ₁ which photocharge in the photodiode 61 is accumulated up to a time T3 _2, similarly time from time t2 to time T3 _1, the accumulated charge amount between the photodiode 61 the first charge accumulation It is set so as not to exceed the total saturation charge amount of the portion 66.

  The column processing unit 13 takes a difference between the signal level SL2 and the signal level NL2. Then, the column processing unit 13 supplies the difference value SNL2 (= SL2-NL2) to the memory 111b via the switch 101 and holds it.

  On the other hand, the data storage unit 19 supplies the difference value SNL1 of the corresponding unit pixel 60A to the memory 111a and holds it. The adding unit 112 adds the difference value SNL1 held in the memory 111a and the difference value SNL2 held in the memory 111b, and causes the data storage unit 19 to hold the integrated value SNLa.

  These processes are performed for each row, and as a result, the image data including the integrated value SNLa of each pixel is held in the data storage unit 19.

Next, at times T1 _{3 to} T6 ₃ , operations similar to those at times T1 _{1 to} T6 ₁ are performed, and are output to the vertical signal line 17 through the amplification transistor 68 and the selection transistor 69 in the order of the reset level NL3 and the signal level SL3. The

The time from the time T4 ₂ light charges are accumulated in the photodiode 61 until time T3 _3, similarly time from time t2 to time T3 _1, the accumulated charge amount between the photodiode 61 the first charge accumulation It is set so as not to exceed the total saturation charge amount of the portion 66.

  The column processing unit 13 calculates a difference between the signal level SL3 and the signal level NL3. Then, the column processing unit 13 supplies the difference value SNL3 (= SL3-NL3) to the memory 111b via the switch 101 and holds it.

  On the other hand, the data storage unit 19 supplies the integrated value SNLa of the corresponding unit pixel 60A to the memory 111a and holds it. The adding unit 112 adds the integrated value SNLa held in the memory 111a and the difference value SNL3 held in the memory 111b, and causes the data storage unit 19 to hold the integrated value SNLa.

  These processes are performed for each row, and as a result, the image data including the integrated value SNLa of each pixel is held in the data storage unit 19.

Thereafter, similar processing is performed at times T1 _{4 to} T6 _n . That is, during the entire pixel exposure period, the accumulated charge amount is accumulated in the pixel unit 60A at a time interval that does not exceed the sum of the saturated charge amounts of the photodiode 61 and the first charge accumulation unit 66 while the exposure is continued. Intermediate readout is performed n times to output the photocharge amount as an electrical signal (pixel signal), and an integrated value SNLa corresponding to the accumulated charge amount for each pixel is obtained.

  Further, from time t3 to t12, the same operation as that for short-time exposure is performed. As a result, the reset level N1, the first signal level S1, the second signal level S2, and the reset level N2 are output to the vertical signal line 17 through the amplification transistor 68 and the selection transistor 69 in this order.

  A pixel signal of each pixel is generated based on the integrated value SNLa held in the data storage unit 19 and the signal levels S1 and S2 and the reset levels N1 and N2.

(Modification of circuit operation during long exposure of unit pixel 60A)
FIG. 37 shows a modification of the detailed timing chart in the period surrounded by the dashed-dotted line in FIG.

  The timing chart of FIG. 37 is different from the timing chart of FIG. 32 described above in that the transfer signal SG is not in the active state but remains in the inactive state during the period from time t2 to time t3. . That is, when the photocharge accumulated in the photodiode 61 is transferred to the FD portion 71 via the first charge accumulation portion 66, the gate electrode 661 of the first charge accumulation portion 66 remains in a non-conductive state. It becomes.

  When the potential at the time of depletion of the photodiode 61 is sufficiently shallower than the potential at the time of depletion of the first charge storage unit 66, such an operation can be performed.

(Example of circuit operation during long exposure of unit pixel 60A2)
FIGS. 38 and 39 are timing charts showing circuit operations during long exposure of the unit pixel 60A2 (FIG. 20) according to the second modification of the unit pixel 60A. FIG. 39 shows a detailed timing chart of a period surrounded by a dashed-dotted line in FIG.

  The timing chart of FIG. 39 is similar to the timing chart of FIG. 37 in that the transfer signal SG is not in the active state but remains in the inactive state during the all-pixel common exposure period. Is different.

(Timing for switching circuit operation during short exposure and circuit operation during long exposure)
Here, the switching timing of the circuit operation during the short exposure and the circuit operation during the long exposure will be considered.

  In order not to reduce the dynamic range due to the circuit operation during long exposure, the number n (natural number) of intermediate reading during the exposure period must be set so as to satisfy the following conditional expression (8).

  Qs ≦ Qm × n (8)

  Here, Qs is the saturation charge amount of the unit pixel 60A in the circuit operation at the time of short-time exposure, and Qm is the maximum charge amount that can be read from the unit pixel 60A by one intermediate reading. That is, it is necessary to set the number n of intermediate readings so that the amount of photocharge that can be read from the unit pixel 60A by repeating the intermediate reading n times is equal to or greater than the saturation charge amount Qs of the unit pixel 60A.

  The following expression (9) is a modification of expression (8).

  n ≧ Qs / Qm (9)

  The saturation charge amount Qs and the maximum charge amount Qm are both determined by the device characteristics of the CMOS image sensor 10 including the unit pixel 60A. As a result, the condition of the intermediate read number n is determined by the equation (9), and the intermediate read number n can be set in advance within the range of the obtained condition.

  On the other hand, assuming that the exposure time of the imaging apparatus including the CMOS image sensor 10 is Te and the required time for intermediate reading for one frame is Tm, the exposure time Te, the required time Tm, and the number of intermediate readings n are expressed by the following conditional expression ( 10) must be satisfied.

  Tm ≦ Te / n (10)

  Therefore, when the exposure time Te satisfies the following expression (11), it is possible to switch to the circuit operation during long exposure.

  Te ≧ n × Tm (11)

  Based on whether the exposure time Te satisfies the conditional expression (11), for example, the drive unit of the CMOS image sensor 10 automatically switches the circuit operation during the short exposure and the long exposure. May be. Alternatively, when the exposure time Te does not satisfy the conditional expression (11), it may be fixed by a circuit operation at the time of short-time exposure, and when the conditional expression (11) is satisfied, it may be switched by a user operation. .

  As described above, in the circuit operation during the long-time exposure, the photocharge is accumulated and read out without accumulating the photocharge in the second charge accumulation unit 67 having a large leakage current and without overflowing the photocharge. Is done. Therefore, for example, by switching the circuit operation of the unit pixel according to the exposure time, it is possible to obtain an image with a wide dynamic range and less noise regardless of the exposure period.

  In addition, although the case where a dynamic range falls is also assumed, you may enable it to switch the circuit operation | movement at the time of short time exposure and long time exposure by user operation irrespective of exposure time Te.

[6-3. Example in which second charge storage unit 67 is omitted]
It is also possible to delete the second charge accumulation unit 67 from the unit pixel and use the FD unit 71 as the second charge accumulation unit. That is, it is possible to transfer the photocharges overflowing from the first charge accumulation unit 66 to the FD unit 71 for accumulation.

(Circuit configuration of unit pixel 60B)
FIG. 40 is a circuit diagram showing a circuit configuration of a unit pixel 60B in which the second charge accumulation unit 67 is omitted. As shown in FIG. 40, the unit pixel 60B has, for example, a PN junction photodiode 61 as a photoelectric conversion unit that receives light to generate and accumulate photocharges, similarly to the unit pixel 60A. . The photodiode 61 generates and accumulates photocharges corresponding to the received light quantity.

  The unit pixel 60B further includes, for example, a first transfer gate unit 62, a second transfer gate unit 63, a reset gate unit 65, a first charge storage unit 66, an amplification transistor 68, a selection transistor 69, and a charge discharge gate. Part 70.

  In the unit pixel 60B having the above configuration, the first charge accumulation unit 66 corresponds to the first charge accumulation unit described above. That is, the first charge storage unit 66 is configured by an embedded MOS capacitor.

For the unit pixel 60B, a plurality of drive lines are wired, for example, for each pixel row as the pixel drive lines 16 in FIG. Various drive signals TG / SG, FG, RST, SEL, and PG are supplied from the vertical drive unit 12 of FIG. 1 through a plurality of drive lines of the pixel drive line 16. These drive signals TG / SG, FG, RST, SEL, and PG are in the above configuration because each transistor is an NMOS transistor, so that the high level (for example, power supply voltage V _DD ) is in an active state, and the low level is low. This is a pulse signal in which a level state (for example, a negative potential) becomes an inactive state.

  The drive signal TG / SG is applied as a transfer signal to the gate electrode of the first transfer gate unit 62. In the first transfer gate portion 62, one source / drain region is connected to the photodiode 61 in terms of a circuit. Then, the first transfer gate unit 62 is turned on in response to the drive signal TG / SG becoming active, so that the photocharge stored in the photodiode 61 is transferred to the first charge storage unit. 66. The photocharge transferred by the first transfer gate unit 62 is temporarily stored in the first charge storage unit 66.

  The drive signal FG is applied as a transfer signal to the gate electrode of the second transfer gate unit 63. The second transfer gate unit 63 is connected in circuit between the first charge storage unit 66 and the FD unit 71 to which the gate electrode of the amplification transistor 68 is connected. The FD unit 71 converts the photoelectric charge into an electric signal, for example, a voltage signal, and outputs it. Then, when the drive signal FG becomes active, the second transfer gate portion 63 becomes conductive in response to the photocharge accumulated in the first charge accumulation portion 66 to the FD portion 71. Forward.

The drive signal RST is applied as a reset signal to the gate electrode of the reset gate unit 65. In the reset gate portion 65, one source / drain region is connected to the reset voltage _VDR and the other source / drain region is connected to the FD portion 71 in terms of a circuit. Then, when the drive signal RST becomes active, the reset gate unit 65 is turned on in response to resetting the potential of the FD unit 71 to the level of the reset voltage _VDR .

The amplification transistor 68 has a circuit in which a gate electrode is connected to the FD unit 71 and a drain electrode is connected to the power supply voltage V _DD , and is a readout circuit that reads out photoelectric charges obtained by photoelectric conversion in the photodiode 61, so-called It becomes the input part of the source follower circuit. That is, the amplification transistor 68 forms a source follower circuit with a constant current source 80 connected to one end of the vertical signal line 17 by connecting the source electrode to the vertical signal line 17 through the selection transistor 69.

  The drive signal SEL is applied as a selection signal to the gate electrode of the selection transistor 69. The selection transistor 69 is connected in circuit between the source electrode of the amplification transistor 68 and the vertical signal line 17. Then, the selection transistor 69 becomes conductive in response to the drive signal SEL becoming active, and connects the pixel signal output from the amplification transistor 68 to the vertical signal line 17 with the unit pixel 60A selected.

The drive signal PG is applied as a charge discharge control signal to the gate electrode of the charge discharge gate unit 70. The charge discharge gate unit 70 is connected between the photodiode 61 and the charge discharge unit (for example, the power supply voltage V _DD ) in circuit. Then, when the drive signal PG becomes active, the charge discharge gate unit 70 becomes conductive, and charges a predetermined amount from the photodiode 61 or all photocharges accumulated in the photodiode 61. Selectively discharge to the discharge section.

  The charge discharge gate unit 70 is provided for the following purpose. That is, by making the charge discharge gate unit 70 conductive during a period in which photocharge accumulation is not performed, the photodiode 61 is saturated with photocharge, and the charge exceeding the saturation charge amount is in the first charge accumulation unit 66. This is to avoid overflowing to the FD portion 71 and peripheral pixels.

(Pixel structure of unit pixel 60B)
FIG. 41 is a schematic diagram showing the pixel structure of the unit pixel 60B. In FIG. 41, the same parts as those in FIG. 40 are denoted by the same reference numerals. FIG. 41 shows a plane pattern showing the pixel layout, a cross section taken along the line AA ′, and a cross section taken along the line BB ′ in the plane pattern.

  41, the photodiode (PD) 61 has a PN junction in which an N-type semiconductor region 611 is formed in a P-type well 52 on a semiconductor substrate 51. It has a diode configuration. The photodiode 61 is a buried photodiode (so-called HAD (Hole Accumulation Diode) sensor structure) in which a depletion end is separated from the interface by forming a P-type semiconductor region 612 in the surface layer portion thereof.

  The first transfer gate portion 62 has a gate electrode 621 disposed on a substrate surface via a gate insulating film (not shown), and a P − type semiconductor region 622 formed on the substrate surface layer portion. It has become. The P − type semiconductor region 622 slightly deepens the potential below the gate electrode 621 as compared to the case where the semiconductor region 622 is not formed. As a result, as is clear from the cross-sectional view taken along the line B-B ′, the P− type semiconductor region 622 has a predetermined amount or more of photocharges overflowing from the photodiode 61, specifically, the saturation charge amount of the photodiode 61. An overflow path is formed to transfer photocharges exceeding 1 to the first charge storage section 66.

  Further, the gate electrode 621 of the first transfer gate unit 62 also serves as the gate electrode 661 of the first charge storage unit 66. In other words, the gate electrode 621 of the first transfer gate unit 62 and the gate electrode 661 of the first charge storage unit 66 are integrally formed.

  The first charge storage unit 66 includes a gate electrode 661 that also serves as the gate electrode 621 of the first transfer gate unit 62, and is formed as an embedded MOS capacitor under the gate electrode 661. That is, the first charge storage portion 66 includes an N-type semiconductor region 662 formed in the P-type well 52 below the gate electrode 661 and a P-type semiconductor region 623 formed in the surface layer portion. An embedded MOS capacitor is used.

  The second transfer gate portion 63 has a gate electrode 631 disposed on the substrate surface via a gate insulating film (not shown). The second transfer gate unit 63 uses the N-type semiconductor region 662 of the first charge storage unit 66 as one source / drain region and the N + type semiconductor region 711 serving as the FD unit 71 as the other source / drain region. .

  The second transfer gate unit 63 and the gate electrode 661 of the first charge storage unit 66 function to couple or divide the potentials of the FD unit 71 and the first charge storage unit 66.

  The second transfer gate portion 63 has a structure in which an N − type semiconductor region 632 is formed in the surface layer portion of the channel portion. The N − type semiconductor region 632 makes the potential below the gate electrode 631 slightly deeper than when the semiconductor region 632 is not formed. As a result, as is clear from the cross-sectional view taken along the line AA ′, the N − type semiconductor region 632 has a predetermined amount or more of photocharges overflowing from the first charge accumulation portion 66, specifically, the first An overflow path for transferring photocharges equal to or greater than the saturation charge amount of the charge storage unit 66 to the FD unit 71 is formed.

  Here, regarding the overflow path formed under the first and second transfer gate portions 62 and 63, the photocharge accumulated in the first accumulated charge portion 66 does not leak into the photodiode 61. It is important that it is formed so as to be transferred to the FD portion 71.

  As described above, the unit pixel 60B has an overflow path below the gate electrode 631 of the second transfer gate portion 63, so that the photocharge overflowing from the photodiode 61 at high illuminance is also accumulated in the FD portion 71. Can do. Specifically, even when the second transfer gate unit 63 is in a non-conducting state, a predetermined amount or more of the photocharge overflowing from the first charge storage unit 66 is transferred to the FD unit 71 and stored in the FD unit 71. Can do. Thereby, the saturation charge amount of the first charge storage unit can be set smaller than the saturation charge amount of the photodiode 61.

(Circuit operation of unit pixel 60B)
Next, the circuit operation of the unit pixel 60B will be described with reference to the timing chart of FIG. 42 and the potential diagrams of FIGS.

  FIG. 42 shows a timing chart of the selection signal SEL, the reset signal RST, the transfer signal TG / SG, the charge discharge control signal PG, and the transfer signal FG for the unit pixel 60B. 43 to 50 show the state of the potential of the unit pixel 60B in the Nth row at times ta to tg in the timing chart of FIG. 42, respectively.

  First, at time t61, the charge discharge control signal PG remains in the active state, and the selection signal SEL, the reset signal RST, and the transfer signal FG are simultaneously in the active state for all the pixels. As a result, the select transistor 69, the reset gate unit 65, the second transfer gate unit 63, and the charge discharge gate unit 70 become conductive.

  FIG. 43 shows the potential state of the unit pixel 60B at time ta between time t61 and time t62. As described above, the potentials of the FD unit 71 and the first charge storage unit 66 are coupled, and the coupled region is reset.

  Thereafter, all the pixels simultaneously become inactive in the order of the transfer signal FG, the reset signal RST, and the selection signal SEL. At time t62, the charge discharge control signal PG becomes inactive at the same time for all the pixels. As a result, an exposure period common to all pixels is entered.

  FIG. 44 shows the potential state of the unit pixel 60B at time t62. At this time, no photocharge is accumulated in the photodiode 61 and the first charge accumulation section 66.

  FIG. 45 shows the potential state of the unit pixel 60B at time tb between time t62 and time t63. As described above, the photocharge is accumulated in the photodiode 61 and, at the time of high illuminance, the photocharge overflowing from the photodiode 61 passes through the overflow path of the first transfer gate portion 62 and becomes the first charge. Accumulated in the accumulation unit 66. Further, when the first charge accumulation unit 66 is saturated, the photocharge overflowing from the first charge accumulation unit 66 is accumulated in the FD unit 71 via the overflow path of the second transfer gate unit 63. In the case of low illuminance, photocharge is stored only by the photodiode 61.

  Next, at time t63, the transfer signal TG / SG becomes active, and the first transfer gate portion 62 and the gate electrode 661 of the first charge accumulation portion 66 become conductive.

  FIG. 46 shows the potential state of the unit pixel 60B at time tc between time t63 and time t64. As described above, the photocharge accumulated in the photodiode 61 is transferred to the first charge accumulation unit 66 and accumulated in the first charge accumulation unit 66.

  Next, at time t64, the transfer signal TG / SG simultaneously becomes inactive at the same time for all pixels, and at the same time, the charge discharge control signal PG becomes active. Then, the first transfer gate unit 62 and the gate electrode 661 of the first charge storage unit 66 are turned off, the potential of the first charge storage unit 66 is restored, and the charge discharge gate unit 70 is turned on. become. Thereby, the exposure period common to all pixels ends. Further, when the accumulated charge amount of the first charge accumulation unit 66 exceeds the saturation charge amount, the photocharge overflowing from the first charge accumulation unit 66 passes through the overflow path of the second transfer gate unit 63. Are stored in the FD unit 71.

  Then, after the exposure period common to all the pixels is completed, reading of the photocharges accumulated one by one in order is performed.

  Specifically, at time t65, the selection signal SEL in the Nth row is activated and the selection transistor 69 in the Nth row is turned on, so that the unit pixel 60A in the Nth row is selected.

  FIG. 47 shows the potential state of the unit pixel 60B at time td between time t65 and time t66. In this state, the potential of the FD unit 71 is set to the vertical signal line 17 through the amplification transistor 68 and the selection transistor 69 as the first signal level S1 corresponding to the charge amount exceeding the saturation charge amount of the first charge storage unit 66. Is output.

  Next, at time t66, the reset signal RST becomes active, and the reset gate unit 65 becomes conductive. As a result, the FD unit 71 is reset. At time t67, the reset signal RST becomes inactive and the reset gate unit 65 becomes non-conductive.

  FIG. 48 shows the potential state of the unit pixel 60B at time te between time t67 and time t68. The potential of the FD unit 71 in this state is output to the vertical signal line 17 through the amplification transistor 68 and the selection transistor 69 as the reset level N1.

  Next, at time t68, the transfer signal FG becomes active, and the second transfer gate 63 becomes conductive.

  FIG. 49 shows the potential state of the unit pixel 60B at time tf between time t68 and time t69. In this way, the potentials of the FD unit 71 and the first charge storage unit 66 are coupled, and photocharge is transferred from the first charge storage unit 66 to the FD unit 71.

  Next, at time t69, the transfer signal FG becomes inactive, and the second transfer gate unit 63 becomes non-conductive.

  FIG. 50 shows the potential state of the unit pixel 60B at time tg between time t69 and time t70. The potential of the FD unit 71 in this state is output to the vertical signal line 17 through the amplification transistor 68 and the selection transistor 69 as the second signal level S2 corresponding to the amount of stored charge in the first charge storage unit 66.

  Next, at time t70, the selection signal SEL in the N-th row becomes inactive, and the selection transistor 69 in the N-th row becomes non-conductive, so that the unit pixel 60A in the N-th row becomes non-selected. .

  Through the series of circuit operations described above, the first signal level S1, the reset level N1, and the second signal level S2 are sequentially output from the unit pixel 60B to the vertical signal line 17.

  For example, the column processing unit 13 performs noise removal processing by taking the difference between the first signal level S1 and the reset level N1 and the difference between the reset level N1 and the second signal level S2. . At this time, for example, when the difference between the first signal level S1 and the reset level N1 is taken, the reset level N1 of the previous frame may be used.

  As described above, according to the unit pixel 60B, by omitting the second charge storage unit 67, the area of the photodiode 61 can be increased, and the saturation charge amount of the photodiode 61 can be secured more. Alternatively, the area of the first charge storage section 66 can be increased, and a larger amount of saturation charge can be secured in the first charge storage section 66. On the contrary, if the saturation charge amount is equal, the unit pixel size can be reduced by the amount that can save space.

  In addition, when all the pixels are read simultaneously, the photocharge at the time of low illuminance is accumulated in the first charge accumulation unit 66 having good characteristics at the time of darkness, while the photocharge at the time of high illuminance is poor in the characteristics at darkness. Accumulated in. Therefore, the image quality of the captured image at the time of darkness or low illuminance does not deteriorate as compared with the prior art that realizes global exposure.

(Circuit operation during long exposure of the unit pixel 60B)
In the unit pixel 60B, the circuit operation at the time of long exposure similar to that of the unit pixel 60A can be realized. That is, during long exposure, the accumulated photocharge is periodically read out during the exposure period, so that only the photodiode 61 and the first charge accumulation unit 66 do not accumulate the photocharge in the FD unit 71. Photocharge can be accumulated.

  Here, the circuit operation of the unit pixel 60B during long-time exposure will be described with reference to the timing charts of FIGS. 51 and 52 and the potential diagrams of FIGS.

FIG. 51 shows a timing chart of the selection signal SEL, the reset signal RST, the transfer signal TG / SG, the charge discharge control signal PG, and the transfer signal FG for the unit pixel 60B. FIG. 52 shows a detailed timing chart of a period surrounded by a dashed-dotted line in FIG. Further, FIG. 53 through FIG. 56 shows a state of the potential of the unit pixel 60B at time Ta to Td ₁ of Figure 52, respectively.

  Note that the circuit operation in the period surrounded by the one-dot chain line in FIGS. 51 and 52, that is, the period from time t62 to time t63, differs between the short exposure and the long exposure. Hereinafter, circuit operation during this period will be described.

Figure 52 shows the state of the potential of the unit pixel 60B at time Ta between time t62 and time T61 _1.

At time T61 _1, the N-th row of the selection signal SEL is changed to an active state, the N-th row of the selection transistor 69 is turned on, the unit pixel 60A of the N-th row is selected. At the same time, the reset signal RST becomes active and the reset gate unit 65 becomes conductive, whereby the FD unit 71 is reset. Then, at time t62 _1, the reset signal RST is placed into an inactive state.

Then, during the time T62 ₁ and the time T63 _1, the potential of the FD portion 71 as a reset level NL1, is output to the vertical signal line 17 through the amplification transistor 68 and selection transistor 69.

Next, at time T63 _1, the transfer signal TG / SG and transfer signal FG becomes active state, the first transfer gate portion 62, the gate electrode 661 of the first charge accumulation portion 66, and a second transfer gate The part 63 becomes conductive.

Figure 54 is a diagram showing the potential state of the unit pixel 60B at time Tb ₁ between times T63 ₁ and the time T64 _1. In this way, the potentials of the FD unit 71 and the first charge storage unit 66 are coupled, and the photocharge accumulated in the photodiode 61 is transferred to the coupled region. Further, the light charge generated by the photodiode 61 during the time T63 ₁ and the time T64 ₁ also transferred to the bonded area.

The time from time t62 to time T63 _1, the amount of accumulated charge is set so as not to exceed the sum of the photodiode 61 the saturation charge amount of the first charge accumulation portion 66. Therefore, during this period, photocharges may overflow from the photodiode 61 and may be accumulated in the first charge accumulation unit 66 via the overflow path of the first transfer gate unit 62. Photocharges overflow from the charge storage unit 66 and are not stored in the FD unit 71 via the overflow path of the second transfer gate unit 63.

Next, at time T64 _1, the transfer signal TG / SG becomes inactive state, the gate electrode 661 of the first transfer gate portion 62 and the first charge accumulation portion 66 is nonconducting. Then, the charge transfer to the photodiode 61 is resumed when the first transfer gate portion 62 is turned off.

Figure 55 is a diagram showing the potential state of the unit pixel 60A at time Tc ₁ between times T64 ₁ and the time T65 _1. As described above, all the photocharges transferred to the region where the potentials of the FD unit 71 and the first charge storage unit 66 are coupled are transferred to the FD unit 71.

Next, at time T65 _1, the transfer signal FG becomes inactive state, the second transfer gate portion 63 is nonconducting.

FIG. 56 is a diagram showing a potential state of the unit pixel 60B at time Td ₁ between time T65 ₁ and time T66 ₁ . In this state, the potential of the FD portion 71 is output to the vertical signal line 17 through the amplification transistor 68 and the selection transistor 69 as the signal level SL2 corresponding to the amount of charge accumulated in the photodiode 61.

Next, at time T66 _1, the selection signal SEL becomes inactive state, that N-th row of the selection transistor 69 becomes non-conducting state, the unit pixel 60A of the N-th row is non-selected state.

Thereafter, at times T61 _{2 to} T66 _n , operations similar to those at times T61 _{1 to} T66 ₁ are repeated n−1 times. As a result, the reset level NL2, the third signal level SL2,..., The reset level NLn, and the signal level SLn are output to the vertical signal line 17 through the amplification transistor 68 and the selection transistor 69.

  As in the case of the unit pixel 60A, each time intermediate reading is performed, an integrated value corresponding to the accumulated charge amount of each pixel is calculated.

  As described above, in the unit pixel 60B as well as the unit pixel 60A, in the circuit operation at the time of long exposure, the photoelectric charge is not accumulated in the FD portion 71 having a large leakage current, and the photoelectric charge is caused to overflow. Instead, photocharge is stored and read out. Therefore, for example, by switching the circuit operation of the unit pixel according to the exposure time, it is possible to obtain an image with a wide dynamic range and less noise regardless of the exposure period.

[6-4. Other variations]
In the above embodiment, the case where the present invention is applied to a CMOS image sensor in which unit pixels are arranged in a matrix has been described as an example. However, the present technology is not limited to application to a CMOS image sensor. That is, the present technology can be applied to all XY address type solid-state imaging devices in which unit pixels are two-dimensionally arranged in a matrix.

  In addition, the present technology is not limited to application to a solid-state imaging device that detects the distribution of the amount of incident light of visible light and captures it as an image, but is a solid that captures the distribution of the incident amount of infrared rays, X-rays, or particles as an image. Applicable to all imaging devices.

  The solid-state imaging device may be formed as a single chip, or may be in a module-like form having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together. Good.

  In addition, all the pixels in the present technology are all the pixels that appear in the image, and dummy pixels and the like are excluded. In this technology, if the time difference and image distortion are small enough not to be a problem, it is possible to scan at a high speed by multiple lines (for example, several tens of lines) instead of the simultaneous operation of all pixels. It is. Furthermore, in the present technology, it is possible to apply the global shutter operation to not only all the pixels appearing in the image but also a predetermined plurality of rows.

  Furthermore, the conductivity type of the device structure in the unit pixel described above is merely an example, and the N type and the P type may be reversed. Note that, depending on whether the majority carrier moving in the unit pixel is a hole or an electron, the magnitude relationship between the potentials or potentials of the above portions may be reversed.

<7. Electronic equipment>
The present technology is not limited to application to a solid-state imaging device, but an imaging device such as a digital still camera or a video camera, a portable terminal device having an imaging function such as a mobile phone, or a solid-state imaging device in an image reading unit. The present invention can be applied to all electronic devices using a solid-state imaging device for an image capturing unit (photoelectric conversion unit) such as a copying machine to be used. Note that the above-described module form mounted on an electronic device, that is, a camera module may be used as an imaging device.

  FIG. 57 is a block diagram illustrating an example of a configuration of an electronic apparatus according to the present technology, for example, an imaging apparatus.

  As shown in FIG. 57, an imaging apparatus 200 according to the present technology includes an optical system including a lens group 201 and the like, an imaging element (imaging device) 202, a DSP circuit 203, a frame memory 204, a display device 205, a recording device 206, an operation, and the like. A system 207 and a power supply system 208 are included. The DSP circuit 203, the frame memory 204, the display device 205, the recording device 206, the operation system 207, and the power supply system 208 are connected to each other via the bus line 209.

  The lens group 201 takes in incident light (image light) from a subject and forms an image on the imaging surface of the imaging element 202. The imaging element 202 converts the amount of incident light imaged on the imaging surface by the lens group 201 into an electrical signal in units of pixels and outputs it as a pixel signal.

  The display device 205 includes a panel type display device such as a liquid crystal display device or an organic EL (electroluminescence) display device, and displays a moving image or a still image captured by the image sensor 202. The recording device 206 records a moving image or a still image captured by the image sensor 202 on a recording medium such as a video tape or a DVD (Digital Versatile Disk).

  The operation system 207 issues operation commands for various functions of the imaging apparatus under operation by the user. The power supply system 208 appropriately supplies various power sources serving as operation power sources for the DSP circuit 203, the frame memory 204, the display device 205, the recording device 206, and the operation system 207 to these supply targets.

  The imaging apparatus having the above-described configuration can be used as an imaging apparatus such as a video camera, a digital still camera, and a camera module for mobile devices such as a mobile phone. And in the said imaging device, the following effects can be obtained by using solid-state imaging devices, such as the CMOS image sensor 10 which concerns on embodiment mentioned above, as the image pick-up element 202. FIG.

  That is, the CMOS image sensor 10 according to the above-described embodiment can realize imaging without distortion by global exposure. Therefore, it can be realized as an imaging device suitable for use in sensing applications that require high-speed imaging of subjects moving at high speed and image synchronization that cannot permit image distortion.

  In addition, the CMOS image sensor 10 according to the above-described embodiment has a higher saturation charge amount without deteriorating the image quality of a captured image in the dark or at low illuminance as compared with the conventional technology that realizes global exposure. A large amount can be secured, in other words, the capacitance value capable of storing photocharges can be increased. If a larger amount of saturated charge can be secured, if the equivalent amount of saturated charge is sufficient, the unit pixel size can be reduced by the amount that can secure a larger amount of saturated charge, and the number of pixels can be increased accordingly. . Therefore, it is possible to improve the image quality of the captured image.

  The present technology is not limited to the above description. The pixel structure, for example, the overflow path and the conductive layer in the surface layer portion of the embedded MOS capacitor is not limited, and various changes can be made to the circuit diagram, timing chart, and the like without departing from the spirit of the present technology.

  For example, this technique can also take the following structures.

(1)
A plurality of unit pixels each including a photoelectric conversion unit that generates and accumulates a photocharge according to the amount of received light, a first charge accumulation unit including a buried MOS capacitor, and a second charge accumulation unit are arranged, A pixel array unit capable of batch exposure of the unit pixels;
Photoelectric charge generated by the photoelectric conversion unit during the exposure period is accumulated in the photoelectric conversion unit, the first charge accumulation unit, and the second accumulation unit, or the photoelectric charge is accumulated during the exposure period. A solid-state imaging device comprising: a drive unit that performs a second drive for accumulating photoelectric charges generated by the conversion unit in the photoelectric conversion unit and the first charge accumulation unit.
(2)
The driving unit performs driving for outputting the photoelectric charges accumulated in the photoelectric conversion unit and the first charge accumulating unit as an electric signal a predetermined number of times during the exposure period as the second driving. The solid-state imaging device according to 1).
(3)
An integration unit that integrates the value of the electrical signal output during the exposure period for each pixel;
The solid-state imaging device according to (2), further including: a holding unit that holds an integrated value for each pixel.
(4)
The solid-state imaging device according to any one of (1) to (3), wherein the driving unit switches between the first driving and the second driving according to a length of the exposure period.
(5)
In the exposure period, the driving unit accumulates photocharges less than or equal to the saturation charge amount of the photoelectric conversion unit in the photoelectric conversion unit, and exceeds the saturation charge amount of the photoelectric conversion unit during the exposure period. A drive for accumulating charges in the first charge accumulating unit and the second charge accumulating unit is performed, and as the second driving, a photocharge less than a saturation charge amount of the photoelectric conversion unit is applied during the exposure period. The solid-state imaging according to any one of (1) to (4), wherein the solid-state imaging according to any one of (1) to (4) described above is performed. apparatus.
(6)
The unit pixel is
A first transfer gate unit that transfers the photocharge accumulated in the photoelectric conversion unit to the first charge accumulation unit;
The solid-state imaging according to (5), further including: a first overflow path that is formed under the first transfer gate and transfers the photoelectric charge overflowing from the photoelectric conversion unit to the first charge accumulation unit. apparatus.
(7)
The unit pixel is
A second transfer gate portion for transferring the photocharge accumulated in the first charge accumulation portion to the second charge accumulation portion;
(6) further comprising: a second overflow path formed under the second transfer gate and transferring photocharges overflowing from the first charge accumulation unit to the second charge accumulation unit. The solid-state imaging device described.
(8)
The driving unit accumulates photocharges less than or equal to a saturation charge amount of the first charge accumulation unit in the first charge accumulation unit when transferring photocharges from the photoelectric conversion unit to all pixels simultaneously, The solid-state imaging device according to any one of (1) to (7), wherein driving is performed such that photocharges exceeding a saturation charge amount of one charge storage unit are stored in the second charge storage unit.
(9)
The unit pixel includes a charge discharge gate unit that selectively discharges the charge in the photoelectric conversion unit in a period in which photoelectric charge is not accumulated in the photoelectric conversion unit. Any one of (1) to (8) The solid-state imaging device described.
(10)
The unit pixel is
It has a floating diffusion part that outputs electric charge as an electrical signal,
The solid-state imaging device according to any one of (1) to (9), wherein the second charge accumulation unit includes a capacitor having a larger capacitance value per unit area than the first charge accumulation unit.
(11)
The unit pixel is
A first transfer gate unit that transfers the photocharge accumulated in the photoelectric conversion unit to the first charge accumulation unit;
The solid-state imaging device according to (10), further including: a second transfer gate portion that transfers the photocharge accumulated in the first charge accumulation portion to the floating diffusion portion.
(12)
The unit pixel is
The solid-state imaging device according to (11), further including a third transfer gate unit that transfers the photocharge accumulated in the first charge accumulation unit to the second charge accumulation unit.
(13)
The unit pixel is
A reset gate portion for resetting the photoelectric charge of the floating diffusion portion;
An amplification transistor that converts the photoelectric charge of the floating diffusion portion into an electrical signal;
The solid-state imaging device according to any one of (10) to (12), further including a selection transistor that is connected to the amplification transistor and performs pixel selection.
(14)
The unit pixel is
A reset gate portion for resetting the floating diffusion portion;
An amplification transistor that converts the photoelectric charge of the floating diffusion portion into an electrical signal;
The solid-state imaging device according to any one of (10) to (12), wherein pixel selection is performed by applying a driving voltage to the reset gate unit.
(15)
The first charge accumulation unit has a saturation charge amount smaller than a saturation charge amount of the photoelectric conversion unit,
The second charge accumulation unit has a saturation charge amount in which a total of a saturation charge amount and a saturation charge amount of the first charge accumulation unit is equal to or more than a saturation charge amount of the photoelectric conversion unit. The solid-state imaging device according to any one of 14).
(16)
The solid-state imaging device according to any one of (1) to (9), wherein the second charge accumulation unit includes a floating diffusion unit that outputs charges as an electric signal.
(17)
The unit pixel is
A first transfer gate unit that transfers the photocharge accumulated in the photoelectric conversion unit to the first charge accumulation unit;
The solid-state imaging device according to (16), further comprising: a second transfer gate unit that transfers the photocharge stored in the first charge storage unit to the floating diffusion unit.
(18)
The unit pixel is
A reset gate portion for resetting the photoelectric charge of the floating diffusion portion;
An amplification transistor that converts the photoelectric charge of the floating diffusion portion into an electrical signal;
The solid-state imaging device according to (17), further including: a selection transistor connected to the amplification transistor and performing pixel selection.
(19)
A plurality of unit pixels each including a photoelectric conversion unit that generates and accumulates a photocharge according to the amount of received light, a first charge accumulation unit including a buried MOS capacitor, and a second charge accumulation unit are arranged, A solid-state imaging device including a pixel array unit capable of batch exposure of the unit pixels,
Photoelectric charge generated by the photoelectric conversion unit during the exposure period is accumulated in the photoelectric conversion unit, the first charge accumulation unit, and the second accumulation unit, or the photoelectric charge is accumulated during the exposure period. A method for driving a solid-state imaging device that performs second driving for accumulating photoelectric charges generated by a conversion unit in the photoelectric conversion unit and the first charge storage unit.
(20)
A plurality of unit pixels each including a photoelectric conversion unit that generates and accumulates a photocharge according to the amount of received light, a first charge accumulation unit including a buried MOS capacitor, and a second charge accumulation unit are arranged, A pixel array unit capable of batch exposure of the unit pixels;
Photoelectric charge generated by the photoelectric conversion unit during the exposure period is accumulated in the photoelectric conversion unit, the first charge accumulation unit, and the second accumulation unit, or the photoelectric charge is accumulated during the exposure period. A solid-state imaging device comprising: a drive unit that performs a second drive for accumulating photoelectric charges generated by the conversion unit in the photoelectric conversion unit and the first charge accumulation unit;
An electronic apparatus comprising: a signal processing unit that performs signal processing on a signal output from the unit pixel.

  10, 10A, 10B CMOS image sensor, 11 pixel array unit, 12 vertical drive unit, 13 column processing unit, 14 horizontal drive unit, 15 system control unit, 16 pixel drive line, 17 vertical signal line, 18 signal processing unit, 19 Data storage unit 30, 66 first charge storage unit, 40, 67 second charge storage unit, 60A to 60A2, 60B unit pixel, 61 photodiode, 62 first transfer gate unit, 63 second transfer gate Part, 64 third transfer gate part, 65 reset gate part, 68 amplification transistor, 69 selection transistor, 70 charge discharge gate part, 71 FD part (floating diffusion part), 111a, 111b memory, 112 addition part, 200 imaging device 202 Imaging device

Claims (20)

A plurality of unit pixels each including a photoelectric conversion unit that generates and accumulates a photocharge according to the amount of received light, a first charge accumulation unit including a buried MOS capacitor, and a second charge accumulation unit are arranged, A pixel array unit capable of batch exposure of the unit pixels;
Photoelectric charge generated by the photoelectric conversion unit during the exposure period is accumulated in the photoelectric conversion unit, the first charge accumulation unit, and the second accumulation unit, or the photoelectric charge is accumulated during the exposure period. A solid-state imaging device comprising: a drive unit that performs a second drive for accumulating photoelectric charges generated by the conversion unit in the photoelectric conversion unit and the first charge accumulation unit. The driving unit performs driving for outputting the photoelectric charges accumulated in the photoelectric conversion unit and the first charge accumulation unit as an electrical signal a predetermined number of times during the exposure period as the second driving. The solid-state imaging device according to 1. An integration unit that integrates the value of the electrical signal output during the exposure period for each pixel;
The solid-state imaging device according to claim 2, further comprising: a holding unit that holds an integrated value for each pixel. The solid-state imaging device according to claim 1, wherein the driving unit switches between the first driving and the second driving according to a length of the exposure period. In the exposure period, the driving unit accumulates photocharges less than or equal to the saturation charge amount of the photoelectric conversion unit in the photoelectric conversion unit, and exceeds the saturation charge amount of the photoelectric conversion unit during the exposure period. A drive for accumulating charges in the first charge accumulating unit and the second charge accumulating unit is performed, and as the second driving, a photocharge less than a saturation charge amount of the photoelectric conversion unit is applied during the exposure period. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is driven to accumulate in the photoelectric conversion unit and accumulate in the first charge accumulation unit photocharges exceeding a saturation charge amount of the photoelectric conversion unit. The unit pixel is
A first transfer gate unit that transfers the photocharge accumulated in the photoelectric conversion unit to the first charge accumulation unit;
The solid-state imaging device according to claim 5, further comprising: a first overflow path that is formed under the first transfer gate and transfers the photoelectric charge overflowing from the photoelectric conversion unit to the first charge accumulation unit. . The unit pixel is
A second transfer gate portion for transferring the photocharge accumulated in the first charge accumulation portion to the second charge accumulation portion;
7. A second overflow path formed under the second transfer gate and transferring photocharges overflowing from the first charge accumulation unit to the second charge accumulation unit. Solid-state imaging device. The driving unit accumulates photocharges less than or equal to a saturation charge amount of the first charge accumulation unit in the first charge accumulation unit when transferring photocharges from the photoelectric conversion unit to all pixels simultaneously, 2. The solid-state imaging device according to claim 1, wherein the solid-state imaging device according to claim 1 is driven to accumulate photocharges exceeding a saturation charge amount of one charge accumulation unit in the second charge accumulation unit. The solid-state imaging device according to claim 1, wherein the unit pixel includes a charge discharge gate unit that selectively discharges charges in the photoelectric conversion unit during a period in which photoelectric charge is not accumulated in the photoelectric conversion unit. The unit pixel is
It has a floating diffusion part that outputs electric charge as an electrical signal,
The solid-state imaging device according to claim 1, wherein the second charge accumulation unit is configured by a capacitor having a capacitance value per unit area larger than that of the first charge accumulation unit. The unit pixel is
A first transfer gate unit that transfers the photocharge accumulated in the photoelectric conversion unit to the first charge accumulation unit;
The solid-state imaging device according to claim 10, further comprising: a second transfer gate unit configured to transfer the photocharge accumulated in the first charge accumulation unit to the floating diffusion unit. The unit pixel is
The solid-state imaging device according to claim 11, further comprising a third transfer gate unit that transfers the photocharge accumulated in the first charge accumulation unit to the second charge accumulation unit. The unit pixel is
A reset gate portion for resetting the photoelectric charge of the floating diffusion portion;
An amplification transistor that converts the photoelectric charge of the floating diffusion portion into an electrical signal;
The solid-state imaging device according to claim 10, further comprising: a selection transistor connected to the amplification transistor for performing pixel selection. The unit pixel is
A reset gate portion for resetting the floating diffusion portion;
An amplification transistor that converts the photoelectric charge of the floating diffusion portion into an electrical signal;
The solid-state imaging device according to claim 10, wherein pixel selection is performed by applying a driving voltage to the reset gate unit. The first charge accumulation unit has a saturation charge amount smaller than a saturation charge amount of the photoelectric conversion unit,
11. The second charge accumulation unit has a saturation charge amount in which a total of a saturation charge amount and a saturation charge amount of the first charge accumulation unit is equal to or more than a saturation charge amount of the photoelectric conversion unit. Solid-state imaging device. The solid-state imaging device according to claim 1, wherein the second charge accumulation unit includes a floating diffusion unit that outputs charges as an electric signal. The unit pixel is
A first transfer gate unit that transfers the photocharge accumulated in the photoelectric conversion unit to the first charge accumulation unit;
The solid-state imaging device according to claim 16, further comprising: a second transfer gate unit that transfers the photocharge accumulated in the first charge accumulation unit to the floating diffusion unit. The unit pixel is
A reset gate portion for resetting the photoelectric charge of the floating diffusion portion;
An amplification transistor that converts the photoelectric charge of the floating diffusion portion into an electrical signal;
The solid-state imaging device according to claim 17, further comprising: a selection transistor connected to the amplification transistor for performing pixel selection. A plurality of unit pixels each including a photoelectric conversion unit that generates and accumulates a photocharge according to the amount of received light, a first charge accumulation unit including a buried MOS capacitor, and a second charge accumulation unit are arranged, A solid-state imaging device including a pixel array unit capable of batch exposure of the unit pixels,
Photoelectric charge generated by the photoelectric conversion unit during the exposure period is accumulated in the photoelectric conversion unit, the first charge accumulation unit, and the second accumulation unit, or the photoelectric charge is accumulated during the exposure period. A method for driving a solid-state imaging device that performs second driving for accumulating photoelectric charges generated by a conversion unit in the photoelectric conversion unit and the first charge storage unit. A plurality of unit pixels each including a photoelectric conversion unit that generates and accumulates a photocharge according to the amount of received light, a first charge accumulation unit including a buried MOS capacitor, and a second charge accumulation unit are arranged, A pixel array unit capable of batch exposure of the unit pixels;
Photoelectric charge generated by the photoelectric conversion unit during the exposure period is accumulated in the photoelectric conversion unit, the first charge accumulation unit, and the second accumulation unit, or the photoelectric charge is accumulated during the exposure period. A solid-state imaging device comprising: a drive unit that performs a second drive for accumulating photoelectric charges generated by the conversion unit in the photoelectric conversion unit and the first charge accumulation unit;
An electronic apparatus comprising: a signal processing unit that performs signal processing on a signal output from the unit pixel.

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