CN107846217B

CN107846217B - Self-calibration circuit

Info

Publication number: CN107846217B
Application number: CN201710443129.3A
Authority: CN
Inventors: 管继孔; 赵煜; 林嘉亮
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2016-09-20
Filing date: 2017-06-13
Publication date: 2021-05-25
Anticipated expiration: 2037-06-13
Also published as: TWI638524B; CN107846217A; TW201815072A; US9705512B1

Abstract

A self-correcting circuit is provided, a circuit receives a reference clock and outputs an output clock according to a clock multiplier, the circuit comprises a digital control time sequence adjusting circuit, a time sequence detecting circuit, a loop filter, a controllable oscillator, a clock frequency eliminator, a modulator and a correcting circuit, wherein the modulator is used for modulating the clock multiplier into a divisor and calculating a known noise caused by the modulation operation; in addition, the digitally controlled timing adjustment circuit, the timing detection circuit, the loop filter, the controllable oscillator, and the clock divider form a feedback loop, so that the frequency of the output clock is equal to the frequency of the reference clock multiplied by the clock multiplier, but the known noise caused by the modulation operation is corrected by the digitally controlled timing adjustment circuit, and the correction circuit corrects the known noise in a closed loop manner, thereby minimizing a correlation between the known noise and the output of the timing detection circuit.

Description

Self-calibration circuit

Technical Field

The present invention generally relates to phase locked loops.

Background

Those skilled in the art will understand the terms and concepts of microelectronics, such as voltages, currents, signals, logic signals, clocks, rising edges, phases, capacitors, charges, charge pumps, transistors, MOS (metal oxide semiconductor), PMOS (P-channel metal oxide semiconductor), NMOS (N-channel metal oxide semiconductor), sources, gates, drains, circuit nodes, ground nodes, operational amplifiers, common mode feedback, electromotive force (electromotive force), switches, single-ended circuits, differential circuits, etc., and therefore, the terms and concepts of microelectronics used in the present disclosure will not be described in detail herein.

In the present disclosure, a logic signal refers to a signal having two states, i.e., "logic level high" and "logic level low", which can also be represented as "1" and "0". To avoid redundancy, a logic signal in a "logic level high" ("logic level low") state may be described briefly as the logic signal being "high" ("low"), or as the logic signal being "1" ("0"). In addition, to avoid redundancy, reference numerals may be omitted, and thus the above description is simplified to the logic signal being high (low) or 1(0), and the description is understood to be illustrative of the states of the logic signal.

When a logic signal is high, it is called "asserted". When a logic signal is low, it is called "de-asserted".

A clock signal is a cyclic logic signal. To avoid redundancy, hereinafter, the "clock signal" may be simply referred to as "clock".

A timing of a clock signal refers to an instant (time instant) at which the clock signal undergoes a state transition (transition), which may refer to a low-to-high transition or to a high-to-low transition. When a clock signal undergoes a low-to-high (high-to-low) transition, it corresponds to a rising (falling) edge in a timing diagram.

A Phase Lock Loop (PLL) receives a first clock and outputs a second clock, so that the phase of the second clock tracks the phase of the first clock, and as a result, the frequency of the second clock is determined by the frequency of the first clock. A phase-locked loop of the prior art includes a phase/frequency detector (hereinafter PFD), a charge pump (hereinafter CP) circuit, a loop filter (hereinafter LF), a voltage controlled oscillator (hereinafter VCO), and a clock divider circuit (clock divider circuit), wherein the VCO outputs the second clock according to a control voltage, and thus the frequency of the second clock is determined by the control voltage; the clock frequency dividing circuit receives the second clock and outputs a third clock according to a divisor (division ratio); the PFD receives the first clock and the third clock and outputs a timing signal to represent a difference in timing between the first clock and the third clock; the CP circuit converts the time sequence signal into a current signal; the LF filters the current signal to generate the control voltage for controlling the frequency of the second clock. Accordingly, the frequency of the second clock is adjusted in a closed loop manner, thereby tracking the frequency of the first clock. The PFD, CP circuit, LF, VCO and clock divider circuits are well known in the art, and therefore their contents are not described in detail herein. In a steady state, the frequency of the second clock is equal to the frequency of the first clock multiplied by a multiplier (multiplication factor) N, which can be expressed as follows:

N＝N_int+α

wherein N is_intIs a positive integer and alpha is a proportional number which is less than one but not less than zero. If alpha is zero, the clock frequency-dividing circuit has a fixed divisor N_intThat is, the circuit performs a "divide by N_int"wherein every N of the second clock_intA cycle (cycle), one cycle of the third clock is output. If α is not equal to zero, it must be a fraction, in this case, the phase-locked loop is called fractional-N PLL (fractional-N PLL), and the clock divider circuit cannot have a fixed divisor. In one example, the divisor of the clock frequency divider circuit is modulated by a sigma-delta modulator and dynamically divided by N_intAnd N_int+1 round trip (toggle between N_int and N_int+1) so that an average of the divisor equals N_int+ α, since the value of the divisor is modulated, the instantaneous value (instant value) will be different from the average value (e.g., N) of the divisor_intAnd N_int+1 are all different from N_int+ α) resulting in a transient noise (instantaneous noise) attached to the PLL. In a US patent (US 7,999,622), Galton et al disclose a method for eliminating the additive noise caused by the modulation of the divisor based on using a digital-to-analog converter to output a current that offsets the additive noise in the output of a charge pump circuit (resulting from the modulation of the divisor), however, the digital-to-analog converter (DAC) itself also generates noise, although a large current can be used to reduce the effect of the noise, at the cost of high power consumption, and in addition, the DAC linearity is not perfect in practice, which may give the PLL additional noise, and a dynamic element may be used to reduce the adverse effect of the DAC nonlinearityMatching techniques, but at the cost of high circuit complexity.

In view of the problems of the prior art, the disclosed invention discloses a method for eliminating the noise in a fractional PLL, which is derived from the modulation process of a divisor, without consuming high power or requiring high circuit complexity.

Disclosure of Invention

One aspect of the present invention is directed to a digitally controlled timing adjustment circuit for correcting a pre-known (pre-known) timing error in a fractional phase locked loop caused by modulation of a divisor of a clock divider, wherein a gain of the digitally controlled timing adjustment circuit is corrected in a closed loop manner based on the pre-known timing error and a residual timing error of an output of the digitally controlled timing adjustment circuit.

In one embodiment, a circuit comprises: a digital control time sequence adjusting circuit for receiving a first clock and a second clock and outputting a third clock and a fourth clock according to a noise eliminating signal and a gain control signal; a timing detection circuit for receiving the third clock and the fourth clock and outputting a timing error signal; a filter circuit for receiving the timing error signal and outputting an oscillator control signal; a controllable oscillator for receiving the oscillator control signal and outputting a fifth clock; a clock frequency divider for receiving the fifth clock and outputting the second clock according to a divisor; a modulator for receiving a clock multiplier and outputting the divisor and the noise cancellation signal, wherein an average value of the divisor is equal to the clock multiplier; and a correction circuit for receiving the timing error signal and the noise cancellation signal and outputting the gain control signal. In one embodiment, a timing difference between the fourth clock and the third clock is equal to a sum of: a timing difference between the second clock and the first clock, the noise cancellation signal scaled according to the gain control signal, and a fixed timing offset. In one embodiment, the digitally controlled timing adjustment circuit comprises: a fixed delay circuit for receiving the second clock and outputting the fourth clock; and a digitally controlled variable delay circuit for receiving the first clock and for outputting the third clock according to the noise cancellation signal and the gain control signal. In one embodiment, a delay amount of the digitally controlled variable delay circuit is linearly dependent on the noise cancellation signal and linearly dependent on the gain control signal. In one embodiment, the digitally controlled variable delay circuit comprises: an adjustable inverter controlled by the gain control signal; and a variable capacitor controlled by the noise cancellation signal. In one embodiment, the calibration circuit comprises: a charge pump for receiving the timing error signal and outputting an intermediate current signal according to a common-mode feedback voltage; a single-pole double-throw switch controlled by a symbol of the noise cancellation signal; an integrator for receiving the intermediate current signal through the single-pole double-throw switch and outputting the gain control signal; and a common-mode feedback network for receiving a first voltage at a positive input terminal of the integrator and a second voltage at a negative input terminal of the integrator, and outputting the common-mode feedback voltage, wherein a first throw of the single-pole double-throw switch is coupled to the positive input terminal of the integrator, and a second throw of the single-pole double-throw switch is coupled to the negative input terminal of the integrator. In one embodiment, the modulator comprises a one-order delta-sigma modulator. In one embodiment, the controllable oscillator is a voltage controlled oscillator. In one embodiment, the clock divider is a counter.

In one embodiment, a method comprises the steps of: receiving a first clock and a clock multiplier; modulating the clock multiplier to a divisor, wherein an average of the divisor is equal to the clock multiplier; establishing a noise cancellation signal according to a difference between the clock multiplier and the divisor; deriving a third clock and a fourth clock from the first clock and a second clock using a digitally controlled timing adjustment circuit according to the noise cancellation signal and a gain control signal; establishing a timing error signal by detecting a timing difference between the fourth clock and the third clock; filtering the timing error signal to generate an oscillator control signal; outputting a fifth clock by using a controllable oscillator according to the oscillator control signal; down-converting the fifth clock according to the divisor to output the second clock; and adjusting the gain control signal according to a correlation between the timing error signal and the noise cancellation signal. In one embodiment, the digitally controlled timing adjustment circuit comprises: a fixed delay circuit for receiving the second clock and outputting the fourth clock; and a digitally controlled variable delay circuit for receiving the first clock and for outputting the third clock according to the noise cancellation signal and the gain control signal. In one embodiment, a delay amount of the digitally controlled variable delay circuit is linearly dependent on the noise cancellation signal and linearly dependent on the gain control signal. In one embodiment, the digitally controlled variable delay circuit comprises: an adjustable inverter controlled by the gain control signal; and a variable capacitor controlled by the noise cancellation signal. In one embodiment, the step of adjusting the gain control signal uses a calibration circuit comprising: a charge pump for receiving the timing error signal and outputting an intermediate current signal according to a common-mode feedback voltage; a single-pole double-throw switch controlled by a symbol of the noise cancellation signal; an integrator for receiving the intermediate current signal through the single-pole double-throw switch and outputting the gain control signal; and a common-mode feedback network for receiving a first voltage at a positive input terminal of the integrator and a second voltage at a negative input terminal of the integrator, and outputting the common-mode feedback voltage, wherein a first throw of the single-pole double-throw switch is coupled to the positive input terminal of the integrator, and a second throw of the single-pole double-throw switch is coupled to the negative input terminal of the integrator. In one embodiment, the modulator for modulation is a one-order delta-sigma modulator. In one embodiment, the controllable oscillator is a voltage controlled oscillator. In one embodiment, the clock divider is a counter.

The features, implementations, and technical advantages of the present invention are described in detail below with reference to the accompanying drawings.

Drawings

Fig.1A shows a functional block diagram of a fractional phase-locked loop according to an embodiment of the present invention.

FIG. 1B shows a schematic diagram of a phase/frequency detector.

FIG. 1C shows a schematic diagram of a charge pump.

FIG. 1D shows a schematic diagram of a loop filter.

FIG. 1E shows a schematic diagram of a voltage controlled oscillator.

FIG. 1F shows a functional block diagram of a digitally controlled timing adjustment circuit.

FIG. 1G shows a schematic diagram of a digitally controlled variable delay circuit.

FIG. 2 shows a schematic diagram of a calibration circuit.

Fig. 3 shows a schematic diagram of a modulator.

FIG. 4 shows a flow chart of the method of the present invention.

Description of reference numerals:

100 Phase Locked Loop (PLL)

110 phase/frequency detector (PFD)

120 Charge Pump (CP)

130 Loop Filter (LF)

140 Voltage Controlled Oscillator (VCO)

150 clock frequency divider (clock divider)

160 digital control timing adjustment circuit (logic circuit)

170 Modulator (MOD)

180 correction circuit (calibration circuit)

CK 1-CK 5 clock

S_TETiming error signal

I_CCorrection Current (output to LF 130of FIG.1A (to LF 130of FIG.1A))

V_CTLControl voltage (output to VCO 140of FIG.1A (to VCO 140of FIG.1A))

N_DIVDivisor

N_CNoise cancellation signal

N_MULClock multiplier

G_CGain control signal

111. 112 data flip-flop (DFF)

113 AND gate

RST reset signal

UP, DN logic signal (with S)_TE(embodying S_TE))

121 current source

122 current inflow source

123 first switch

124 second switch

125 output node

I_UPCharging current

I_DNDischarge current

131 resistor

132 first capacitance

133 second capacitance

141 voltage to current converter (V-to-C converter)

142 NMOS transistor

143 current mirror

144. 145 PMOS transistor

146 ring oscillator (ring oscillator)

147. 148, 149 inverter

Current mirror

VDD Power supply node

I_CTLControlling current

I_MMirror current

161 fixed delay circuit (fixed-delay circuit)

162 digitally controlled variable-delay circuit (digital controlled variable-delay circuit)

163_0, 163_1, 163_2, 163_3 capacitance

164_0, 164_1, 164_2, 164_3 switches

165 circuit node

166 variable capacitance (variable capacitor)

167 adjustable inverter (tunable inverter)

168 output inverter

N_C[0]、N_C[1]、N_C[2]、N_C[3]Bit cell

MP1 first PMOS transistor

MP2 second PMOS transistor

MN1 first NMOS transistor

MN1 second NMOS transistor

I_SCOut flowing current

I_SKFlowing current in

200 correction circuit

210 Charge pump (charge pump)

220 single pole double throw switch network (SPDT switching network)

230 integrator (integrator)

250 common mode feedback network (CM feedback network)

260 symbol detection circuit (Sign detection circuit)

211 current source

212 current inflow source

213 first switch

214 second switch

215 output node

221. 222 switch

231. 232 capacity

233 fully differential operational amplifier

252. 253 resistor

254 operational amplifier

261 sign arithmetic unit

262 inverter

I’_UPCharging current

I’_DNDischarge current

I’_CIntermediate current signal

POS, NEG logic signal

V_X+、V_X-Voltage of input terminal

G_C+、G_C-Voltage of output terminal

V_CMFBCommon mode feedback voltage

V_CMCommon mode voltage

V_CMRCommon mode reference voltage

300 modulator

301. 303, 305 summing operator

302 rounding operator

304. 306 delay unit

1^storder delta-sigma modulator first-order delta-sigma modulator

error accumulator

e₁Rounding errors

e_1dDelayed rounding errors

N_CNEXTIntermediate signal

N’_MULModulation multiplier

400 method flow chart

401 to 409

Detailed Description

The present invention relates to phase locked loops. While this specification describes several preferred embodiments of the invention, these embodiments are not limitations on the practice of the invention, in other words, the invention can be practiced in many ways and is not limited to the ways described in the embodiments of this specification and the features carried out therein. In other instances, well-known technical details are not shown or described in order to avoid obscuring aspects of the present invention.

Fig.1A shows a functional block diagram of a Phase Locked Loop (PLL)100, according to an embodiment of the present invention. The PLL 100 includes: a digitally controlled timing adjustment circuit 160 for receiving a first clock CK1 and a second clock CK2 and for receiving a noise cancellation signal N_CAnd a gain control signal G_CTo output a third clock CK3 and a fourth clock CK 4; a phase/frequency detector (PFD)110 for receiving the third clock CK3 and the fourth clock CK4 and outputting a timing error signal (S)_TETo indicate a timing difference between the third clock CK3 and the fourth clock CK 4; a Charge Pump (CP)120 for pumping the timing error signal S_TEIs converted into a correction current I_C(ii) a A Loop Filter (LF)130 for receiving the correction current I_CAnd outputs a control voltage V_CTL(ii) a A Voltage Controlled Oscillator (VCO)140 for generating a control voltage V according to the control voltage_CTLOutputting a fifth clock; a clock divider (150) for receiving the fifth clock CK5 and for dividing the clock by a divisor N_DIVOutputting the second clock CK 2; a Modulator (MOD)170 for modulating the clock signal according to a clock multiplier N_MULTo output the divisor N_DIVAnd the noise cancellation signal N_C(ii) a And a calibration circuit 180 for calibrating the timing error signal S according to the timing error signal S_TEAnd the noise cancellation signal N_CA correlation (correlation) between the gain control signals to output the gain control signal G_C. To avoid redundancy, hereinafter the first (second, third, fourth, fifth) clock CK1(CK2, CK3, CK4, CK5) will be referred to simply as CK1(CK2, CK3, CK4, CK 5); the timing error signal S_TEWill be abbreviated as S_TE(ii) a The correction current I_CWill be referred to as I_C(ii) a The control voltage V_CTLWill be referred to as V for short_CTL(ii) a The noise cancellation signal N_CWill be referred to as N for short_C(ii) a The gain control signal G_CWill be referred to as G for short_C(ii) a The clock multiplier N_MULWill be referred to as N for short_MUL(ii) a And the divisor N_DIVWill be referred to as N for short_DIV。

If the digitally controlled timing adjustment circuit 160 and the calibration circuit 180 are removed and the PFD 110 receives CK1 and CK2 instead of CK3 and CK4, the PLL 100 will be the same as the PLL of the prior art previously disclosed. Similar to prior art PLLs, the PLL 100 receives CK1 and uses the VCO 140 to output CK5, which is adjusted in a closed loop manner via a feedback path that includes the clock divider 150, the PFD 110, the CP 120, and the LF 130, such that the frequency of CK5 is equal to the frequency of CK1 multiplied by N_MUL，N_MULNot a pure integer (pure integer). Due to N_MULNot a pure integer, but N_DIV(which is the clock divisor of clock divider 150) must be an integer, N_DIVMust be modulated in a manner such that N_DIVAn average value of is equal to N_MUL. Modulator 170 receives N_MULAnd output N_DIVEffectively modulate N_DIVSo that N is_DIVIs equal to N_MUL. By doing so, the average frequency of CK5 will be equal to the frequency of CK1 multiplied by N_MULHowever, an instantaneous timing of CK2 may deviate from an ideal timing of a virtual clock divider, assuming that the virtual divider implements non-integer divisors. Due to N_DIVThe deviation of the instantaneous timing of CK2 from the ideal timing results in a transient noise (instantaneous noise) in the timing difference between CK2 and CK 1. However, from N_DIVIs known in advance (pre-knock), which can be calculated by the modulator 170 and is denoted as N_C. The digitally controlled timing adjustment circuit 160 is used to correct the delay time from N_DIVIs present in the timing difference between CK2 and CK1, whereby the timing difference between CK4 and CK3 is protected from the transient noise. However, N_CThe timing difference between CK2 and CK1 is analog in nature, so that a digital-to-analog conversion function is performed by the digitally controlled timing adjustment circuit 160 to convert N to N_CConverted into a timing difference quantity, which must be eliminated. G_CA gain factor for the digital-to-analog conversion is determined.

In one embodiment, a function of the digitally controlled timing adjustment circuit 160 can be expressed by the following mathematical expression:

t₄-t₃＝t₂-t₁+N_C·G_C+t_OS (I)

in the above formula, t₁Is the timing of a rising edge of CK1, t₂Is the timing of a rising edge of CK2, t₃Is the timing of a rising edge of CK3, t₄Is the timing of a rising edge of CK4, and t_OSIs a fixed timing offset, where t₂-t₁Is the timing difference between CK2 and CK1, and t₄-t₃Is the timing difference between CK4 and CK3, S_TERepresents a relative timing between CK4 and CK3, and is mathematically equal to t₄-t₃，N_CRepresents t₂-t₁In by N_DIVIf G is the instantaneous noise caused by the modulation of_C(which is the conversion gain used to convert N to_CConversion to timing difference to be eliminated) is set appropriately, t₂-t₁In by N_DIVWill be corrected so that the noise does not occur at t₄-t₃In another aspect, if G_CNot properly set, the noise may be excessively corrected or insufficiently corrected, resulting in t₄-t₃There is a residual noise, which becomes S_TEA part of (a). When G is_CSet too large (small), the noise is overcorrected (undercorrected), and therefore, t₄-t₃Will contain a residual noise that positively (negatively) correlates to N_CSo when N is_CWhen it is positive (negative), S_TEWill tend to be too high (low). Therefore, the calibration circuit 180 is based on N_CAnd S_TEA correlation between G and G_C: when S is_TEPositively (negatively) associating N_CWhich is represented by G_CToo large (small) and needs to be reduced (increased).

In one embodiment shown in FIG. 1B, the PFD 110 includes two data flip-flops (DFFs) 111 AND 112 AND an AND gate 113. Each DFF includes an input terminal labeled D, an output terminal labeled Q, a reset terminal labeled R, and a clock terminal represented by a wedge symbol, which are widely used in the art. DFF 111 outputs a first logic signal UP, and DFF 112 outputs a second logic signal DN. The AND gate 113 receivesThe two logic signals UP and DN output a reset signal RST. The first (second) logic signal up (dn) is asserted according to a rising edge of CK3(CK4) and de-asserted when the reset signal RST is asserted. The two logic signals UP and DN jointly represent the timing error signal S_TEIs used to represent a timing difference between CK3 and CK 4. The above embodiments are widely used and well known in the art and therefore are not described in detail herein.

In one embodiment shown in fig. 1C, CP 120 comprises: a current source 121 for flowing a charging current I_UP(ii) a A current sink 122 for flowing a discharge current I_DN(ii) a A first switch 123 for switching the charging current I when the logic signal UP is asserted_UPCoupled to an output node 125; and a second switch 124 for switching the discharge current I when the logic signal DN is asserted_DNCoupled to the output node 125. The output node 125 interfaces (interfaces with) and provides the modified current I_CTo LF 130 in fig. 1A. In the present disclosure, VDD represents a power supply node. FIG. 1C is well known in the art and is self-explanatory to those skilled in the art, and therefore will not be described in detail herein.

In one embodiment shown in fig. 1D, the LF 130 includes a resistor 131, a first capacitor 132, and a second capacitor 133 for receiving the correction current I from the CP 120 of fig.1A_CAnd is used for outputting the control voltage V_CTLTo the VCO 140of fig. 1A. FIG. 1D is well known in the art and is self-explanatory to those skilled in the art, and therefore will not be described in detail herein.

In one embodiment shown in fig. 1E, VCO 140 comprises: a voltage-to-current converter (V-to-C converter)141 for converting the control voltage V_CTLIs converted into a control current I_CTL(ii) a A current mirror 143 for converting the control current I_CTLMirrored as a mirrored current I_M(ii) a And a ring oscillator (ring oscillator)146 for mirroring the current I_MAnd outputs CK 5. The voltage-to-current converter 141 includes an NMOS transistor 142. The current mirror 143 includes two

PMOS transistors

144 and 145. The ring oscillator 146 includes three

inverters

147, 148 and 149 arranged in a ring topology and collectively receiving the mirrored current I_M. When the control voltage V is_CTLRise, the control current I_CTLRises and the mirror current I_MAs well as the same. Therefore, the three

inverters

147, 148 and 149 receive more energy (power) and become faster, resulting in a higher oscillation frequency of CK5 (quenching in a high oscillation frequency for CK 5).

The clock divider 150 may be implemented by a counter that increments a count value according to the rising edge of CK 5. The count value starts at 0, increases to 1 according to a rising edge of CK5, then increases to 2 according to the next rising edge of CK5, and so on. When the count value reaches N _DIV1, the count value returns to 0 upon the next rising edge of CK 5. In this manner, the counter cyclically counts from 0 to N_DIV-1. When the count value equals 0, CK2 is asserted; when the count value is other value, CK2 is deasserted.

The digitally controlled timing adjustment circuit 160 receives CK1 and CK2 and outputs CK3 and CK4, such that a timing difference between CK4 and CK3 is related to a timing difference between CK2 and CK1 as in equation (1). In one embodiment shown in fig. 1F, the digitally controlled timing adjustment circuit 160 comprises: a fixed delay circuit 161 for receiving CK2 and outputting CK 4; and a digitally controlled variable delay circuit 162 receiving CK1 and dependent on G_CAnd N_CAnd outputs CK 3. The fixed delay circuit 161 provides a fixed timing difference between CK4 and CK2, i.e., t₄-t₂Is fixed. In another aspect, the digitally controlled variable delay circuit 162 provides a variable timing difference between CK3 and CK1, and the variable timing difference is controlled by G_CAnd N_CIn other words, t₃-t₁Is variable and controlled by G_CAnd N_C. Thus, through G_CAnd N_CA variable controlled, t₄-t₃Is different from t₂-t₁. It is noted that the variable timing difference is linearly dependent on (linear dependent on) N_CAnd linearly dependent on G_C. In one embodiment, the fixed delay circuit 161 is a simple short circuit; in this example, the fixed delay is zero and CK3 is equal to CK 1. In another embodiment, the fixed delay circuit 161 is an inverter chain (inverter chain) comprising an even number of inverters configured in a cascaded topology.

In one embodiment, G_CIs a differential signal including a first terminal G_C+And a second terminal G_C-Wherein G is_C≡G_C+–G_C. In a non-limiting example, N_CIs a four-bit word (four-bit word) comprising four bits N_C[0]、N_C[1]、N_C[2]、N_C[3]. In one embodiment shown in fig. 1G, the digitally controlled variable delay circuit 162 comprises: an adjustable inverter 167 for receiving CK1 and for synchronizing with G_CAssociated control outputs an intermediate Clock (CKI) at a circuit node 165; an output inverter 168 for receiving the intermediate clock CKI and outputting CK 3; and a variable capacitor 166 for providing a capacitive load at the circuit node 165. The adjustable inverter 167 comprises: a first PMOS transistor MP1 according to G_C+Providing a source current I_SC(ii) a A first NMOS transistor MN1 for outputting a first signal according to G_C-Providing a sink current I_SK(ii) a A second PMOS transistor MP2 controlled by CK1 for enabling the current I_SCTo charge the variable capacitor 166 when CK1 is low (low); and a second NMOS transistor MN2 controlled by CK1 for enabling the current I_SKWhen CK1 is high (high), variable capacitor 166 is discharged. The variable capacitor 166 includes four capacitors 163_0, 163_1, 163_2, and 163_3, respectively based on N_C[0]、N_C[1]、N_C[2]、 N_C[3]Conditionally by four switches 164_0, 164_1, 164_2 and 164_3 connect circuit node 165to ground through a capacitor (shunt the circuit node 165to ground). The output inverter 168 acts as an inverting buffer and, together with the adjustable inverter 167, makes CK3 identical to CK1 (except that they differ by a delay). In one embodiment, a capacitance value of the variable capacitor 166 follows N_CLinearly increases. A low-to-high (high-to-low) transition of CK1 causes the adjustable inverter 167 to pass the in (out) current I_SK(I_SC) The variable capacitor 166 is discharged (charged) through the second nmos (pmos) transistor MN2(MP2), which causes a high-to-low (low-to-high) transition of CKI. In one embodiment, the outgoing (incoming) current I_SC(I_SK) Is negatively linearly dependent on G_C+(G_C-) I.e. G_C+ (G_C-) A positive increase (positive increment) of (b) will result in the outgoing (incoming) current I_SC(I_SK) Negative increase (negative increment). The point in time (i.e., CKI beginning to finish (tabs to low to high) transition in response to the low to high (high to low) transition of CK 1) is linearly dependent on an overall capacitance value at the circuit node, but negatively linearly dependent on the in (out) current I_SK(I_SC) The size of (2). Since the capacitance of the variable capacitor is linearly dependent on N_CAnd the outgoing (incoming) current I_SC(I_SK) Is negatively linearly dependent on G_C+ (G_C-) The point in time (i.e. the intermediate clock CKI beginning to end the transition) depends approximately linearly on N_CAnd linearly dependent on G_C. Therefore, the digitally controlled timing adjustment circuit 160 effectively embodies equation (1).

The correction circuit 180 is based on S_TEAnd N_CA correlation (correlation) between the outputs G_C. In one embodiment, G_CIs established according to an adaptive operation algorithm (algorithm of adaptation) as follows:

in the above formula, μ is an adaptive operating constant (adaptation constant),

is the value prior to the adaptive operation,

is the value after the adaptation operation. The correction circuit 200 shown in fig. 2 includes: a charge pump 210 for receiving S_TEThe charge pump 210 is also used to provide a common mode feedback voltage V, which includes UP and DN as described above_CMFBOutputs an intermediate current signal I'_C(ii) a An integrator 230 for receiving the intermediate current signal I 'via a single-pole-double-throw (SPDT) switch network 220'_CAnd outputs the gain control signal G_CIncludes the first terminal G_C+And the second end G_C-(ii) a And a common mode feedback network 250 for outputting the common mode feedback voltage V_CMFB. The calibration circuit 200 further comprises a sign detection circuit (sign detection circuit)260 for receiving N_CAnd outputs a pair of logic signals POS and NEG that are used to control the SPDT switch network 220. The CP 210 includes: a current source 211 for supplying a charging-up current I'_UP(ii) a A current-flowing source (current sink)212 for flowing a discharge-down current I'_DN(ii) a A first switch 213 for switching the charging current I 'when the logic signal UP is asserted'_UPCoupled to an output node 215; and a second switch 214 for switching the discharge current I 'when the logic signal DN is asserted'_DNIs coupled to the output node 215. The output node 215 interfaces (interfaces with) and provides the intermediate current signal I'_CTo the SPDT switch network 220. The symbol detection circuit 260 includes a symbol operator 261 and an inverter 262, when N is_CPositive, POS is asserted and NEG is de-asserted; when N is present_CWhen it is negative, POS is releasedImmediately NEG is established; when N is present_CAt zero, both POS and NEG are deasserted, the two logic signals POS and NEG thus representing N_CA symbol of (2). The SPDT switch network 220 includes two switches 221 and 222 controlled by the two logic signals POS and NEG, respectively. The integrator 230 includes: a fully differential operational amplifier (233); and two

capacitors

231 and 232 configured in a negative feedback topology. The fully differential operational amplifier 233 includes two input terminals on the left side, denoted as "+" and "-", and two output terminals on the right side, denoted as "+" and "-". The voltages of the two input ends are respectively V_X+And V_X-The voltages of the two output ends are respectively G_C-And G_C+. When N is present_CIf n and POS are thus established, if'_CIs positive (negative), the capacitor 232 is I 'via the switch 221'_CCharging (discharging), which results in G_C+Is decreased (increased), thereby resulting in G_CDecrease (increase) of. Furthermore, the intermediate current signal I'_CIs S_TEIs represented by a current pattern, so that when N is_CWhen it is positive (negative), G_CWith a direct ratio to-S_TE(S_TE) Is adjusted by an increment. The correction circuit 200 thus exhibits the function as described in equation (2).

The CM feedback network 250 includes: two

resistors

252 and 253 for V_X+And V_X-Form a series connection therebetween to sense (tap) a common mode voltage V_CM(i.e., performing CM detection); and an operational amplifier 254 for receiving a common mode reference voltage V at a non-inverting terminal (denoted as "+")_CMRAnd receiving the common mode voltage V at an inverting terminal (labeled "-")_CMAnd outputs a common mode feedback voltage V_CMFBTo control the discharge current I'_DN. In an alternative embodiment (not shown), the common mode feedback voltage V_CMFBControlling the charging current I'_UP. In either case, the CM feedback network 250 adjusts a portion of the charge pump 210 in a closed loop manner such that V_X+And V_XAn average of-will be approximately V_CMR. Common mode feedbackAre well known to those skilled in the art and are not described in detail herein.

In one embodiment, the MOD 170 of fig.1A is implemented by the modulator 300 shown in fig. 3. The modulator 300 includes: a rounding operator (denoted round ()) 302; two delay units (in Z)^-1To) 304 and 306; and three summing

operators

301, 303, and 305. The delay unit 304 receives a rounding error e₁And outputs a delayed rounding error e_1d. Summing operator 301 sums N_MULAnd e_1dTo generate a modulated multiplier N'_MUL. Rounding operator 302 rounds N'_MULTo generate N_DIV. Totalizer 303 will sum N'_MULMinus N_DIVTo produce e₁. Summing operator 305 sums N_CAnd N_DIVThen subtract N_MULTo output an intermediate signal N_CNEXT. Delay unit 306 receives N_CNEXTAnd output N_C. The rounding operator 302, the summing

operators

301 and 303, and the delay unit 304 form a 1st order delta-sigma modulator, whereby N_DIVAn average value of is equal to N_MUL. The summing operator 305 and the delay unit 306 constitute an error accumulator (error accumulator) whereby N_CIs equal to N_DIVAnd N_MULCumulative aggregate of the differences between. N is a radical of_DIVAnd N_MULThe difference between them is a transient error of the first order delta-sigma modulator and thus an error of the clock divide operation of the clock divider 150. N is a radical of_CIs N_DIVAnd N_MULThe cumulative sum of the differences represents the cumulative error of the clock dividing operation of the clock divider 150, and thus the timing error of CK2, by using N_CThe determined adjustment amount is used to adjust the timing difference between CK2 and CK1, and the digitally controlled timing adjustment circuit 160 corrects the timing error.

Please refer to fig. 1F. In an alternative embodiment (not shown), the fixed delay circuit 161 and the digitally controlled variable delay circuit 162 are swapped (swapped) so that the digitally controlled variable delay circuit 162 is switched by G_Cand-N_CControlled by, wherein-N_CIs N_CInversion (inversion) of (c). In this alternative embodiment, the timing difference between CK3 and CK1 is fixed, and the timing difference between CK4 and CK2 is variable and is fixed by G_Cand-N_CControlled, but the circuit function remains unchanged and equation (1) is still satisfied.

Please continue to refer to fig. 1F. The digitally controlled variable delay circuit 162 belongs to a digital-to-time converter (digital-to-time converters) in which a timing of an output clock is controlled by a digital signal. The digitally controlled variable delay circuit 162 may be implemented by other digital-to-time converters as long as the timing difference between CK3 and CK1 is still linearly dependent on N_CAnd G_C。

Now, please refer to FIG. 1A. The PFD 110 is merely an exemplary timing detection circuit, and not a limitation, an alternative timing detection circuit may be used in place of this circuit, as long as the timing difference between CK4 and CK3 can be detected and appropriately compensated by an associated timing error signal (e.g., S)_TE) To indicate. Furthermore, VCO 140 is merely an exemplary VCO circuit and not a limitation, an alternative VCO circuit may be used instead, as long as an output clock (e.g., CK5) may be generated and the frequency of the output clock may be controlled by a control signal (e.g., V5)_CTL) And (4) controlling. Similarly, the CP 120 and the LF 130 are exemplary (not limiting) embodiments for filtering a timing error signal (e.g., S) generated by a preamble timing detection circuit (e.g., the PFD 110)_TE) Thereby generating a control signal (e.g. V)_CTL). An alternative embodiment may be employed so long as the timing error signal can be filtered into a controllable signal for controlling a subsequent controllable oscillator circuit (e.g., VCO 140).

A flow chart 400 of a method according to an embodiment of the invention includes: receiving a first clock and a clock multiplier (step 401); modulating the clock multiplier to a divisor, wherein an average of the divisor equals the clock multiplier (step 402); establishing a noise cancellation signal according to a difference between the clock multiplier and the divisor (step 403); deriving a third clock and a fourth clock from the first clock and a second clock using a digitally controlled timing adjustment circuit according to the noise cancellation signal and a gain control signal (step 404); establishing a timing error signal by detecting a timing difference between the fourth clock and the third clock (step 405); filtering the timing error signal to generate an oscillator control signal (step 406); outputting a fifth clock using a controllable oscillator according to the oscillator control signal (step 407); down-converting the fifth clock according to the divisor to output the second clock (step 408); and adjusting the gain control signal according to a correlation between the timing error signal and the noise cancellation signal (step 409).

Although the embodiments of the present invention have been described above, the embodiments are not intended to limit the present invention, and those skilled in the art can make variations on the technical features of the present invention according to the explicit or implicit contents of the present invention, and all such variations may fall within the scope of the patent protection sought by the present invention.

Claims

1. A self-calibration circuit, comprising:

a digital control time sequence adjusting circuit for receiving a first clock and a second clock and outputting a third clock and a fourth clock according to a noise eliminating signal and a gain control signal;

a timing detection circuit for receiving the third clock and the fourth clock and outputting a timing error signal;

a filter circuit for receiving the timing error signal and outputting an oscillator control signal;

a controllable oscillator for receiving the oscillator control signal and outputting a fifth clock;

a clock frequency divider for receiving the fifth clock and outputting the second clock according to a divisor;

a modulator for receiving a clock multiplier and outputting the divisor and the noise cancellation signal, wherein an average value of the divisor is equal to the clock multiplier; and

a correction circuit for receiving the timing error signal and the noise cancellation signal and outputting the gain control signal.

2. The self-calibration circuit as claimed in claim 1, wherein a timing difference between the fourth clock and the third clock is equal to a sum of: a timing difference between the second clock and the first clock, the noise cancellation signal scaled according to the gain control signal, and a fixed timing offset.

3. The self-calibration circuit of claim 1 wherein the digitally-controlled timing adjustment circuit comprises: a fixed delay circuit for receiving the second clock and outputting the fourth clock; and a digitally controlled variable delay circuit for receiving the first clock and for outputting the third clock according to the noise cancellation signal and the gain control signal.

4. The self-calibration circuit of claim 3 wherein a delay amount of the digitally controlled variable delay circuit is linearly dependent on the noise cancellation signal and linearly dependent on the gain control signal.

5. The self-calibration circuit as claimed in claim 4, wherein the calibration circuit comprises: a charge pump for receiving the timing error signal and outputting an intermediate current signal according to a common-mode feedback voltage; a single-pole double-throw switch controlled by a symbol of the noise cancellation signal; an integrator for receiving the intermediate current signal through the single-pole double-throw switch and outputting the gain control signal; and a common-mode feedback network for receiving a first voltage at a positive input terminal of the integrator and a second voltage at a negative input terminal of the integrator, and outputting the common-mode feedback voltage, wherein a first throw of the single-pole double-throw switch is coupled to the positive input terminal of the integrator, and a second throw of the single-pole double-throw switch is coupled to the negative input terminal of the integrator.

6. The self-calibration circuit as claimed in claim 5, wherein the integrator comprises a differential operational amplifier and two feedback capacitors.

7. The self-calibration circuit as claimed in claim 6, wherein the single-pole double-throw switch is configured to steer the intermediate current signal to the positive input terminal of the integrator when the noise-cancellation signal corresponds to a first sign, and the single-pole double-throw switch is further configured to steer the intermediate current signal to the negative input terminal of the integrator when the noise-cancellation signal corresponds to a second sign.

8. The self-calibration circuit of claim 1, wherein the modulator comprises a one-order delta-sigma modulator.

9. The self-calibration circuit of claim 1, wherein the controllable oscillator is a voltage controlled oscillator.

10. The self-calibration circuit as claimed in claim 1, wherein the clock divider is a counter.