CN107845371B - Power management integrated circuit and liquid crystal panel - Google Patents
Power management integrated circuit and liquid crystal panel Download PDFInfo
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- CN107845371B CN107845371B CN201710948937.5A CN201710948937A CN107845371B CN 107845371 B CN107845371 B CN 107845371B CN 201710948937 A CN201710948937 A CN 201710948937A CN 107845371 B CN107845371 B CN 107845371B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/025—Reduction of instantaneous peaks of current
Abstract
The invention provides a power management integrated circuit and a liquid crystal panel. The power management integrated circuit is characterized in that a logic control module (1), an interface module (2) and an RC selection module (3) are additionally arranged in a power management chip (IC1), and the interface module (2) is used for selecting the conduction of a corresponding RC circuit unit (L) in the RC selection module (3) according to the condition of parasitic inductance in a current pump line (CP) so as to control the opening speed and the source-drain on-state resistance of a first field-effect tube (Q1) or a second field-effect tube (Q2) and prevent the current pump line (CP) from generating large current due to the parasitic inductance; the logic control module (1) controls the conduction and the cut-off of the first field effect transistor (Q1) or the second field effect transistor (Q2) through the conducted RC circuit unit (L); the power-on high current can be avoided from being caused by parasitic inductance in a current pump Circuit (CP), and the power management integrated circuit is prevented from being burnt out by the power-on high current.
Description
Technical Field
The invention relates to the technical field of display, in particular to a power management integrated circuit and a liquid crystal panel.
Background
A Liquid Crystal Display panel (LCD), which is referred to as a Liquid Crystal panel for short, has many advantages of thin body, power saving, no radiation, etc., and is widely used, for example: liquid crystal televisions, smart phones, digital cameras, tablet computers, computer screens, or notebook computer screens, etc., are dominant in the field of flat panel displays.
The liquid crystal panel operates on the principle that liquid crystal molecules are filled between a Thin Film Transistor Array Substrate (TFT Array Substrate) and a Color Filter Substrate (Color Filter, CF), and driving voltages are applied to the two substrates to control the rotation direction of the liquid crystal molecules, so that light rays of the backlight module are refracted out to generate a picture.
The driving of the liquid crystal panel requires a driving voltage VGH. In the prior art, VGH is generally generated by using a current Pump (Charge Pump) line in a power management integrated circuit, and the architecture has low cost and simple implementation and is the most common topology structure at present.
Referring to fig. 1, a conventional power management integrated circuit includes a power management chip IC10 and a current pump circuit CP 10. The power management chip IC10 includes an N-channel MOS transistor Q10, a P-channel MOS transistor Q20, and a driving pin DRVP; the current pump line CP10 is composed of a first diode D10, a second diode D20, a first capacitor C10, a second capacitor C20, and a third capacitor C30. The current pump line CP10 is electrically connected to an N-channel MOS transistor Q10, a P-channel MOS transistor Q20, and a driving pin DRVP, and the N-channel MOS transistor Q10 and the P-channel transistor Q20 perform time-sharing control on the current pump line CP 10. The current pump line CP10 generates the final required voltage by the change of the high and low potentials of the driving pin DRVP through the current pump function of the first capacitor C10, but the current pump line CP10 generates parasitic inductances L10, L20, and L30 in the dense circuit layout (layout) due to external wiring, so that when the N-channel MOS Q10 is turned on and off due to the establishment of the power supply voltage AVDD, a large current passes through the parasitic inductances L10 and L20, and when the P-channel MOS Q20 is turned on and off, a large current passes through the parasitic inductances L30 and L20, which may cause the damage of the driving pin DRVP and the damage of other logic elements inside the power management chip IC 10. For example, when the current pump line CP10 starts to operate, the N-channel MOS transistor Q10 is turned on, and then a large current passes through the current pump line CP10 because neither the first capacitor C10 nor the second capacitor C20 is charged, and after the N-channel MOS transistor Q10 is turned off, a large amount of energy is stored in the second inductor L20, which causes the voltage on the driving pin DRVP to rise.
The larger the parasitic inductance, the larger the energy accumulated on the inductance, and the greater the corresponding hazard, the generation of the parasitic inductance is inevitable due to the existence of the circuit trace, and as the Printed Circuit Board Assembly (PCBA) becomes smaller and smaller, the parasitic parameters become larger and larger, and it is very necessary to improve the existing power management integrated circuit.
Disclosure of Invention
The invention aims to provide a power management integrated circuit, which can avoid the large current caused by the parasitic inductance in a current pump circuit when the power is turned on and prevent the power management integrated circuit from being burnt out by the large current when the power is turned on.
Another objective of the present invention is to provide a liquid crystal panel, in which the power management ic is more stable and reliable.
To achieve the above object, the present invention provides a power management integrated circuit, which includes a power management chip and a current pump circuit connected to the power management chip, wherein the power management chip includes: the device comprises a logic control module, an interface module, an RC selection module, a first field effect transistor and a second field effect transistor;
the logic control module is electrically connected with the interface module; the input end of the RC selection module is electrically connected with the logic control module and the interface module; the grid electrode of the first field effect transistor is electrically connected with the output end of the RC selection module, the source electrode of the first field effect transistor is grounded, and the drain electrode of the first field effect transistor is electrically connected with the driving pin; the grid electrode of the second field effect transistor is electrically connected with the output end of the RC selection module, and the source electrode of the second field effect transistor is electrically connected with the driving pin; the current pump circuit is electrically connected with the driving pin and the drain electrode of the second field effect transistor; the conduction potentials of the first field effect transistor and the second field effect transistor are opposite;
the RC selection module comprises a plurality of RC circuit units which are connected in parallel, and the resistance values and the capacitance values of the RC circuit units are different;
the interface module selects a corresponding RC circuit unit to be conducted according to the condition of parasitic inductance in the current pump circuit so as to control the opening speed and the source-drain on-state resistance of the first field effect transistor or the second field effect transistor and prevent the current pump circuit from generating large current due to the parasitic inductance;
the logic control module is used for controlling the conduction and the cut-off of the first field effect transistor or the second field effect transistor through the conducted RC circuit unit.
The current pump circuit comprises a first capacitor, a second capacitor, a third capacitor, a first diode and a second diode;
one end of the first capacitor is electrically connected with the driving pin, and the other end of the first capacitor is electrically connected with the node; the anode of the first secondary tube is electrically connected with the drain electrode of the second field effect tube, and the cathode of the first secondary tube is electrically connected with the node; the anode of the second diode is electrically connected with the node, and the cathode of the second diode is electrically connected with one end of the second capacitor; the other end of the second capacitor is grounded; one end of the third capacitor is electrically connected with the drain electrode of the second field effect transistor, and the other end of the third capacitor is grounded.
The interface module is an I2C interface.
Each RC circuit unit comprises a resistor, a control switch connected with the resistor in series and a capacitor, one end of the capacitor is electrically connected between the resistor and the control switch, and the other end of the capacitor is grounded; the interface module is used for controlling the control switch of the corresponding RC circuit unit to be closed so as to conduct the RC circuit unit.
The RC selection module comprises three RC circuit units which are connected in parallel; the first RC circuit unit comprises a first resistor, a first control switch connected with the first resistor in series, and a first branch capacitor, one end of the first branch capacitor is electrically connected between the first resistor and the first control switch, and the other end of the first branch capacitor is grounded; the second RC circuit unit comprises a second resistor, a second control switch connected with the second resistor in series, and a second branch capacitor with one end electrically connected between the second resistor and the second control switch and the other end grounded; the third RC circuit unit comprises a third resistor, a third control switch connected with the third resistor in series, and a third branch capacitor, one end of the third branch capacitor is electrically connected between the third resistor and the third control switch, and the other end of the third branch capacitor is grounded.
The interface module controls a first control switch of a first RC circuit unit in the RC selection module to be closed by using binary number 00, and a first resistor and a first branch capacitor work; using binary number 01 to control a second control switch of a second RC circuit unit in the RC selection module to be closed, and enabling a second resistor and a second branch capacitor to work; and controlling a third control switch of a third RC circuit unit in the RC selection module to be closed by using the binary number 10, and enabling a third resistor and a third branch capacitor to work.
The first field effect transistor is an N-channel MOS transistor, and the second field effect transistor is a P-channel MOS transistor.
The invention also provides a liquid crystal panel which comprises the power management integrated circuit.
The invention has the beneficial effects that: compared with the prior art, the power management integrated circuit provided by the invention has the advantages that the logic control module, the interface module and the RC selection module are additionally arranged in the power management chip, and the interface module is used for selecting the corresponding RC circuit unit in the RC selection module to be conducted according to the parasitic inductance condition in the current pump circuit so as to control the opening speed and the source-drain on-state resistance of the first field effect tube or the second field effect tube; the logic control module controls the conduction and the cut-off of the first field effect tube or the second field effect tube through the conducted RC circuit unit; the power-on high current can be prevented from being caused by parasitic inductance in a current pump circuit, and the power management integrated circuit is prevented from being burnt out by the power-on high current. The liquid crystal panel provided by the invention comprises the power management integrated circuit, so that the large power-on current caused by parasitic inductance in a current pump circuit can be avoided, and the power management integrated circuit is prevented from being burnt out by the large power-on current.
Drawings
For a better understanding of the nature and technical aspects of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are provided for purposes of illustration and description and are not intended to limit the invention.
In the drawings, there is shown in the drawings,
FIG. 1 is a circuit diagram of a prior art power management integrated circuit;
FIG. 2 is a circuit diagram of a power management integrated circuit according to the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Referring to fig. 2, the present invention provides a power management integrated circuit, which includes a power management chip IC1 and a current pump circuit CP connected to the power management chip IC 1.
Wherein the power management chip IC1 includes: the controller comprises a logic control module 1, an interface module 2, an RC selection module 3, a first field effect transistor Q1 and a second field effect transistor Q2.
The logic control module 1 is electrically connected with the interface module 2.
The conducting potential of the first field effect transistor Q1 is opposite to that of the second field effect transistor Q2. Preferably, the first field effect transistor Q1 is an N-channel MOS transistor, and the second field effect transistor Q2 is a P-channel MOS transistor.
The interface module 2 is preferably an Inter-Integrated Circuit bus (I2C) interface.
The input end of the RC selection module 3 is electrically connected with the logic control module 1 and the interface module 2. The RC selecting module 3 includes a plurality of RC circuit units L connected in parallel, each RC circuit unit L includes a resistor, a control switch connected in series with the resistor, and a capacitor having one end electrically connected between the resistor and the control switch and the other end grounded, and the resistance and capacitance of each RC circuit unit L are different. For example, the RC selecting module 3 may include, but is not limited to, three RC circuit units L connected in parallel with each other; the first RC circuit unit L comprises a first resistor R1, a first control switch S1 connected in series with the first resistor R1, and a first branch capacitor C1' having one end electrically connected between the first resistor R1 and the first control switch S1 and the other end grounded; the second RC circuit unit L comprises a second resistor R2, a second control switch S2 connected in series with the second resistor R2, and a second branch capacitor C2' having one end electrically connected between the second resistor R2 and the second control switch S2 and the other end grounded; the third RC circuit unit L includes a third resistor R3, a third control switch S3 connected in series with the third resistor R3, and a third branch capacitor C3' having one end electrically connected between the third resistor R3 and the third control switch S3 and the other end grounded. The node where the first resistor R1, the second resistor R2 and the third resistor R3 are connected in parallel is the input end of the RC selecting module 3, and the node where the first control switch S1, the second control switch S2 and the third control switch S3 are connected in parallel is the output end of the RC selecting module 3.
The gate of the first field effect transistor Q1 is electrically connected to the output terminal of the RC selection module 3, the source is grounded, and the drain is electrically connected to the driving pin DRVP.
The gate of the second fet Q2 is electrically connected to the output terminal of the RC selection module 3, and the source is electrically connected to the driving pin DRVP.
The current pump line CP is electrically connected to the driving pin DRVP and the drain of the second field effect transistor Q2. Specifically, the current pump line CP includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a first diode D1, and a second diode D2. One end of the first capacitor C1 is electrically connected to the driving pin DRVP, and the other end is electrically connected to the node a; the anode of the first diode D1 is electrically connected with the drain of the second field effect transistor Q2, and the cathode of the first diode D1 is electrically connected with the node A; the anode of the second diode D2 is electrically connected with the node A, and the cathode of the second diode D2 is electrically connected with one end of the second capacitor C2; the other end of the second capacitor C2 is grounded; one end of the third capacitor C3 is electrically connected to the drain of the second fet Q2, and the other end is grounded. The current pump line CP utilizes the current pump function of the first capacitor C1 to generate the finally required voltage by the variation of high and low voltages on the driving pin DRVP, and of course, the current pump line CP inevitably generates parasitic inductances L1, L2 and L3 due to external wiring in a dense circuit layout.
The interface module 2 controls the control switch of one RC circuit unit L in the RC selecting module 3 to be closed according to its internal instruction so as to select the RC circuit unit L to be turned on. Receiving an example that the RC selecting module 3 includes three RC circuit units L connected in parallel, the interface module 2 controls the first control switch S1 of the first RC circuit unit L in the RC selecting module 3 to close using binary number 00, and the first resistor R1 works with the first branch capacitor C1'; a binary number 01 is used for controlling a second control switch S2 of a second RC circuit unit L in the RC selection module 3 to be closed, and a second resistor R2 and a second branch capacitor C2' work; the binary number 10 is used to control the third control switch S3 of the third RC circuit unit L in the RC selecting module 3 to close, and the third resistor R3 and the third branch capacitor C3' work.
The logic control module 1 is used for controlling the on and off of the first field effect transistor Q1 or the second field effect transistor Q2 through the turned-on RC circuit unit L.
Due to the characteristics of the RC circuit, when a certain RC circuit unit L is turned on, a certain time process is required for charging the corresponding branch capacitor in the RC circuit unit L, the voltage output by the corresponding branch capacitor is gradually increased along with the time, so that the opening degree of the first field effect transistor Q1 or the second field effect transistor Q2 is gradually increased, the source drain on-state resistance (RDS (on)) is gradually reduced, there is also a gradual change in the current flowing through the first fet Q1 or the second fet Q2, even if the first fet Q1 or the second fet Q2 is turned on at a constant turn-on speed due to the establishment of the power supply voltage AVDD when the liquid crystal panel is turned on, no large current occurs, therefore, the parasitic inductors L1, L2, and L3 do not store much energy, and damage to the driving pin DRVP and other logic components inside the power management ic is prevented.
The interface module 2 can control the turn-on speed and the source-drain on-state resistance of the first fet Q1 or the second fet Q2 by controlling the conduction of different RC circuit units L according to the condition of parasitic inductance in the current pump line CP, for example, the first turn-on speed and the source-drain on-state resistance of the first fet Q1 or the second fet Q2 are obtained by controlling the conduction of the first RC circuit unit L, the second turn-on speed and the source-drain on-state resistance of the first fet Q1 or the second fet Q2 are obtained by controlling the conduction of the second RC circuit unit L, the third turn-on speed and the source-drain on-state resistance of the first fet Q1 or the second fet Q2 are obtained by controlling the conduction of the third RC circuit unit L, so that the current pump line CP can be prevented from generating large current due to the parasitic inductance, and thus can be prevented from generating large turn-on current due to the parasitic inductance in the current pump line CP, the power management integrated circuit is prevented from being burnt out by large current during startup.
Based on the same inventive concept, the present invention further provides a liquid crystal panel, which includes the above-mentioned power management integrated circuit shown in fig. 2, which is more stable and reliable, and will not be described repeatedly herein.
In summary, compared with the prior art in which a logic control module, an interface module, and an RC selection module are added in a power management chip, the interface module selects a corresponding RC circuit unit in the RC selection module to be turned on according to the condition of parasitic inductance in a current pump line, so as to control the turn-on speed and the source-drain on-state resistance of a first field effect transistor or a second field effect transistor; the logic control module controls the conduction and the cut-off of the first field effect tube or the second field effect tube through the conducted RC circuit unit; the power-on high current can be prevented from being caused by parasitic inductance in a current pump circuit, and the power management integrated circuit is prevented from being burnt out by the power-on high current. The liquid crystal panel comprises the power management integrated circuit, so that the large power-on current caused by parasitic inductance in a current pump circuit can be avoided, and the power management integrated circuit is prevented from being burnt by the large power-on current.
As described above, it will be apparent to those skilled in the art that other various changes and modifications may be made based on the technical solution and concept of the present invention, and all such changes and modifications should fall within the scope of the claims of the present invention.
Claims (8)
1. A power management integrated circuit comprising a power management chip (IC1) and a current pump line (CP) connected to the power management chip (IC1), wherein the power management chip (IC1) comprises: the device comprises a logic control module (1), an interface module (2), an RC selection module (3), a first field effect transistor (Q1) and a second field effect transistor (Q2);
the logic control module (1) is electrically connected with the interface module (2); the input end of the RC selection module (3) is electrically connected with the logic control module (1) and the interface module (2); the grid electrode of the first field effect transistor (Q1) is electrically connected with the output end of the RC selection module (3), the source electrode is grounded, and the drain electrode is electrically connected with a driving pin (DRVP); the grid electrode of the second field effect transistor (Q2) is electrically connected with the output end of the RC selection module (3), and the source electrode of the second field effect transistor is electrically connected with a driving pin (DRVP); the current pump line (CP) is electrically connected with the drive pin (DRVP) and the drain electrode of the second field effect transistor (Q2); the conducting potentials of the first field effect transistor (Q1) and the second field effect transistor (Q2) are opposite;
the RC selection module (3) comprises a plurality of RC circuit units (L) which are connected in parallel, and the resistance values and the capacitance values of the RC circuit units (L) are different;
the interface module (2) selects a corresponding RC circuit unit (L) to be conducted according to the condition of parasitic inductance in the current pump line (CP) so as to control the opening speed and the source-drain on-state resistance of the first field-effect tube (Q1) or the second field-effect tube (Q2) and prevent the current pump line (CP) from generating large current due to the parasitic inductance;
the logic control module (1) is used for controlling the on and off of the first field effect transistor (Q1) or the second field effect transistor (Q2) through the turned-on RC circuit unit (L).
2. The power management integrated circuit of claim 1, wherein the current pump line (CP) comprises a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a first diode (D1), and a second diode (D2);
one end of the first capacitor (C1) is electrically connected with the driving pin (DRVP), and the other end is electrically connected with the node (A); the anode of the first secondary transistor (D1) is electrically connected with the drain of the second field effect transistor (Q2), and the cathode of the first secondary transistor is electrically connected with the node (A); the anode of the second diode (D2) is electrically connected with the node (A), and the cathode of the second diode is electrically connected with one end of the second capacitor (C2); the other end of the second capacitor (C2) is grounded; one end of the third capacitor (C3) is electrically connected with the drain electrode of the second field effect transistor (Q2), and the other end is grounded.
3. A power management integrated circuit according to claim 1, wherein the interface module (2) is an I2C interface.
4. A power management integrated circuit according to claim 3, characterized in that each RC circuit cell (L) comprises a resistor, a control switch connected in series with said resistor, and a capacitor electrically connected between said resistor and said control switch at one end and grounded at the other end; the interface module (2) is closed by controlling a control switch of the corresponding RC circuit unit (L) to conduct the RC circuit unit (L).
5. Power management integrated circuit according to claim 4, characterized in that said RC selection module (3) comprises three RC circuit cells (L) connected in parallel with each other; the first RC circuit unit (L) comprises a first resistor (R1), a first control switch (S1) connected with the first resistor (R1) in series, and a first branch capacitor (C1') with one end electrically connected between the first resistor (R1) and the first control switch (S1) and the other end grounded; the second RC circuit unit (L) comprises a second resistor (R2), a second control switch (S2) connected with the second resistor (R2) in series, and a second branch capacitor (C2') with one end electrically connected between the second resistor (R2) and the second control switch (S2) and the other end grounded; the third RC circuit unit (L) comprises a third resistor (R3), a third control switch (S3) connected with the third resistor (R3) in series, and a third branch capacitor (C3') with one end electrically connected between the third resistor (R3) and the third control switch (S3) and the other end grounded.
6. The power management integrated circuit according to claim 5, characterized in that the interface module (2) controls the closure of the first control switch (S1) of the first RC circuit cell (L) within the RC selection module (3) using the binary number 00, the first resistor (R1) operating with the first branch capacitor (C1'); a binary number 01 is used for controlling a second control switch (S2) of a second RC circuit unit (L) in the RC selection module (3) to be closed, and a second resistor (R2) works with a second branch capacitor (C2'); and controlling a third control switch (S3) of a third RC circuit unit (L) in the RC selection module (3) to be closed by using the binary number 10, and operating a third resistor (R3) and a third branch capacitor (C3').
7. The power management integrated circuit of claim 1, wherein the first field effect transistor (Q1) is an N-channel MOS transistor and the second field effect transistor (Q2) is a P-channel MOS transistor.
8. A liquid crystal panel comprising the power management integrated circuit as claimed in any one of claims 1 to 7.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710948937.5A CN107845371B (en) | 2017-10-12 | 2017-10-12 | Power management integrated circuit and liquid crystal panel |
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| CN201710948937.5A CN107845371B (en) | 2017-10-12 | 2017-10-12 | Power management integrated circuit and liquid crystal panel |
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| CN107845371A CN107845371A (en) | 2018-03-27 |
| CN107845371B true CN107845371B (en) | 2020-04-03 |
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| KR20110007529A (en) * | 2009-07-16 | 2011-01-24 | 삼성전자주식회사 | Source driver and display apparatus comprising the same |
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| KR100632211B1 (en) * | 2005-08-31 | 2006-10-09 | 엘지전자 주식회사 | Driving apparatus of plasma display panel wherein characteristics of gate current are enhanced |
| CN102769451A (en) * | 2011-05-06 | 2012-11-07 | 夏普株式会社 | Semiconductor device and electronic device |
| CN102253286A (en) * | 2011-06-27 | 2011-11-23 | 郑军 | Resistance/capacitance measuring method and device thereof |
| CN106646181A (en) * | 2016-11-24 | 2017-05-10 | 瑞能半导体有限公司 | Thyristor test circuit and thyristor test method |
| CN106972841A (en) * | 2017-04-25 | 2017-07-21 | 中国工程物理研究院流体物理研究所 | A kind of simplified pulse shaping circuit and LTD modules |
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| CN107845371A (en) | 2018-03-27 |
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