CN107844665A - A kind of factory's logic chart design method and logic chart - Google Patents
A kind of factory's logic chart design method and logic chart Download PDFInfo
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- CN107844665A CN107844665A CN201711187020.4A CN201711187020A CN107844665A CN 107844665 A CN107844665 A CN 107844665A CN 201711187020 A CN201711187020 A CN 201711187020A CN 107844665 A CN107844665 A CN 107844665A
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Abstract
The invention discloses a kind of factory's logic chart design method and logic chart, wherein, a kind of factory's logic chart design method, comprise the following steps：Step 1：Statistics be originally inputted a little with final output point；Step 2：Design logic relation, count middle output point and intermediate input point；Step 3：Design logic relation is continued according to middle output point and intermediate input point, the design until completing logical relation；Step 4：It is determined that middle output point and intermediate input point write address；Step 5：The address of connected intermediate input point is marked on each middle output point according to numbering, the address of connected middle output point is marked on each intermediate input point according to numbering, the logic chart of this method design, in later stage trouble hunting, the annexation time between signal is searched by logic chart, it can quickly investigate thoroughly and look for bright annexation, and then the source of trouble can be quickly found out, it is time saving and energy saving.
Description
Technical field
The present invention relates to DCS in factory design field, and in particular to a kind of factory's logic chart design method and logic chart.
Background technology
Need to carry out the design of logic chart in DCS in factory design process, input signal, defeated is generally included in current logic figure
The logical relation three parts for going out signal and being connected between input signal and output signal.Designed in DCS in factory design process
Logic chart be additionally operable to the trouble hunting in later stage, i.e., the annexation between signal is searched by logic chart, searches the source of trouble, when
When logic chart quantity is more, the annexation between signal is searched very bothersome laborious.
In consideration of it, special propose this invention.
The content of the invention
For the deficiencies in the prior art, it is an object of the invention to provide a kind of factory's logic chart design method,
It is easy to post facility quickly to search the annexation between signal when overhauling.
The technical proposal of the invention is realized in this way：
A kind of factory's logic chart design method, comprises the following steps：Step 1：Statistics is originally inputted a little with final output point, and is remembered
Enter logic chart, be originally inputted and be a little an externally input a little, such as by the input point that is gathered in sensor and be manually entered a little, most
Whole output point is outside output point, the control point such as exported to relay actuator；Step 2：Design logic relation, in statistics
Between output point and intermediate input point, and charge to logic chart, middle output point and intermediate input point for it is internal be connected with each other input, it is defeated
Go out a little, in the process of design logic relation, middle output point and the intermediate input point of interconnection write and is identically numbered,
And charge to logic chart；Step 3：Design logic relation is continued according to middle output point and intermediate input point, closed until completing logic
The design of system, in the process of design logic relation, identical is write to middle output point and the intermediate input point of interconnection
Numbering；Step 4：It is determined that middle output point and intermediate input point write address；Step 5：According to numbering on each middle output point
The address of connected intermediate input point is marked, is marked on each intermediate input point according to numbering and is exported among connected
The address of point, the logic chart of this method design, mark has the address of middle output point on intermediate input point,
Mark has the address of intermediate input point on middle output point, in later stage trouble hunting, is searched and believed by logic chart
The annexation time between number, it can quickly investigate thoroughly and look for bright annexation, and then the source of trouble can be quickly found out, time saving province
Power, on the other hand, middle output point and the intermediate input point of interconnection is write and is identically numbered, and according to numbering in each
Between the address of connected intermediate input point is marked on output point, and mark connects with it on each intermediate input point according to numbering
The address of the middle output point connect, can improve accuracy during tag address.
Further, in step 2 and step 3, during design logic relational process, numbered using KKS, to the centre of interconnection
Output point and intermediate input point are write and are identically numbered.
Further, in step 1, a little it is numbered to being originally inputted with final output point.
Further, in step 1, numbered using KKS, be a little numbered to being originally inputted with final output point.
Further, the address of connected intermediate input point is marked on each middle output point in accordance with the following steps：Step
Rapid 5.1：Check the numbering of middle output point；Step 5.2：The intermediate input point with identical numbering is searched, and is write down the address；Step
Rapid 5.3：The address of connected intermediate input point is marked on middle output point.
Further, the address of connected middle output point is marked on each intermediate input point as follows：Step
Rapid 5.4：Check the numbering of intermediate input point；Step 5.5：The middle output point with identical numbering is searched, and is write down the address；Step
Rapid 5.6：The address of connected middle output point is marked on intermediate input point.
Further, the present invention also provides a kind of logic chart, including input signal information row, logical relation row and output signal
Information arranges, between the connection of logical relation row and input signal information row and output signal information row.
Further, input signal information row include source address row, input signal numbering row and input signal address column,
Output signal information row include whereabouts address column, output signal numbering row and output signal address column, and source address, which arranges, to be used for
The address for the middle output point being connected with each intermediate input point is filled in, whereabouts address column is used to fill in be connected with each middle output point
Intermediate input point address, input signal numbering row be used for fill in be originally inputted a little and intermediate input point numbering, export
Signal numbering row are used for the numbering for filling in final output point and middle output point, and input signal address column is used to be originally inputted a little
And the address of intermediate input point, output signal address column are used for the address of final output point and middle output point.
Further, between the connection of logical relation row and input signal address column and output signal address column.
The beneficial effects of the invention are as follows：
（1）The logic chart of this method design, mark has the address of middle output point on intermediate input point, in
Between on output point mark have the address of intermediate input point, in later stage trouble hunting, signal is searched by logic chart
Between the annexation time, can quickly investigate thoroughly and look for bright annexation, and then the source of trouble can be quickly found out, it is time saving and energy saving.
（2）Middle output point and the intermediate input point of interconnection is write and is identically numbered, and according to numbering in each
Between the address of connected intermediate input point is marked on output point, and mark connects with it on each intermediate input point according to numbering
The address of the middle output point connect, can improve accuracy during tag address.
Brief description of the drawings
Fig. 1 is logic chart 1；
Fig. 2 is logic chart 2；
Fig. 3 is logic chart 3.
Embodiment
In order that those skilled in the art more fully understand technical scheme, with reference to embodiments of the invention,
Clear, complete description is carried out to technical scheme, based on the embodiment in the application, those of ordinary skill in the art
The other similar embodiments obtained on the premise of creative work is not made, it should all belong to the model of the application protection
Enclose.
Embodiment one：
Design in accordance with the following steps and draw the logic chart of factory liquid level of steam drum DCS controls, step 1：Draw initial logic figure（I.e.
Empty graph, for being inserted during late design）, initial logic figure, which includes input signal information row, logical relation row and output signal, to be believed
Breath row, input signal information row include source address row, input signal numbering row and input signal address column, output signal letter
Breath row include whereabouts address column, output signal numbering row and output signal address column, in input signal address column from top to bottom
1-45 is inserted successively, and specific numeral represents input signal（Original input signal and intermediate input signal）In the logic chart
Location, 46-90 is inserted successively from top to bottom in output signal address column, specific numeral represents output signal（Final output signal and
Intermediate output signal）The address in the logic chart, the number are the preferable number of the present embodiment, can also insert it as needed
His number.
Step 2：Statistics is originally inputted a little, is a little numbered using KKS numberings to being originally inputted, and is included in input signal volume
Number row, count final output point, using KKS numbering final output point is numbered, and be included in input signal numbering row.
Step 3：Design logic relation, and logical relation is included in logical relation row, during design logic relation,
Output point among statistics, middle output point is numbered using KKS numberings, and is included in output signal numbering row, meanwhile, statistics
Intermediate input point, middle input point is numbered using KKS numberings, and is included in input signal numbering row.
Step 4：Design logic relation is continued according to middle output point and intermediate input point, and logical relation is included in logic
Relation arranges, the design until completing logical relation, during design logic relation, counts middle output point, is compiled using KKS
Number middle output point is numbered, and is included in output signal numbering row, meanwhile, intermediate input point is counted, uses KKS numberings pair
Intermediate input point is numbered, and is included in input signal numbering row, and the present embodiment is completed to patrol using 3 altogether during logical relation design
Figure is collected, writes figure number respectively：Logic chart 1, logic chart 2 and logic chart 3.
Step 5：Determine the address of each middle output point and intermediate input point, figure number and specific logic of the address by logic chart
Address in figure is characterized jointly.
Step 6：The numbering of middle output point is checked one by one, then searches the intermediate input point with identical numbering, and remember
The address of intermediate input point with identical numbering down, address is included in the position of intermediate output signal corresponding to whereabouts address column
Put.
Step 7：The numbering of intermediate input point is checked one by one, then searches the middle output point with identical numbering, and remember
The address of middle output point with identical numbering down, address is included in the position of intermediate input signal corresponding to source address row
Put.
Moreover, it will be appreciated that although the present specification is described in terms of embodiments, not each embodiment is only wrapped
Containing an independent technical scheme, this narrating mode of specification is only that those skilled in the art should for clarity
Using specification as an entirety, the technical solutions in the various embodiments may also be suitably combined, forms those skilled in the art
It is appreciated that other embodiment.
Claims (9)
1. a kind of factory's logic chart design method, comprises the following steps：Step 1：Statistics be originally inputted a little with final output point, and
Charge to logic chart；Step 2：Design logic relation, middle output point and intermediate input point are counted, and charge to logic chart；Step 3：
Design logic relation is continued according to middle output point and intermediate input point, the design until completing logical relation, it is characterised in that
In step 2 and step 3, during the process of design logic relation, middle output point and the intermediate input point of interconnection is write
It is identically numbered, also comprises the following steps after step 3, step 4：It is determined that middle output point and intermediate input point write address；Step
Rapid 5：The address of connected intermediate input point is marked on each middle output point according to numbering, it is defeated in each centre according to numbering
The address of connected middle output point is marked in access point.
A kind of 2. factory's logic chart design method according to claim 1, it is characterised in that in step 2 and step 3, if
When counting logical relation process, numbered using KKS, identical volume is write to middle output point and the intermediate input point of interconnection
Number.
3. a kind of factory's logic chart design method according to claim 1, it is characterised in that in step 1, to being originally inputted
Point and final output point are numbered.
4. a kind of factory's logic chart design method according to claim 3, it is characterised in that in step 1, compiled using KKS
Number, a little it is numbered to being originally inputted with final output point.
5. a kind of factory's logic chart design method according to claim 1, it is characterised in that in accordance with the following steps in each
Between the address of connected intermediate input point is marked on output point：Step 5.1：Check the numbering of middle output point；Step
5.2：The intermediate input point with identical numbering is searched, and is write down the address；Step 5.3：Mark on middle output point and connect with it
The address of the intermediate input point connect.
6. a kind of factory's logic chart design method according to claim 1, it is characterised in that as follows in each
Between the address of connected middle output point is marked in input point：Step 5.4：Check the numbering of intermediate input point；Step
5.5：The middle output point with identical numbering is searched, and is write down the address；Step 5.6：Mark on intermediate input point and connect with it
The address of the middle output point connect.
7. a kind of logic chart of any described factory's logic chart design method designs of 1-6 is required according to profit, it is characterised in that bag
Include input signal information row, logical relation row and output signal information row, logical relation row connection with input signal information row with
Between output signal information row.
8. a kind of logic chart according to profit requires 7, it is characterised in that input signal information row include source address and arrange, be defeated
Enter signal numbering row and input signal address column, output signal information row includes whereabouts address column, output signal numbering arrange with
And output signal address column, source address arrange the address for filling in the middle output point being connected with each intermediate input point, whereabouts
Address column is used for the address for filling in the intermediate input point being connected with each middle output point, and input signal numbering row are original for filling in
The numbering of input point and intermediate input point, output signal numbering row are used for the volume for filling in final output point and middle output point
Number, input signal address column be used for be originally inputted a little and intermediate input point address, output signal address column be used for finally it is defeated
Go out a little and middle output point address.
9. according to profit require 8 described in a kind of logic chart, it is characterised in that logical relation row connection with input signal address column with
Between output signal address column.
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| CN201711187020.4A CN107844665A (en) | 2017-11-24 | 2017-11-24 | A kind of factory's logic chart design method and logic chart |
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| CN201711187020.4A CN107844665A (en) | 2017-11-24 | 2017-11-24 | A kind of factory's logic chart design method and logic chart |
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Application publication date: 20180327 |