CN107483178A - A kind of device and smart card for realizing Secure Hash Algorithm SHA3 - Google Patents
A kind of device and smart card for realizing Secure Hash Algorithm SHA3 Download PDFInfo
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- CN107483178A CN107483178A CN201710613047.9A CN201710613047A CN107483178A CN 107483178 A CN107483178 A CN 107483178A CN 201710613047 A CN201710613047 A CN 201710613047A CN 107483178 A CN107483178 A CN 107483178A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0643—Hash functions, e.g. MD5, SHA, HMAC or f9 MAC
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/3001—Arithmetic instructions
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30029—Logical and Boolean instructions, e.g. XOR, NOT
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30054—Unconditional branch instructions
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Abstract
The present invention relates to a kind of device and smart card for realizing Secure Hash Algorithm SHA3.Including：Control module, computing module, memory module, control module is used to receive peripheral operation instruction, a peripheral operation instruction is often received, send corresponding control signal according to peripheral operation instruction completes required movement to computing module and memory module, computing module and memory module according to control signal；Computing module completes each basic logic operations according to the control signal received；Memory module is used for the intermediate result for storing each step computing, and the storage location of intermediate result is provided by control signal.Because the present invention uses the mode of microprocessor framework to realize that the combinational logic used is very few, therefore shared chip area is also very small, and low in energy consumption；Because the deposit position of all intermediate data of algorithm all can be defined freely, the flexibility ratio used is greatly improved, is adapted to the application of smart card.
Description
Technical field
The present invention relates to field of information security technology, realizes Secure Hash Algorithm SHA3's more specifically to a kind of
Device and smart card.
Background technology
In the rapid development epoch of current electronic information technology, in field of telecommunications, financial field, field of traffic, medical treatment neck
Domain, governmental domains, also many enterprise, mechanism, office, hotel, public place of entertainment, tourist attractions, residential quarter and schools etc. are all
Smart card is taken as the instrument for improving the efficiency of management.Smart card has good security feature, while has and be easy to carry, makes
The features such as with facilitating.
Just due to its application, it is extensive, and development is rapid, so usually have very high requirement for its security,
There are the Secure Hash Algorithm such as many MD5, SHA0, SHA1 in conventional smart card, due to occurring successfully cracking to MD5, with
And to the method that cracking in theory occurs in SHA0 and SHA1, therefore in order to meet the security requirement of various application scenarios, intelligence
Card needs to update Secure Hash Algorithm (Secure Hash Algorithm, SHA) SHA3 of a new generation, is counted from SHA3 algorithms
Two aspects of performance and the symmetry of round function are tested it, the results showed that SHA3 algorithm avalanche effects are good, average to become
Change bit number and all very close ideal value of mean change probability, and variance is smaller has higher stability and relatively low collision
Degree.Because SHA3 algorithms are that the data of 1600 bits are handled, per treatment have a five step interative computations, at every piece of message
Reason 24 times, therefore SHA3 algorithms are very to consume logical resource, it is impossible to meet smart card demand, for the area and work(of chip
Consumption has quite harsh requirement, and this requires SHA3 hardware structure to have the requirement of low-power consumption small area.
The content of the invention
The technical problem to be solved in the present invention is, big, no for the above-mentioned SHA3 algorithms area and power consumption of prior art
A kind of the defects of smart card demand can be met, there is provided device and smart card for realizing Secure Hash Algorithm SHA3.
The technical solution adopted for the present invention to solve the technical problems is：Construct and a kind of realize Secure Hash Algorithm SHA3's
Device, including：Control module, computing module, memory module, wherein,
The control module is used to receive peripheral operation instruction, a peripheral operation instruction is often received, according to described
Peripheral operation instruction sends corresponding control signal to the computing module and memory module, the computing module and memory module
Required movement is completed according to the control signal；
The computing module completes each basic logic operations according to the control signal received；
The memory module is used for the intermediate result for storing each step computing, and the storage location of the intermediate result is by described
Control signal provides.
Preferably, the device of the present invention for realizing Secure Hash Algorithm SHA3, the logic of the basic logic operations
Operation is all handled according to 64 bits；
The memory module is the single port random access memory that storage depth is 256 and data width is 64 bits.
Preferably, the device of the present invention for realizing Secure Hash Algorithm SHA3, the basic logic operations include：Two
Input xor operation, constant xor operation, two inputs and operation, not operation and 25 kinds of shifting functions；
The shift count of 25 kinds of shifting functions is respectively：0、36、3、41、18、1、44、10、45、2、62、6、43、
15、61、28、55、25、21、56、27、20、39、8、14。
Preferably, the device of the present invention for realizing Secure Hash Algorithm SHA3, the two inputs xor operation are described
Control module performs following operate：
S1：The control module sends first operand address to the memory module, with reading the first operand
Data corresponding to location；
S2：The control module, which is sent, downloads the first data controlling signal to the computing module, and the data of reading are sent out
Deliver to the first register；
S3：The control module continues to send second operand address to the memory module, reads second operation
Data corresponding to number address；
S4：The control module, which is sent, downloads the second data controlling signal to the computing module, and the data of reading are sent out
Deliver to the second register；
S5：The control module finally sends operation result control signal, notifies the computing module to send out operation result
The memory module is given, and the control module sends the address of the operation result to the memory module simultaneously and write
Effective order.
Preferably, the device of the present invention for realizing Secure Hash Algorithm SHA3, the peripheral operation instruction are 32 ratios
Spy, including：8 bit first operand addresses, 8 bit second operand addresses, 8 bit arithmetic result addresses, 8 bits perform
Operational order.
Preferably, the device of the present invention for realizing Secure Hash Algorithm SHA3, the control module include：Idle shape
State, operational order selection state, first operand address state is loaded into, first operand state is loaded into, is loaded into second operand
Address state, it is loaded into second operand state, is loaded into result phase；
When enabling signal is invalid, the control module is in the idle condition；It is described when the enabling signal is effective
Control module jumps to the operational order selection state, and state is redirected according to low eight selections of operational order：Described low eight
When position is 0 or 1, the control module jumps to the loading first operand address state；Described low eight be 2 to 28 when,
The control module jumps to the loading second operand address state；
The control module jumps to the loading first automatically after jumping to the loading first operand address state
Number state is operated, and then jumps to the loading second operand address state automatically, further jumps to the loading automatically
Second operand state, the loading result phase is further jumped to automatically, is eventually returned to the idle condition.
Preferably, the device of the present invention for realizing Secure Hash Algorithm SHA3, the control module include：First is defeated
Incoming interface, the second input interface, the 3rd input interface, the 4th input interface, the first output interface, the second output interface, the 3rd
Output interface, the 4th output interface, the 5th output interface, the 6th output interface；
The first input interface input clock signal；Second input interface inputs reset signal, described to reset letter
Number low level is effective；3rd input circuit inputs the operational order of 32 bits；The 4th input circuit input starts letter
Number；The first output interface output takes first operand control signal；The second output interface output takes second operand
Control signal；3rd output interface exports write-back result to memory module control signal；The 4th output signal output
Computing complement mark signal；5th output interface exports memory module address control signal；6th output interface is defeated
Go out memory module read-write control signal.
Preferably, the device of the present invention for realizing Secure Hash Algorithm SHA3, the computing module include：First is defeated
Incoming interface, the second input interface, the 3rd input interface, the 4th input interface, the 5th input interface, the 6th input interface, the 7th
Input interface, the 8th input interface and the first output interface；
The first input interface input clock signal；Second input interface inputs reset signal, described to reset letter
Number low level is effective；3rd input interface inputs 64 bit arithmetic module input datas；The 4th input interface input
32 bit operatings instruct；The 5th input interface wheel for inputting number；The 6th input interface input takes first operand control
Signal；7th input interface inputs second operand control signal；8th input interface inputs write-back result to depositing
Store up module control signal；First output interface exports 64 bit arithmetic module output results.
Preferably, the device of the present invention for realizing Secure Hash Algorithm SHA3, the memory module include：First is defeated
Incoming interface, the second input interface, the 3rd input interface, the 4th input interface and the first output interface；
The first input interface input clock signal；Second input interface inputs read-write；Described 3rd is defeated
Incoming interface inputs the random access memory write-in data of 64 bits；The 4th input interface input random access memory
Location；First output interface exports 64 bit random access memories and reads data.
In addition, the present invention also constructs a kind of smart card, the smart card realizes Secure Hash Algorithm SHA3's including above-mentioned
Device.
Implement the device and smart card of realizing Secure Hash Algorithm SHA3 of the present invention, have the advantages that：The dress
Put including：Control module, computing module, memory module, wherein, control module is used to receive peripheral operation instruction, often receives one
Bar peripheral operation is instructed, and corresponding control signal is sent to computing module and memory module, computing mould according to peripheral operation instruction
Block and memory module complete required movement according to control signal；Computing module is completed each basic according to the control signal received
Logical operation；Memory module is used for the intermediate result for storing each step computing, and the storage location of intermediate result is carried by control signal
For.Because the present invention uses the mode of microprocessor framework to realize that the combinational logic used is very few, therefore shared chip
Area is also very small, and low in energy consumption.Because the deposit position of all intermediate data of algorithm all can be defined freely, greatly carry
The flexibility ratio that height uses, it is adapted to the application of smart card.
Brief description of the drawings
Below in conjunction with drawings and Examples, the invention will be further described, in accompanying drawing：
Fig. 1 is a kind of structural representation for the device for realizing Secure Hash Algorithm SHA3 of the present invention；
Fig. 2 is a kind of architecture principle schematic diagram for the device for realizing Secure Hash Algorithm SHA3 of the present invention；
Fig. 3 is a kind of state transfer schematic diagram of device for realizing Secure Hash Algorithm SHA3 of the present invention；
Fig. 4 is a kind of integral frame structure figure for the device for realizing Secure Hash Algorithm SHA3 of the present invention；
Fig. 5 is the flow signal of two input xor operations in a kind of device for realizing Secure Hash Algorithm SHA3 of the present invention
Figure.
Embodiment
In order to which technical characteristic, purpose and the effect of the present invention is more clearly understood, now compares accompanying drawing and describe in detail
The embodiment of the present invention.
The wheel computing of SHA3 algorithms is introduced first, and the wheel computing is the core of SHA3 algorithms, often takes turns computing and is divided into five
Step, second step and the 3rd step are merged into a step here and realized.The process is described with pseudo code below.
SHA3 algorithms, which are can be seen that, from the description of above false code only uses four kinds of basic logic operations：XOR, displacement,
With, it is non-.Each step logic in above-mentioned SHA3 false codes is split into specific basic logic operations now.
1, firstly for THETA computings, first calculates C [i], C [i] is made up of the XOR of five inputs, therefore is only needed here
The XOR for splitting into one two input can be to realize, implementation process is as follows：
The first step：First calculateHere will in the buffer address that result is stored in RAM
This is data cached to be named as Temp, now Temp=A [i, 0] ⊕ A [i, 1]；
Second step：Take out Temp and carry out XOR with A [i, 3], as a result continue to be stored in this buffer address, now
3rd step：Take out Temp and carry out XOR with A [i, 4], the result now obtained is exactly to need to obtain
Next D [i] is split, as can be seen that calculating the data only needs two kinds of computings, XOR from false code
And displacement, implementation process are as follows：
The first step：(C [i+1] ＜ ＜ ＜ 1) is first calculated, therefore only needs the logic of a ring shift left one, will be performed
The data of complete ring shift left one are stored in buffer address；
Second step：Take out data cached and carry out XOR with C [i-1], obtain result D [i]；
Finally A [i, j] is split, because the step only has two data to carry out XOR, so only needing one two
The XOR of input just can be realized.
2 next for RHO and PI computings, the logic with shift that the computing is only used, and the number simply shifted is different,
Be listed below all logic with shift shift counts used in the computing be respectively 0,36,3,41,18,1,44,10,45,2,62,
6th, 43,15,61,28,55,25,21,56,27,20,39,8,14 amount to 25 kinds of shift operations.
3 for CHI computings, logical operation during the computing uses three, XOR, with and it is non-, the computing is split below,
Implementation process is as follows：
The first step：Negated operation is first carried out, result is put into buffer address, it is now data cached
Second step：Carry out and operation, by it is data cached take out and with B [i+2j] carry out and logical operation, then will knot
Fruit is put into buffer address, now
3rd step：Carry out xor operation, by it is data cached take out and with B [i, j] carry out XOR computing obtain most
The result A [i, j] of the computing afterwards.
4, finally for IOTA computings, the computing is a constant xor operation, newly increases one here by input constant
XOR.
In summary, whole SHA3 algorithms are disassembled, it is final only to need 29 kinds of basic logic operations, can be with completion
The computing of all of above data, and the operational data in each step is all 64 bits, thus present invention design as shown in figure 1,
Using control module, a basic logic operations in SHA3 algorithms are completed in computing module, the once-through operation of memory module.
Fig. 1 is a kind of structural representation for the device for realizing Secure Hash Algorithm SHA3 of the present invention.
Specifically, this realizes that Secure Hash Algorithm SHA3 device includes：Control module, computing module, memory module, its
In, control module is used to receive peripheral operation instruction, often receives a peripheral operation instruction, is instructed according to peripheral operation and send phase
The control signal answered completes required movement to computing module and memory module, computing module and memory module according to control signal.
Computing module completes each basic logic operations according to the control signal received.Memory module is used to store each step computing
Intermediate result, the storage location of intermediate result are provided by control signal.
Preferably, the logical operation of basic logic operations is all handled according to 64 bits；Memory module is storage depth
For 256 and single port random access memory that data width is 64 bits.
Preferably, the device for realizing Secure Hash Algorithm SHA3 of the invention, basic logic operations include：Two input XORs
Operation, constant xor operation, two inputs and operation, not operation and 25 kinds of shifting functions；The shift count of 25 kinds of shifting functions
Respectively：0、36、3、41、18、1、44、10、45、2、62、6、43、15、61、28、55、25、21、56、27、20、39、8、14.
Fig. 2 is a kind of architecture principle schematic diagram for the device for realizing Secure Hash Algorithm SHA3 of the present invention.
Specifically, control module is controller, computing module is arithmetic unit, and memory module is memory.
First, controller and arithmetic unit can receive the operational order (opercode) of outside transmission, the instruction lattice of the instruction
Formula is as shown in table 1 below：
Table 1
| 8 | 8 | 8 | 8 |
| First operand address | Second operand address | Operation result address | The operational order of execution |
As shown in table 1, peripheral operation instruction is 32 bits, including：8 bit first operand addresses, 8 bits second operate
The operational order that number address, 8 bit arithmetic result addresses, 8 bits perform.Controller can according to the instruction format of operational order come
Corresponding control signal is sent, is performed by controller, with specific reference to Fig. 5.Herein, first operand is operand a, and second operates
Number is operand b, operation result r.
Fig. 5 is the flow signal of two input xor operations in a kind of device for realizing Secure Hash Algorithm SHA3 of the present invention
Figure.
For two input xor operations, controller performs following operate：
S1：Controller sends first operand address to memory, reads data corresponding to first operand address；
S2：Controller, which is sent, downloads the first data controlling signal to arithmetic unit, and the data of reading are sent to the first deposit
Device；
S3：Controller continues to send second operand address to memory, reads data corresponding to second operand address；
S4：Controller, which is sent, downloads the second data controlling signal to arithmetic unit, and the data of reading are sent to the second deposit
Device；
S5：So far, the data used required for XOR are already prepared to, and controller finally sends operation result control
Signal, operation result is sent to memory by notice arithmetic unit, and controller sends the ground of operation result to memory simultaneously
Location and write effective order.
Above is controller performs the flow of an XOR.
And arithmetic unit can parse the operational order representated by low eight of operational order to perform corresponding computing, here can
The order of xor operation is received, so arithmetic unit can perform xor operation, and is receiving operation result control signal (load_r)
Result is seen off afterwards.
Fig. 3 is a kind of state transfer schematic diagram of device for realizing Secure Hash Algorithm SHA3 of the present invention.
Here controller is realized by a finite state machine, is illustrated in figure 3 the state transfer of the finite state machine
Figure, is illustrated, the controller includes 7 states to the state transition diagram transfer process below：Idle condition (IDLE), operation
Command selection state (CHOOSE_OPERCODE_STATE), it is loaded into first operand address state (LOAD_A_ADDR_
STATE), it is loaded into first operand state (LOAD_A_STATE), is loaded into second operand address state (LOAD_B_ADDR_
STATE), it is loaded into second operand state (LOAD_B_STATE), is loaded into result phase (LOAD_R_STATE).Herein, first
Operand is operand a, and second operand is operand b, operation result r.
When enabling signal (start) is invalid, controller is in idle condition (IDLE)；When enabling signal is effective, control
Device jumps to operational order selection state, is selected according to the operational order representated by low eight of operational order (opercode)
Redirect state：Low eight when being 0 or 1, controller, which jumps to, is loaded into first operand address state (LOAD_A_ADDR_
STATE)；Low eight be 2 to 28 when, controller jump to be loaded into second operand address state (LOAD_B_ADDR_STATE).
Controller jumps to loading first operand address state (LOAD_A_ADDR_STATE) and unconditionally redirected automatically afterwards
To loading first operand state (LOAD_A_STATE), and then unconditional jump to automatically is loaded into second operand address state
(LOAD_B_ADDR_STATE), further unconditional jump to automatically is loaded into second operand state (LOAD_B_STATE), enters
One step unconditionally jumps to automatically is loaded into result phase (LOAD_R_STATE), finally returns to the free time from LOAD_R_STATE states
State (IDLE).
Fig. 4 is a kind of integral frame structure figure for the device for realizing Secure Hash Algorithm SHA3 of the present invention.It can be seen by figure
Go out core module to be made up of control module (SHA3_FSM) and computing module (SHA3_ALU) said before, below for
The two modules are described in further detail.
Control module (SHA3_FSM) includes：First input interface (clk), the second input interface (rst_n), the 3rd input
Interface (opercode [31:0]), the 4th input interface (start), the first output interface (load_a), the second output interface
(load_b), the 3rd output interface (load_r), the 4th output interface (done), the 5th output interface (addr_ram [7:0])、
6th output interface (write_ram).Specifically, as shown in table 2：
Table 2
| Signaling interface title | Direction | Illustrate |
| clk | Input | Clock signal |
| rst_n | Input | Reset signal, low level are effective |
| opercode[31:0] | Input | The bit of operational order code 32 |
| start | Input | Enabling signal |
| load_a | Output | Extract operation number a control signals |
| load_b | Output | Extract operation number b control signals |
| load_r | Output | Write-back result is to memory control signal |
| done | Output | Computing complement mark signal |
| addr_ram[7:0] | Output | Storage address control signal |
| write_ram | Output | Memory read/write control signal |
As known from Table 2, the first input interface input clock signal；Second input interface inputs reset signal, reset signal
Low level is effective；3rd input circuit inputs the operational order of 32 bits；4th input circuit inputs enabling signal；First output
Interface output takes first operand control signal；The output of second output interface takes second operand control signal；3rd output connects
Mouth exports write-back result to memory module control signal；4th output signal exports computing complement mark signal；5th output connects
Mouth output memory module address control signal；6th output interface exports memory module read-write control signal.Herein, the first operation
Number is operand a, and second operand is operand b.
Next interface specification is carried out to computing module (SHA3_ALU) module, it is as shown in table 3 below：
Table 3
As known from Table 3, computing module (SHA3_ALU) includes：First input interface (clk), the second input interface (rst_
N), the 3rd input interface (in [63:0]), the 4th input interface (opercode [31:0]), the 5th input interface (round [4:
0]), the 6th input interface (load_a), the 7th input interface (load_b), the 8th input interface (load_r) and first are defeated
Outgoing interface (out [63:0]).
First input interface input clock signal；Second input interface inputs reset signal, and reset signal low level is effective；
3rd input interface inputs 64 bit arithmetic module input datas；4th input interface inputs the instruction of 32 bit operatings；5th is defeated
Incoming interface wheel for inputting number；The input of 6th input interface takes first operand control signal；The operation of 7th input interface input second
Number control signal；8th input interface inputs write-back result to memory module control signal；First output interface exports 64 bits
Computing module output result.
Dotted line encloses the core logic (SHA3_Logic) that the part come is SHA3 in Fig. 4, is a depth outside red line
The random access memory (RAM) for 256 and single port that data width is 64 bits is spent, RAM interface is also carried out below
Illustrate, it is as shown in table 4 below.
Table 4
| Signaling interface title | Direction | Illustrate |
| clock | Input | Clock signal |
| wren | Input | For read-write 1 to write, 0 or 1 is all reading |
| data[63:0] | Input | The RAM bit of write-in data 64 |
| address[7:0] | Input | Address ram |
| q[63:0] | Output | The RAM bit of reading data 64 |
As known from Table 4, memory module includes：It is first input interface (clock), the second input interface (wren), the 3rd defeated
Incoming interface (data [63:0]), the 4th input interface (address [7:0]) and the first output interface (q [63:0]).
First input interface input clock signal；Second input interface inputs read-write, and read-write 1 is writes, and 0 or 1
All it is reading；3rd input interface inputs the random access memory write-in data of 64 bits；The input of 4th input interface is deposited at random
Access to memory address；First output interface exports 64 bit random access memories and reads data.
For RAM when control module is in idle condition outside can be to the random read-writes of RAM, at control module
In computing state, RAM is controlled by control module completely, and this is judged by done signals, and computing state done is 0, idle condition
Done is 1 so most of the time done is for 1, conveniently can carry out computing by the outside RAM that write message blocks at any time.
In addition, the present invention also constructs a kind of smart card, smart card includes the above-mentioned device for realizing Secure Hash Algorithm SHA3.
Above example only technical concepts and features to illustrate the invention, its object is to allow person skilled in the art
Scholar can understand present disclosure and implement accordingly, can not limit the scope of the invention.It is all to be wanted with right of the present invention
The equivalent changes and modifications that scope is done are sought, the covering scope of the claims in the present invention all should be belonged to.
Claims (10)
- A kind of 1. device for realizing Secure Hash Algorithm SHA3, it is characterised in that including：Control module, computing module, storage mould Block, wherein,The control module is used to receive peripheral operation instruction, a peripheral operation instruction is often received, according to the outside Operational order sends corresponding control signal to the computing module and memory module, the computing module and memory module according to The control signal completes required movement；The computing module completes each basic logic operations according to the control signal received；The memory module is used for the intermediate result for storing each step computing, and the storage location of the intermediate result is by the control Signal provides.
- 2. the device according to claim 1 for realizing Secure Hash Algorithm SHA3, it is characterised in that the basic logic fortune The logical operation of calculation is all handled according to 64 bits；The memory module is the single port random access memory that storage depth is 256 and data width is 64 bits.
- 3. the device according to claim 1 for realizing Secure Hash Algorithm SHA3, it is characterised in that the basic logic fortune Including：Two input xor operations, constant xor operation, two inputs and operation, not operation and 25 kinds of shifting functions；The shift count of 25 kinds of shifting functions is respectively：0、36、3、41、18、1、44、10、45、2、62、6、43、15、61、 28、55、25、21、56、27、20、39、8、14。
- 4. the device according to claim 3 for realizing Secure Hash Algorithm SHA3, it is characterised in that the two inputs XOR Operation, the control module perform following operate：S1：The control module sends first operand address to the memory module, reads the first operand address pair The data answered；S2：The control module, which is sent, downloads the first data controlling signal to the computing module, by the data of reading send to First register；S3：The control module continues to send second operand address to the memory module, with reading the second operand Data corresponding to location；S4：The control module, which is sent, downloads the second data controlling signal to the computing module, by the data of reading send to Second register；S5：The control module finally sends operation result control signal, notifies the computing module to be sent to operation result The memory module, and the control module sends the address of the operation result and with effect to the memory module simultaneously Order.
- 5. the device according to claim 4 for realizing Secure Hash Algorithm SHA3, it is characterised in that the peripheral operation refers to Make as 32 bits, including：8 bit first operand addresses, 8 bit second operand addresses, 8 bit arithmetic result addresses, 8 ratios The operational order that spy performs.
- 6. the device according to claim 4 for realizing Secure Hash Algorithm SHA3, it is characterised in that the control module bag Include：Idle condition, operational order selection state, first operand address state is loaded into, is loaded into first operand state, is loaded into the Two operand address states, it is loaded into second operand state, is loaded into result phase；When enabling signal is invalid, the control module is in the idle condition；When the enabling signal is effective, the control Module jumps to the operational order selection state, and state is redirected according to low eight selections of operational order：Described low eight are 0 Or when 1, the control module jumps to the loading first operand address state；Described low eight be 2 to 28 when, the control Molding block jumps to the loading second operand address state；The control module jumps to the operation of loading first automatically after jumping to the loading first operand address state Number state, and then the loading second operand address state is jumped to automatically, the loading second is further jumped to automatically Number state is operated, the loading result phase is further jumped to automatically, is eventually returned to the idle condition.
- 7. the device according to claim 1 for realizing Secure Hash Algorithm SHA3, it is characterised in that the control module bag Include：First input interface, the second input interface, the 3rd input interface, the 4th input interface, the first output interface, the second output Interface, the 3rd output interface, the 4th output interface, the 5th output interface, the 6th output interface；The first input interface input clock signal；Second input interface inputs reset signal, and the reset signal is low Level is effective；3rd input circuit inputs the operational order of 32 bits；4th input circuit inputs enabling signal；Institute State the output of the first output interface and take first operand control signal；The second output interface output takes second operand control letter Number；3rd output interface exports write-back result to memory module control signal；The 4th output signal output computing is complete Into marking signal；5th output interface exports memory module address control signal；The 6th output interface output storage Module read-write control signal.
- 8. the device according to claim 1 for realizing Secure Hash Algorithm SHA3, it is characterised in that the computing module bag Include：First input interface, the second input interface, the 3rd input interface, the 4th input interface, the 5th input interface, the 6th input Interface, the 7th input interface, the 8th input interface and the first output interface；The first input interface input clock signal；Second input interface inputs reset signal, and the reset signal is low Level is effective；3rd input interface inputs 64 bit arithmetic module input datas；The ratio of 4th input interface input 32 Special operational order；The 5th input interface wheel for inputting number；The 6th input interface input takes first operand control signal； 7th input interface inputs second operand control signal；8th input interface inputs write-back result to memory module Control signal；First output interface exports 64 bit arithmetic module output results.
- 9. the device according to claim 1 for realizing Secure Hash Algorithm SHA3, it is characterised in that the memory module bag Include：First input interface, the second input interface, the 3rd input interface, the 4th input interface and the first output interface；The first input interface input clock signal；Second input interface inputs read-write；3rd input connects The random access memory write-in data of mouth 64 bits of input；4th input interface inputs random access memory address； First output interface exports 64 bit random access memories and reads data.
- 10. a kind of smart card, it is characterised in that the realization that the smart card includes described in claim any one of 1-9 is breathed out safely Uncommon algorithm SHA3 device.
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