CN107833924B - Top gate type thin film transistor, preparation method thereof, array substrate and display panel - Google Patents
Top gate type thin film transistor, preparation method thereof, array substrate and display panel Download PDFInfo
- Publication number
- CN107833924B CN107833924B CN201711022384.7A CN201711022384A CN107833924B CN 107833924 B CN107833924 B CN 107833924B CN 201711022384 A CN201711022384 A CN 201711022384A CN 107833924 B CN107833924 B CN 107833924B
- Authority
- CN
- China
- Prior art keywords
- gate insulating
- insulating layer
- layer
- substrate
- hydrofluoric acid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 60
- 239000010409 thin film Substances 0.000 title claims abstract description 44
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 239000010410 layer Substances 0.000 claims abstract description 194
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 126
- 238000005530 etching Methods 0.000 claims abstract description 55
- 238000004140 cleaning Methods 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 40
- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 20
- 230000003647 oxidation Effects 0.000 claims abstract description 18
- 239000011241 protective layer Substances 0.000 claims abstract description 8
- 239000010408 film Substances 0.000 claims description 43
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 17
- 230000009194 climbing Effects 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 5
- 238000000427 thin-film deposition Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims 1
- 238000004458 analytical method Methods 0.000 description 5
- 229910052681 coesite Inorganic materials 0.000 description 5
- 229910052906 cristobalite Inorganic materials 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 5
- 229910052682 stishovite Inorganic materials 0.000 description 5
- 229910052905 tridymite Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 4
- 239000002131 composite material Substances 0.000 description 3
- 238000007715 excimer laser crystallization Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
Abstract
The disclosure provides a top gate type thin film transistor, a preparation method thereof, an array substrate and a display panel, and relates to the technical field of display. The preparation method of the top gate type thin film transistor comprises the following steps: preparing a second gate insulating layer on a substrate on which a semiconductor active layer, a source electrode, a drain electrode, a first gate insulating layer and a first gate electrode are formed, and forming an etching protective layer above the second gate insulating layer; placing the substrate with the second gate insulating layer and the etching protection layer in a hydrofluoric acid cleaning device for oxidation treatment and hydrofluoric acid cleaning so as to remove the etching protection layer in the hydrofluoric acid cleaning process; and preparing a second grid electrode on the substrate cleaned by the hydrofluoric acid. The method can improve the surface damage caused by cleaning the gate insulating layer by hydrofluoric acid, thereby ensuring the electrical property of the thin film transistor and the stability of the subsequent process.
Description
Technical Field
The disclosure relates to the technical field of display, and in particular relates to a top gate type thin film transistor, a preparation method thereof, an array substrate and a display panel.
Background
With the rapid development of semiconductor technology, the LTPS (Low Temperature polysilicon) backplane technology has advantages of high mobility, high aperture ratio, and capable of implementing GOA (Gate Driver on Array) so that the display panel based on the LTPS technology has better display effect than the display panel based on the a-Si (amorphous silicon) technology, and thus receives more and more attention.
Today, resolution requirements for displays are becoming higher and higher, and high PPI (Pixels Per inc) displays are a great challenge for existing LTPS processes. In the LTPS process, there is a process step of etching the gate insulating layer, which requires hydrofluoric acid (HF) cleaning of the gate insulating layer, but the cleaning process inevitably has certain influence on the gate insulating layer, such as thinning of the gate insulating layer, short circuit risk even at a climbing position, and the like, thereby affecting the stability of the subsequent process and the electrical characteristics of a Thin Film Transistor (TFT).
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
An object of the present disclosure is to provide a top gate type thin film transistor, a method of fabricating the same, an array substrate, and a display panel, which overcome one or more of the problems due to the limitations and disadvantages of the related art, at least to some extent.
Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosure.
According to an aspect of the present disclosure, there is provided a method of manufacturing a top gate type thin film transistor, including:
preparing a second gate insulating layer on a substrate on which a semiconductor active layer, a source electrode, a drain electrode, a first gate insulating layer and a first gate electrode are formed, and forming an etching protective layer above the second gate insulating layer;
placing the substrate with the second gate insulating layer and the etching protection layer in a hydrofluoric acid cleaning device for oxidation treatment and hydrofluoric acid cleaning so as to remove the etching protection layer in the hydrofluoric acid cleaning process;
and preparing a second grid electrode on the substrate cleaned by the hydrofluoric acid.
In an exemplary embodiment of the present disclosure, forming an etching protection layer over the second gate insulating layer includes:
and forming an amorphous silicon film above the second gate insulating layer.
In an exemplary embodiment of the present disclosure, the performing an oxidation process on the substrate on which the second gate insulating layer and the etching protection layer are formed in a hydrofluoric acid cleaning apparatus includes:
and placing the substrate on which the second gate insulating layer and the amorphous silicon film are formed in a hydrofluoric acid cleaning device for ozone oxidation treatment so as to convert the amorphous silicon film into a silicon oxide film.
In an exemplary embodiment of the present disclosure, forming an etching protection layer over the second gate insulating layer includes:
and forming a layer of silicon oxide film above the second gate insulating layer.
In an exemplary embodiment of the present disclosure, the thickness of the etching protection layer is
In an exemplary embodiment of the present disclosure, the second gate insulating layer and the etching protection layer are prepared in the same thin film deposition apparatus.
In one exemplary embodiment of the present disclosure, preparing a second gate insulating layer on a substrate on which a semiconductor active layer, source and drain electrodes, a first gate insulating layer, and a first gate electrode are formed includes:
one or more of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film are formed on a substrate on which a semiconductor active layer, source and drain electrodes, a first gate insulating layer, and a first gate electrode are formed.
In one exemplary embodiment of the present disclosure, the substrate on which the semiconductor active layer, the source and drain electrodes, the first gate insulating layer, and the first gate electrode are formed includes:
a substrate base plate;
a source and a drain formed over the substrate base;
a semiconductor active layer formed over the source and drain electrodes;
a first gate insulating layer formed over the semiconductor active layer; and the number of the first and second groups,
a first gate electrode formed over the first gate insulating layer.
In one exemplary embodiment of the present disclosure, the substrate on which the semiconductor active layer, the source and drain electrodes, the first gate insulating layer, and the first gate electrode are formed further includes:
and the buffer layer is formed on one side of the substrate base plate facing the semiconductor active layer.
According to one aspect of the disclosure, a top gate thin film transistor is provided, which is prepared by the preparation method.
According to an aspect of the present disclosure, an array substrate is provided, which includes the above-mentioned top gate thin film transistor.
According to an aspect of the present disclosure, a display panel is provided, which includes the above-mentioned top gate type thin film transistor.
In the top gate thin film transistor and the method for manufacturing the same according to the exemplary embodiment of the present disclosure, before the second gate insulating layer is cleaned by hydrofluoric acid, an etching protection layer is formed on the surface of the second gate insulating layer, and the substrate on which the etching protection layer is formed is placed in a hydrofluoric acid cleaning apparatus for cleaning. Therefore, in the hydrofluoric acid cleaning device, the etching protection layer is subjected to oxidation treatment to form an oxide film, and the oxide film can protect the second gate insulating layer below the oxide film when being cleaned by hydrofluoric acid, so that the second gate insulating layer is prevented from being excessively thinned due to etching of hydrofluoric acid, the surface damage condition of the second gate insulating layer is improved, the electrical performance of the thin film transistor can be ensured, and the stability of a subsequent process is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1 schematically illustrates a structural diagram of a thin film transistor in an exemplary embodiment of the present disclosure;
fig. 2 schematically shows surface damage data caused by cleaning the gate insulating layer with hydrofluoric acid under different conditions in the prior art;
FIG. 3 schematically shows a prior art scan analysis test pattern of the top of the gate insulating layer before hydrofluoric acid cleaning;
FIG. 4 is a schematic view showing a scan analysis test chart at a gate insulating layer ramp before hydrofluoric acid cleaning in the prior art;
fig. 5 schematically shows a scan analysis test chart of a gate insulating layer after hydrofluoric acid cleaning in the related art;
fig. 6 schematically illustrates a flow chart of a method of fabricating a thin film transistor in an exemplary embodiment of the present disclosure;
fig. 7 to 9 schematically illustrate a manufacturing process of a thin film transistor in an exemplary embodiment of the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The thicknesses and shapes of the layers in the drawings are not to be construed as true scale, but merely as a matter of convenience for illustrating the disclosure. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted.
The present example embodiment provides a thin film transistor that is a double top gate type transistor. Fig. 1 is a schematic structural diagram of the double top gate thin film transistor. The structure of the thin film transistor 10 may mainly include:
a substrate 101, wherein the substrate 101 can be a glass substrate or a flexible substrate;
a buffer layer 102 over the substrate base plate 101, the buffer layer 102 may be a single-layer structure or a multi-layer structure;
a source electrode 103 and a drain electrode 104 positioned above the buffer layer 102, and a semiconductor active layer 105, wherein the semiconductor active layer 105 may be positioned above the source electrode 103 and the drain electrode 104, or below the source electrode 103 and the drain electrode 104;
a first gate insulating layer 106 and a first gate electrode 107 over the source electrode 103, the drain electrode 104, and the semiconductor active layer 105, wherein the first gate insulating layer 106 may include one or more of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, and a hafnium oxide film, and may have a single-layer structure or a multi-layer composite structure;
a second gate insulating layer 108 and a second gate electrode 109 over the first gate insulating layer 106 and the first gate electrode 107, wherein the second gate insulating layer 108 may include one or more of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film, and may have a single-layer structure or a multi-layer composite structure;
and a protective layer 110 over the second gate insulating layer 108 and the second gate electrode 109.
It should be noted that: in the above process of manufacturing the thin film transistor, particularly after the second gate insulating layer 108 is formed and before the second gate electrode 109 is formed, a hydrofluoric acid HF cleaning process is required. That is, the substrate is placed in a hydrofluoric acid cleaning apparatus and sequentially passed through ozone O3Oxidation treatment-hydrofluoric acid HF cleaning-ozone O3A process of oxidation treatment for subjecting the semiconductor active layer 105 to uniform oxygenSo as to make the crystallization more uniform in the subsequent ELA (Excimer Laser crystallization).
However, the hydrofluoric acid cleaning inevitably causes some damage to the surface of the second gate insulating layer 108. Fig. 2 shows experimentally determined data of surface damage caused by cleaning the second gate insulating layer 108 with hydrofluoric acid under different conditions. The different conditions described herein may be, for example, different gate insulating layer thicknesses, different gate etching modes (WET etching and inductively coupled plasma ICP etching), and the like. From this fact, the film thickness of the second gate insulating layer 108 was set to
And
in the case of (1), the film layer on the top and on the climbing slope has no matter what etching method is adopted
And thinning left and right.
The following is a description of a specific example. Before the hydrofluoric acid cleaning, as shown in fig. 3 and 4, the scan analysis test result of the second gate insulating layer 108 shows that the thickness of the second gate insulating layer 108 at the climbing position is smaller than that at the top portion
Left and right. After the hydrofluoric acid cleaning, as shown in fig. 5, the scanning analysis and test result of the second gate insulating layer 108 shows that the thickness of the second gate insulating layer 108 at the climbing position and the top portion is reduced
Left and right.
Thus, for the top position of the second gate insulating layer 108, the thinned film layer may have a certain influence on the electrical characteristics of the TFT device during operation; for an originally thin climbing position, the thinning amount brings the risk of short circuit, thereby affecting the effectStability of the subsequent process. Specifically, the thickness of the second gate insulating layer 108 deposited on the climbing slope is reduced to some extent, and is further reduced after the hydrofluoric acid cleaning, and the two reductions act together to reduce the thickness of the climbing slope
On the basis, p-Si obtained after the crystallization of the a-Si has certain bulges at the grain boundary, so that the risk of short circuit exists at the climbing position.
In view of this, the present exemplary embodiment provides a method of manufacturing a thin film transistor for manufacturing the double top gate type thin film transistor of the above-described structure. As shown in fig. 6, the method for manufacturing the thin film transistor 10 may include:
s1, referring to fig. 7, preparing a second gate insulating layer 108 on the substrate on which the source and drain electrodes 103 and 104, the semiconductor active layer 105, the first gate insulating layer 106, and the first gate electrode 107 are formed, and forming an etching protection layer 200 over the second gate insulating layer 108;
s2, referring to fig. 8, placing the substrate on which the second gate insulating layer 108 and the etching protection layer 200 are formed in a hydrofluoric acid cleaning apparatus for oxidation treatment and hydrofluoric acid cleaning, so as to remove the etching protection layer 200 during the hydrofluoric acid cleaning process;
s3, referring to fig. 9, the second gate electrode 109 is formed on the substrate after being cleaned with hydrofluoric acid.
The hydrofluoric acid cleaning device can comprise an oxidation treatment unit, a hydrofluoric acid cleaning unit and an oxidation treatment unit which are connected in sequence.
In the method for manufacturing a thin film transistor according to the exemplary embodiment of the present disclosure, before the second gate insulating layer 108 is cleaned by hydrofluoric acid, the etching protection layer 200 is formed on the surface of the second gate insulating layer, and the substrate on which the etching protection layer 200 is formed is placed in a hydrofluoric acid cleaning apparatus for cleaning. Thus, in the hydrofluoric acid cleaning apparatus, the etching protection layer 200 is oxidized to form an oxide film, and the oxide film protects the second gate insulating layer 108 thereunder when being cleaned by the hydrofluoric acid, so as to prevent the second gate insulating layer 108 from being excessively thinned due to etching by the hydrofluoric acid, thereby improving the surface damage of the second gate insulating layer 108, further ensuring the electrical performance of the thin film transistor 10, and improving the stability of the subsequent process.
A method for manufacturing a thin film transistor in this exemplary embodiment will be described in detail below with reference to the drawings.
In step S1, referring to fig. 7, a second gate insulating layer 108 is prepared on the substrate on which the source and drain electrodes 103 and 104, the semiconductor active layer 105, the first gate insulating layer 106, and the first gate electrode 107 are formed, and an etching protection layer 200 is formed over the second gate insulating layer 108.
In this example embodiment, the substrate on which the source and drain electrodes 103 and 104, the semiconductor active layer 105, the first gate insulating layer 106, and the first gate electrode 107 are formed may include: the semiconductor device includes a substrate 101, a buffer layer 102 formed on the substrate 101, a source electrode 103, a drain electrode 104, and a semiconductor active layer 105 formed on the buffer layer 102, a first gate insulating layer 106 formed on the source electrode 103, the drain electrode 104, and the semiconductor active layer 105, and a first gate electrode 107 formed on the first gate insulating layer 106.
The semiconductor active layer 105 may be formed above the source electrode 103 and the drain electrode 104, or below the source electrode 103 and the drain electrode 104, which is not limited herein.
It should be noted that: the "upper" and "lower" in this embodiment are described based on the sequence of the manufacturing process, that is, the structure formed first is on the lower side and the structure formed later is on the upper side, and the relative positions of the upper side and the lower side in the drawings are not absolute.
Based on this, the preparing the second gate insulating layer 108 may include: forming a silicon nitride SiN thin film, a silicon oxide SiO thin film on the substrate by a CVD (Chemical vapor deposition) method2One or more of a thin film and a silicon oxynitride SiNO thin film. The second gate insulating layer 108 may have a single-layer structure or a multi-layer composite structure.
Of course, the present embodiment is not limited thereto, and the second gate insulating layer 108 may also be made of other insulating materials.
On this basis, the forming of the etching protection layer 200 above the second gate insulating layer 108 may include: the etching protection layer 200 is formed over the second gate insulating layer 108 by a CVD method.
The etching protection layer 200 and the second gate insulating layer 108 may be prepared in the same CVD apparatus, such as a same PECVD (Plasma Enhanced Chemical Vapor Deposition) apparatus. Thus, the etching protection layer 200 is directly deposited after the second gate insulating layer 108 is deposited in the same equipment, so that other impurities can be prevented from being introduced, and a high-quality film layer can be obtained.
Preferably, the thickness of the etching protection layer 200 may be
Within the thickness range, the second gate insulating layer 108 can be effectively prevented from being excessively thinned due to etching of hydrofluoric acid in the hydrofluoric acid cleaning process, and the thickness of the second gate insulating layer 108 is not increased, so that the thin film transistor can be ensured to have good electrical performance.
In one embodiment of the present example, the etching protection layer 200 may be an amorphous silicon a-Si thin film. In this case, the forming of the etching protection layer 200 above the second gate insulating layer 108 may be: an amorphous silicon a-Si thin film is formed over the second gate insulating layer 108.
In another embodiment of this example, the etching protection layer 200 may also be silicon oxide SiO2A film. In this case, the forming of the etching protection layer 200 above the second gate insulating layer 108 may be: a layer of silicon oxide SiO is formed over the second gate insulating layer 1082A film.
In step S2, referring to fig. 8, the substrate on which the second gate insulating layer 108 and the etching protection layer 200 are formed is placed in a hydrofluoric acid cleaning apparatus to be subjected to oxidation treatment and hydrofluoric acid cleaning, so that the etching protection layer 200 is removed in the hydrofluoric acid cleaning process.
The present exemplary embodimentWherein the substrate is required to pass through ozone O in sequence in a hydrofluoric acid cleaning device3Oxidation treatment, hydrofluoric acid cleaning, ozone O3And (5) oxidation treatment. At O3During the oxidation process, the film formed on the substrate, especially the etching protection layer 200 on the substrate surface, is oxidized to generate a corresponding oxide, which is etched away during the hydrofluoric acid cleaning.
When the etching protection layer 200 is an amorphous silicon a-Si film, the amorphous silicon a-Si film passes through O in a hydrofluoric acid cleaning device3After oxidation treatment, the silicon oxide is converted into silicon oxide SiO2A film. In this case, the silicon oxide SiO is first cleaned in the hydrofluoric acid cleaning process2The thin film is etched, and then a small amount of etching may be performed on the second gate insulating layer 108, such as a silicon nitride SiN thin film, so that the surface damage to the second gate insulating layer 108 can be effectively reduced.
It should be noted that: in the oxidation process of the amorphous silicon a-Si film, the situation that most of amorphous silicon a-Si is oxidized and a small amount of amorphous silicon a-Si is not oxidized may exist according to the difference of the thickness of the amorphous silicon a-Si film, and at the moment, the residual amorphous silicon a-Si is also etched in the hydrofluoric acid cleaning process.
When the etching protection layer 200 is silicon oxide SiO2When thin film, the silicon oxide SiO2The film passes through O in a hydrofluoric acid cleaning device3Remains as silicon oxide SiO after oxidation treatment2A film. In this case, the silicon oxide SiO is first cleaned in the hydrofluoric acid cleaning process2The thin film is etched, and then a small amount of etching may be performed on the second gate insulating layer 108, such as a silicon nitride SiN thin film, so that the surface damage to the second gate insulating layer 108 can be effectively reduced.
Considering that the thickness of the etching protection layer 200 is relatively small, for example, in
And silicon oxide SiO2The uniformity is poor when the deposition thickness of the thin film is small, so the embodiment preferably adopts an amorphous silicon a-Si thin film as the etching protection layer 200.
In step S3, as shown in fig. 9, the second gate electrode 109 is prepared on the substrate after being cleaned with hydrofluoric acid.
In this example embodiment, the second gate electrode 109 is formed on the second gate insulating layer 108 cleaned by the hydrofluoric acid, and thereafter, a protective layer 110 may be further formed over the second gate electrode 109.
The material of the first gate 107 and the second gate 109 may be any one of metals or alloys such as molybdenum, tungsten, tantalum, molybdenum and tungsten; the materials of the first gate insulating layer 106, the second gate insulating layer 108, and the protective layer 110 may be any of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, and aluminum oxide; the material of the semiconductor active layer 105 may be any one of single crystal silicon, amorphous silicon, polycrystalline silicon, and metal oxide semiconductor, and the present embodiment preferably converts the amorphous silicon into polycrystalline silicon through a subsequent ELA process.
Based on the above description, the thin film transistor 10 provided in this exemplary embodiment may be manufactured by the above manufacturing method, so as to prevent the second gate insulating layer 108 from being excessively thinned due to etching by the hydrofluoric acid, thereby improving the surface damage condition of the second gate insulating layer 108, further ensuring the electrical performance of the thin film transistor 10, and improving the stability of the subsequent process.
The present exemplary embodiment also provides an array substrate including the thin film transistor 10 described above.
The array substrate can be applied to an LCD (Liquid Crystal Display), and forms an LCD panel in a box-to-box manner with a color film substrate.
Alternatively, the array substrate may also be applied to an OLED (Organic Light Emitting Diode) display, and forms an OLED panel with a package substrate facing the case.
Accordingly, the present exemplary embodiment also provides a display panel including the thin film transistor 10 or the array substrate.
Since the thin film transistor 10 provided in this embodiment has stable electrical properties, a display panel using the thin film transistor 10 can also obtain good display effects.
The present exemplary embodiment also provides a display device including the display panel described above.
The display device may include any product or component having a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, and a navigator, and the disclosure does not particularly limit this.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (7)
1. A method for manufacturing a top gate type thin film transistor includes:
preparing a second gate insulating layer on a substrate on which a semiconductor active layer, a source electrode, a drain electrode, a first gate insulating layer and a first gate electrode are formed, and forming an etching protective layer above the second gate insulating layer, wherein the etching protective layer is directly contacted with the second gate insulating layer and at least covers the whole top surface and the whole climbing position of the second gate insulating layer;
placing the substrate with the second gate insulating layer and the etching protection layer in a hydrofluoric acid cleaning device for oxidation treatment and hydrofluoric acid cleaning so as to remove the etching protection layer in the hydrofluoric acid cleaning process;
preparing a second grid electrode on the substrate cleaned by the hydrofluoric acid; wherein the content of the first and second substances,
forming an etching protection layer over the second gate insulating layer includes:
and forming an amorphous silicon film above the second gate insulating layer.
2. The method according to claim 1, wherein performing an oxidation process on the substrate on which the second gate insulating layer and the etching protection layer are formed in a hydrofluoric acid cleaning apparatus comprises:
and placing the substrate on which the second gate insulating layer and the amorphous silicon film are formed in a hydrofluoric acid cleaning device for ozone oxidation treatment so as to convert the amorphous silicon film into a silicon oxide film.
3. The production method according to any one of claims 1 to 2, wherein the etching protective layer has a thickness of
4. The method according to claim 1, wherein the second gate insulating layer and the etching protection layer are formed in the same thin film deposition apparatus.
5. The manufacturing method of claim 4, wherein the manufacturing of the second gate insulating layer on the substrate on which the semiconductor active layer, the source and drain electrodes, the first gate insulating layer, and the first gate electrode are formed comprises:
one or more of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film are formed on a substrate on which a semiconductor active layer, source and drain electrodes, a first gate insulating layer, and a first gate electrode are formed.
6. The method of claim 1, wherein the substrate on which the semiconductor active layer, the source and drain electrodes, the first gate insulating layer, and the first gate electrode are formed comprises:
a substrate base plate;
a source and a drain formed over the substrate base;
a semiconductor active layer formed over the source and drain electrodes;
a first gate insulating layer formed over the semiconductor active layer; and the number of the first and second groups,
a first gate electrode formed over the first gate insulating layer.
7. The method of claim 6, wherein the substrate on which the semiconductor active layer, the source and drain electrodes, the first gate insulating layer, and the first gate electrode are formed further comprises:
and the buffer layer is formed on one side of the substrate base plate facing the semiconductor active layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711022384.7A CN107833924B (en) | 2017-10-26 | 2017-10-26 | Top gate type thin film transistor, preparation method thereof, array substrate and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711022384.7A CN107833924B (en) | 2017-10-26 | 2017-10-26 | Top gate type thin film transistor, preparation method thereof, array substrate and display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107833924A CN107833924A (en) | 2018-03-23 |
| CN107833924B true CN107833924B (en) | 2020-06-19 |
Family
ID=61650784
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711022384.7A Expired - Fee Related CN107833924B (en) | 2017-10-26 | 2017-10-26 | Top gate type thin film transistor, preparation method thereof, array substrate and display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107833924B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110224031A (en) * | 2019-05-22 | 2019-09-10 | 深圳市华星光电半导体显示技术有限公司 | Improve the structure and its production method of metal oxide TFT characteristic |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4960719A (en) * | 1988-02-04 | 1990-10-02 | Seikosha Co., Ltd. | Method for producing amorphous silicon thin film transistor array substrate |
| CN101064323A (en) * | 2006-04-26 | 2007-10-31 | 爱普生映像元器件有限公司 | Electro-optical device, electronic apparatus, and method of manufacturing electro-optical device |
| CN102487041A (en) * | 2010-12-02 | 2012-06-06 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and electronic paper display device |
| CN105789052A (en) * | 2015-12-28 | 2016-07-20 | 昆山国显光电有限公司 | Fabrication method of low-temperature poly-silicon thin film transistor and product |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI476927B (en) * | 2007-05-18 | 2015-03-11 | Semiconductor Energy Lab | Methdo for manufacturing semiconductor device |
| JP6737620B2 (en) * | 2016-04-04 | 2020-08-12 | 株式会社ジャパンディスプレイ | Organic EL display device and method for manufacturing organic EL display device |
-
2017
- 2017-10-26 CN CN201711022384.7A patent/CN107833924B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4960719A (en) * | 1988-02-04 | 1990-10-02 | Seikosha Co., Ltd. | Method for producing amorphous silicon thin film transistor array substrate |
| CN101064323A (en) * | 2006-04-26 | 2007-10-31 | 爱普生映像元器件有限公司 | Electro-optical device, electronic apparatus, and method of manufacturing electro-optical device |
| CN102487041A (en) * | 2010-12-02 | 2012-06-06 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and electronic paper display device |
| CN105789052A (en) * | 2015-12-28 | 2016-07-20 | 昆山国显光电有限公司 | Fabrication method of low-temperature poly-silicon thin film transistor and product |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107833924A (en) | 2018-03-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108022935B (en) | Display device | |
| US12002819B2 (en) | Display device | |
| US20070161165A1 (en) | Systems and methods involving thin film transistors | |
| US20160276376A1 (en) | Array substrate, method for fabricating the same, and display device | |
| US20160133755A1 (en) | Low temperature poly-silicon thin film transistor and manufacturing method thereof, array substrate and display device | |
| US11443658B2 (en) | Flexible display panels, manufacturing methods thereof and flexible display apparatuses | |
| CN106098699B (en) | A kind of array substrate, its production method, display panel and preparation method thereof | |
| US9911618B2 (en) | Low temperature poly-silicon thin film transistor, fabricating method thereof, array substrate and display device | |
| US20080087889A1 (en) | Method of fabricating an organic electroluminescent device and system of displaying images | |
| US11121226B2 (en) | Thin film transistor and method for manufacturing the same, array substrate and display device | |
| US20180292696A1 (en) | Array substrate, manufacturing method thereof, display panel and display device | |
| US11101368B2 (en) | Method of forming crystallized semiconductor layer, method of fabricating thin film transistor, thin film transistor, and display apparatus | |
| TWI388014B (en) | Method of manufacturing thin film transistor | |
| WO2015000255A1 (en) | Array substrate, display device, and method for manufacturing array substrate | |
| KR20110073278A (en) | Thin film transistor and manufacturing method thereof | |
| US20180175073A1 (en) | Array substrate, manufacturing method thereof and display device | |
| US20180182897A1 (en) | Thin film transistor, method for fabricating the same, display substrate and display device | |
| US20080108226A1 (en) | Method of fabricating thin film transistor substrate and thin film transistor substrate produced using the same | |
| US10326024B2 (en) | Thin film transistor, array substrate, manufacturing method and display device | |
| US10693011B2 (en) | Thin film transistor array substrate, method of manufacturing the same, and display device including thin film transistor substrate | |
| US20150380565A1 (en) | Thin film transistor and method for manufacturing the same, array substrate and display device | |
| US20120292628A1 (en) | Thin film transistor, array substrate and preparation method thereof | |
| US20160329352A1 (en) | Array substrate and fabrication method thereof, and display device | |
| US20170278873A1 (en) | Thin film transistor, thin film transistor panel, and method for manufacturing the same | |
| CN107833924B (en) | Top gate type thin film transistor, preparation method thereof, array substrate and display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20200619 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |