CN107833924A - Top gate type thin film transistor and preparation method thereof, array base palte, display panel - Google Patents
Top gate type thin film transistor and preparation method thereof, array base palte, display panel Download PDFInfo
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- CN107833924A CN107833924A CN201711022384.7A CN201711022384A CN107833924A CN 107833924 A CN107833924 A CN 107833924A CN 201711022384 A CN201711022384 A CN 201711022384A CN 107833924 A CN107833924 A CN 107833924A
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- 239000010409 thin film Substances 0.000 title claims abstract description 42
- 238000002360 preparation method Methods 0.000 title claims abstract description 29
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- 238000009413 insulation Methods 0.000 claims abstract description 100
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 19
- 230000003647 oxidation Effects 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims description 180
- 239000010408 film Substances 0.000 claims description 48
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 21
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 18
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 239000012528 membrane Substances 0.000 claims description 7
- 239000011241 protective layer Substances 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 230000003628 erosive effect Effects 0.000 claims description 3
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- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 8
- 229910021419 crystalline silicon Inorganic materials 0.000 description 11
- 230000009194 climbing Effects 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 238000004140 cleaning Methods 0.000 description 6
- 238000004458 analytical method Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
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- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
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- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 241000588731 Hafnia Species 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
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- 239000011521 glass Substances 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- MGRWKWACZDFZJT-UHFFFAOYSA-N molybdenum tungsten Chemical compound [Mo].[W] MGRWKWACZDFZJT-UHFFFAOYSA-N 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
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- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
Abstract
The disclosure provides a kind of top gate type thin film transistor and preparation method thereof, array base palte, display panel, is related to display technology field.The preparation method of the top gate type thin film transistor includes：The second gate insulation layer is prepared on the substrate formed with semiconductor active layer, source electrode and drain electrode, the first gate insulation layer and first grid, and an etch-protecting layer is formed above second gate insulation layer；Substrate formed with second gate insulation layer and the etch-protecting layer is placed in hydrofluoric acid clean device and carries out oxidation processes and hydrofluoric acid clean, to remove the etch-protecting layer during the hydrofluoric acid clean；Second grid is prepared on the substrate after by the hydrofluoric acid clean.The disclosure can improve hydrofluoric acid clean gate insulation layer and caused by surface damage, so as to ensure the stability of the electric property of thin film transistor (TFT) and subsequent technique.
Description
Technical field
This disclosure relates to display technology field, more particularly to a kind of top gate type thin film transistor and preparation method thereof, array
Substrate, display panel.
Background technology
With the high speed development of semiconductor technology, LTPS (Low Temperature Poly-silicon, low-temperature polysilicon
Silicon) with its high mobility, high aperture, achievable GOA, (Gate Driver on Array, array base palte row drive backplane technology
It is dynamic) etc. advantage so that had based on the display panel of LTPS technology compared to the display panel based on a-Si (non-crystalline silicon) technology
More preferably display effect, therefore receive and increasingly pay attention to be extensive.
Nowadays people are for the resolution requirement more and more higher of display, high PPI (Pixels Per Inch, per inch picture
Prime number amount) display is very big challenge for existing LTPS techniques.The work of gate insulation layer etching is had in LTPS techniques
Skill step, the step need to carry out gate insulation layer hydrofluoric acid (HF) cleaning, but inevitably exhausted to grid in cleaning process
Edge layer produces certain influence, such as can cause being thinned, short-circuit risks etc. even being caused at climbing for gate insulation layer, so as to shadow
Ring the stability of subsequent technique and TFT (Thin Film Transistor, thin film transistor (TFT)) electrology characteristic.
It should be noted that information is only used for strengthening the reason to the background of the disclosure disclosed in above-mentioned background section
Solution, therefore can include not forming the information to prior art known to persons of ordinary skill in the art.
The content of the invention
The purpose of the disclosure is to provide a kind of top gate type thin film transistor and preparation method thereof, array base palte, display surface
Plate, and then one or more problem caused by the limitation of correlation technique and defect is at least overcome to a certain extent.
Other characteristics and advantage of the disclosure will be apparent from by following detailed description, or partially by the disclosure
Practice and acquistion.
According to an aspect of this disclosure, there is provided a kind of preparation method of top gate type thin film transistor, including：
Prepared on the substrate formed with semiconductor active layer, source electrode and drain electrode, the first gate insulation layer and first grid
Second gate insulation layer, and form an etch-protecting layer above second gate insulation layer；
Substrate formed with second gate insulation layer and the etch-protecting layer is placed in hydrofluoric acid clean device
Row oxidation processes and hydrofluoric acid clean, to remove the etch-protecting layer during the hydrofluoric acid clean；
Second grid is prepared on the substrate after by the hydrofluoric acid clean.
In a kind of exemplary embodiment of the disclosure, an etch-protecting layer bag is formed above second gate insulation layer
Include：
One layer of amorphous silicon membrane is formed above second gate insulation layer.
In a kind of exemplary embodiment of the disclosure, by formed with second gate insulation layer and the etch-protecting layer
Substrate, which is placed in progress oxidation processes in hydrofluoric acid clean device, to be included：
Substrate formed with second gate insulation layer and the amorphous silicon membrane is placed in hydrofluoric acid clean device
Row ozone Oxidation Treatment, so that the amorphous silicon membrane is converted to silicon oxide film.
In a kind of exemplary embodiment of the disclosure, an etch-protecting layer bag is formed above second gate insulation layer
Include：
One layer of silicon oxide film is formed above second gate insulation layer.
In a kind of exemplary embodiment of the disclosure, the thickness of the etch-protecting layer is
In a kind of exemplary embodiment of the disclosure, second gate insulation layer and the etch-protecting layer are in same film
Prepared in depositing device.
In a kind of exemplary embodiment of the disclosure, formed with semiconductor active layer, source electrode and drain electrode, the first gate insulation
Preparing the second gate insulation layer on the substrate of layer and first grid includes：
Formed on the substrate formed with semiconductor active layer, source electrode and drain electrode, the first gate insulation layer and first grid
One or more in silicon nitride film, silicon oxide film and silicon oxynitride film.
It is described exhausted formed with semiconductor active layer, source electrode and drain electrode, the first grid in a kind of exemplary embodiment of the disclosure
The substrate of edge layer and first grid includes：
Underlay substrate；
The source electrode being formed above the underlay substrate and drain electrode；
The semiconductor active layer being formed above the source electrode and the drain electrode；
The first gate insulation layer being formed above the semiconductor active layer；And
The first grid being formed above first gate insulation layer.
It is described exhausted formed with semiconductor active layer, source electrode and drain electrode, the first grid in a kind of exemplary embodiment of the disclosure
The substrate of edge layer and first grid also includes：
The underlay substrate is formed at towards the cushion of the semiconductor active layer side.
According to an aspect of this disclosure, there is provided a kind of top gate type thin film transistor, the top gate type thin film transistor are adopted
It is prepared with above-mentioned preparation method.
According to an aspect of this disclosure, there is provided a kind of array base palte, including above-mentioned top gate type thin film transistor.
According to an aspect of this disclosure, there is provided a kind of display panel, including above-mentioned top gate type thin film transistor.
Top gate type thin film transistor that disclosure illustrative embodiments are provided and preparation method thereof, exhausted to second gate
Edge layer is carried out first forming an etch-protecting layer on its surface before hydrofluoric acid clean, and the substrate formed with etch-protecting layer is put
In case cleaning in hydrofluoric acid clean device.So, in hydrofluoric acid clean device, the etch-protecting layer can be through peroxidating
Handle and form an oxide-film, the oxide-film can play protection when carrying out hydrofluoric acid clean to the second gate insulation layer below
Effect, so as to prevent the second gate insulation layer by hf etching by excessive thinning, improve the table of the second gate insulation layer with this
Surface damage situation, and then the electric property of thin film transistor (TFT) can be ensured, and improve the stability of subsequent technique.
It should be appreciated that the general description and following detailed description of the above are only exemplary and explanatory, not
The disclosure can be limited.
Brief description of the drawings
Accompanying drawing herein is merged in specification and forms the part of this specification, shows the implementation for meeting the disclosure
Example, and be used to together with specification to explain the principle of the disclosure.It should be evident that drawings in the following description are only the disclosure
Some embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
These accompanying drawings obtain other accompanying drawings.
Fig. 1 schematically shows the structural representation of thin film transistor (TFT) in disclosure exemplary embodiment；
Fig. 2 schematically shows the surface damage number caused by the gate insulation layer of hydrofluoric acid clean different condition in the prior art
According to；
Fig. 3 schematically shows the scanning analysis test chart at the top of gate insulation layer before hydrofluoric acid clean in the prior art；
Fig. 4 schematically shows the scanning analysis test chart at gate insulation layer climbing before hydrofluoric acid clean in the prior art；
Fig. 5 schematically shows the scanning analysis test chart of gate insulation layer after hydrofluoric acid clean in the prior art；
Fig. 6 schematically shows the preparation method flow chart of thin film transistor (TFT) in disclosure exemplary embodiment；
Fig. 7 to Fig. 9 schematically shows the preparation process schematic diagram of thin film transistor (TFT) in disclosure exemplary embodiment.
Embodiment
Example embodiment is described more fully with referring now to accompanying drawing.However, example embodiment can be real in a variety of forms
Apply, and be not understood as limited to example set forth herein；On the contrary, these embodiments are provided so that the disclosure will more comprehensively and
Completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.Described feature, structure or characteristic
It can be incorporated in any suitable manner in one or more embodiments.In the following description, there is provided many details
Embodiment of the disclosure is fully understood so as to provide.It will be appreciated, however, by one skilled in the art that the disclosure can be put into practice
Technical scheme and omit it is one or more in the specific detail, or can use other methods, constituent element, device,
Step etc..In other cases, known solution is not shown in detail or describes to avoid making each side of the disclosure from becoming mould
Paste.
In addition, accompanying drawing is only the schematic illustrations of the disclosure, it is not necessarily drawn to scale.The thickness of each layer in accompanying drawing
Do not reflect actual proportions with shape, be merely for convenience and purposes of illustration content of this disclosure.Identical reference represents identical in figure
Or similar part, thus repetition thereof will be omitted.
This example embodiment provides a kind of thin film transistor (TFT), and the thin film transistor (TFT) is Double Tops gate type transistor.Fig. 1 institutes
It is shown as the structural representation of the Double Tops gate type thin film transistor.The structure of the thin film transistor (TFT) 10 can mainly include：
Underlay substrate 101, the underlay substrate 101 can be glass substrate or flexible base board；
Cushion 102 above underlay substrate 101, the cushion 102 can be single layer structure or sandwich construction；
Source electrode 103 and drain electrode 104 and semiconductor active layer 105 above cushion 102, the semiconductor active
Layer 105 can be located at the top of source electrode 103 and drain electrode 104, can also be located at the lower section of source electrode 103 and drain electrode 104；
The first gate insulation layer 106 and the first grid above source electrode 103 and drain electrode 104 and semiconductor active layer 105
Pole 107, first gate insulation layer 106 can include silicon nitride film, silicon oxide film, silicon oxynitride film, aluminum oxide film,
And the one or more in hafnia film, it can be single layer structure, or multi-layer compound structure；
The second gate insulation layer 108 and second grid 109 above the first gate insulation layer 106 and first grid 107, should
Second gate insulation layer 108 can include the one or more in silicon nitride film, silicon oxide film and silicon oxynitride film,
It can be single layer structure, or multi-layer compound structure；
And the protective layer 110 above the second gate insulation layer 108 and second grid 109.
It should be noted that：In the preparation process of above-mentioned thin film transistor (TFT), specifically formed in the second gate insulation layer 108
Afterwards, it is necessary to carry out a hydrofluoric acid HF cleaning before second grid 109 is formed.That is, substrate is placed in hydrofluoric acid clean device
In, successively by ozone O3Oxidation processes-hydrofluoric acid HF cleanings-ozone O3The process of oxidation processes, it is intended to by semiconductor active layer
105 are uniformly aoxidized, so that during follow-up ELA (Excimer Laser Annealing, Excimer-Laser Crystallization)
Crystallization is more preferably uniform.
But hydrofluoric acid clean inevitably makes the surface of the second gate insulation layer 108 produce certain damage.Its
In, Fig. 2 is the surface damage number caused by the second gate insulation layer 108 of the hydrofluoric acid clean different condition by measuring
According to.Different condition described here for example can be different gate insulation layer thickness, different grid etch mode (wet method WET
Etching and inductively coupled plasma ICP etchings) etc..It follows that the thickness in the second gate insulation layer 108 isWithIn the case of, no matter using which kind of etching mode, the film layer at top and climbing hasLeft and right
It is thinned.
Illustrated below with an instantiation.Before hydrofluoric acid clean is carried out, as shown in Figure 3 and Figure 4, second gate is exhausted
The scanning analysis test result of edge layer 108 shows that thickness of second gate insulation layer 108 at the top of the thickness ratio at climbing is smallLeft and right.After hydrofluoric acid clean is carried out, as shown in figure 5, the second gate insulation layer 108 is scanned analysis test
As a result show, the second gate insulation layer 108 at climbing and top thickness be thinnedLeft and right.
So, for the tip position of the second gate insulation layer 108, TFT devices can be worked by thinned film layer
When electrology characteristic produce certain influence；It and will bring short for natively very thin climbing position, Reducing thickness so
The risk on road, so as to influence the stability of subsequent technique.Specifically, the thickness that the second gate insulation layer 108 deposits at climbing
Originally have it is certain be thinned, and had after hydrofluoric acid clean it is further be thinned, this collective effect being thinned twice causes
Reducing thickness at climbing reachesOn this basis, because the p-Si obtained after a-Si crystallization has in grain boundaries
Certain projection, therefore the risk that short circuit at climbing be present can be made.
Based on this, this example embodiment provides a kind of preparation method of thin film transistor (TFT), for preparing said structure
Double Tops gate type thin film transistor.As shown in fig. 6, the preparation method of the thin film transistor (TFT) 10 can include：
S1, with reference to shown in figure 7, formed with source electrode 103 and drain electrode 104, semiconductor active layer 105, the first gate insulation layer
106 and first grid 107 substrate on prepare the second gate insulation layer 108, and one is formed above the second gate insulation layer 108
Etch-protecting layer 200；
S2, with reference to shown in figure 8, the substrate formed with the second gate insulation layer 108 and etch-protecting layer 200 is placed in hydrofluoric acid
Oxidation processes and hydrofluoric acid clean are carried out in cleaning device, to remove etch-protecting layer 200 during hydrofluoric acid clean；
S3, with reference to shown in figure 9, prepare second grid 109 on by the substrate after hydrofluoric acid clean.
Wherein, the hydrofluoric acid clean device can include be sequentially connected oxidation processes unit, hydrofluoric acid clean unit,
Oxidation processes unit.
The preparation method for the thin film transistor (TFT) that disclosure illustrative embodiments are provided, to the second gate insulation layer 108
Carry out first forming an etch-protecting layer 200 on its surface before hydrofluoric acid clean, and by the substrate formed with etch-protecting layer 200
It is placed in hydrofluoric acid clean device in case cleaning.So, in hydrofluoric acid clean device, the etch-protecting layer 200 passes through
Oxidation processes can form an oxide-film, and the oxide-film can be to the second gate insulation layer 108 below when carrying out hydrofluoric acid clean
Play a protective role, so as to prevent the second gate insulation layer 108 by hf etching by excessive thinning, second gate is improved with this
The surface damage situation of insulating barrier 108, and then the electric property of thin film transistor (TFT) 10 can be ensured, and improve the steady of subsequent technique
It is qualitative.
The preparation method of the thin film transistor (TFT) in this example embodiment is described in detail below in conjunction with the accompanying drawings.
In step sl, with reference to shown in figure 7, formed with source electrode 103 and drain electrode 104, semiconductor active layer 105, first
The second gate insulation layer 108 is prepared on the substrate of gate insulation layer 106 and first grid 107, and on the second gate insulation layer 108
It is square into an etch-protecting layer 200.
It is described exhausted formed with source electrode 103 and drain 104, semiconductor active layer 105, the first grid in this example embodiment
The substrate of edge layer 106 and first grid 107 can include：Underlay substrate 101, it is formed at the buffering of the top of underlay substrate 101
Layer 102, be formed at source electrode 103, drain electrode 104 and the semiconductor active layer 105 of the top of cushion 102, be formed at source electrode 103,
Drain electrode 104 and the first gate insulation layer 106 of the top of semiconductor active layer 105, are formed at the top of the first gate insulation layer 106
First grid 107.
Wherein, semiconductor active layer 105 can be formed at the top of source electrode 103 and drain electrode 104, can also be formed at source electrode
103 and drain electrode 104 lower section, this is not construed as limiting here.
It should be noted that：" top " and " lower section " in the present embodiment is entered by foundation of the sequencing of preparation technology
Row explanation, i.e. for the structure that the structure being initially formed is formed under, afterwards upper, it is not exhausted with the relative position up and down in accompanying drawing
To relation.
Based on this, the second gate insulation layer 108 of the preparation can include：Pass through CVD (Chemical Vapor
Deposition, chemical vapor deposition) method forms silicon nitride SiN films, silicon oxide sio on aforesaid substrate2Film and nitrogen
One or more in silica SiNO films.Second gate insulation layer 108 can be single layer structure, or MULTILAYER COMPOSITE
Structure.
Certainly, the present embodiment is not limited thereto, and the second gate insulation layer 108 can also use other insulating materials to carry out
Prepare.
On this basis, the etch-protecting layer 200 that formed above the second gate insulation layer 108 can include：Pass through
CVD forms the etch-protecting layer 200 above the second gate insulation layer 108.
Wherein, the etch-protecting layer 200 can be with the second gate insulation layer 108 in for example same PECVD of same CVD equipment
Enter in (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition) equipment
It is prepared by row.So, Direct precipitation etch-protecting layer 200 after the second gate insulation layer 108 has been deposited in same equipment, can
Avoid introducing other impurity, so as to obtain high-quality film layer.
Preferably, the thickness of the etch-protecting layer 200 can be, both can be effective in the thickness range
Prevent the second gate insulation layer 108 during hydrofluoric acid clean by hf etching and by excessive thinning, be unlikely to increase again
The thickness of big second gate insulation layer 108, so as to ensure that thin film transistor (TFT) has good electric property.
In a kind of embodiment of this example, the etch-protecting layer 200 can be non-crystalline silicon a-Si films.In this situation
Under, one etch-protecting layer 200 of formation can be above the second gate insulation layer 108：One is formed above the second gate insulation layer 108
Layer non-crystalline silicon a-Si films.
In the another embodiment of this example, the etch-protecting layer 200 can also be silicon oxide sio2Film.Herein
In the case of, one etch-protecting layer 200 of formation can be above the second gate insulation layer 108：It is square on the second gate insulation layer 108
Into one layer of silicon oxide sio2Film.
In step s 2, with reference to shown in figure 8, the substrate formed with the second gate insulation layer 108 and etch-protecting layer 200 is put
Oxidation processes and hydrofluoric acid clean are carried out in hydrofluoric acid clean device, to remove etching protection during hydrofluoric acid clean
Layer 200.
In this example embodiment, the substrate needs to pass through ozone O successively in hydrofluoric acid clean device3At oxidation
Reason, hydrofluoric acid clean, ozone O3Oxidation processes.In O3During oxidation processes, the film layer especially substrate that is formed on the substrate
The etch-protecting layer 200 on surface can be oxidized and generate corresponding oxide, and the oxide can quilt when carrying out hydrofluoric acid clean
Etch away.
When etch-protecting layer 200 is non-crystalline silicon a-Si films, non-crystalline silicon a-Si films are in hydrofluoric acid clean device
By O3Silicon oxide sio will be converted to after oxidation processes2Film.In the case, can be first to oxygen during hydrofluoric acid clean
SiClx SiO2Film performs etching, and then may carry out a small amount of quarter to the second gate insulation layer 108 such as silicon nitride SiN films
Erosion, so can effectively reduce the surface damage to the second gate insulation layer 108.
It should be noted that：In the oxidizing process of non-crystalline silicon a-Si films, it there may be greatly according to the difference of its thickness
Portion of amorphous silicon a-Si is oxidized and situation not oxidized a small amount of non-crystalline silicon a-Si, and the non-crystalline silicon a-Si now remained also can
It is etched during hydrofluoric acid clean.
When etch-protecting layer 200 is silicon oxide sio2During film, the silicon oxide sio2Film passes through in hydrofluoric acid clean device
Cross O3Remained in that after oxidation processes as silicon oxide sio2Film.In the case, can be first to oxidation during hydrofluoric acid clean
Silicon SiO2Film performs etching, and then may carry out a small amount of quarter to the second gate insulation layer 108 such as silicon nitride SiN films
Erosion, so can effectively reduce the surface damage to the second gate insulation layer 108.
Relatively small for example exist in view of the thickness of etch-protecting layer 200Between, and silicon oxide sio2Film
Deposit thickness it is smaller when its homogeneity it is poor, therefore the present embodiment preferably using non-crystalline silicon a-Si films as it is described etching protect
Sheath 200.
In step s3, with reference to shown in figure 9, second grid 109 is prepared on the substrate after by hydrofluoric acid clean.
In this example embodiment, the second grid 109 is formed in the second gate insulation layer after hydrofluoric acid clean
On 108, protective layer 110 hereafter can be also formed above second grid 109.
Wherein, the material of first grid 107 and second grid 109 can be the metal or alloy such as molybdenum, tungsten, tantalum, molybdenum tungsten
Any of；The material of first gate insulation layer 106, the second gate insulation layer 108 and protective layer 110 can be silica,
Any of insulating materials such as silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide；The material of semiconductor active layer 105 can be
Any of monocrystalline silicon, non-crystalline silicon, polysilicon and metal-oxide semiconductor (MOS), and the present embodiment is preferably non-crystalline silicon warp
Later continuous ELA techniques and be converted to polysilicon.
Based on above description, the thin film transistor (TFT) 10 that this example embodiment is provided can be entered using above-mentioned preparation method
Prepared by row, so as to prevent the second gate insulation layer 108 by hf etching by excessive thinning, improve the second gate insulation layer with this
108 surface damage situation, and then the electric property of thin film transistor (TFT) 10 can be ensured, and improve the stability of subsequent technique.
This example embodiment additionally provides a kind of array base palte, including above-mentioned thin film transistor (TFT) 10.
Wherein, the array base palte can apply to LCD (Liquid Crystal Display, liquid crystal display), and with
Color membrane substrates form LCD to box.
Or the array base palte can also be applied to OLED (Organic Light Emitting Diode, organic light emission two
Pole pipe display), and oled panel is formed to box with package substrate.
Based on this, this example embodiment additionally provides a kind of display panel, including above-mentioned thin film transistor (TFT) 10 or
Above-mentioned array base palte.
By the thin film transistor (TFT) 10 that the present embodiment is provided has stable electric property, therefore apply the film crystal
The display panel of pipe 10 can also obtain good display effect.
This example embodiment additionally provides a kind of display device, including above-mentioned display panel.
Wherein, the display device can for example include mobile phone, tablet personal computer, television set, notebook computer, digital phase
Any product or part with display function such as frame, navigator, the disclosure is to this without particular determination.
Those skilled in the art will readily occur to the disclosure its after considering specification and putting into practice invention disclosed herein
Its embodiment.The application is intended to any modification, purposes or the adaptations of the disclosure, these modifications, purposes or
Person's adaptations follow the general principle of the disclosure and including the undocumented common knowledges in the art of the disclosure
Or conventional techniques.Description and embodiments are considered only as exemplary, and the true scope of the disclosure and spirit are by appended
Claim is pointed out.
It should be appreciated that the precision architecture that the disclosure is not limited to be described above and is shown in the drawings, and
And various modifications and changes can be being carried out without departing from the scope.The scope of the present disclosure is only limited by appended claim.
Claims (12)
- A kind of 1. preparation method of top gate type thin film transistor, it is characterised in that including：Second is prepared on the substrate formed with semiconductor active layer, source electrode and drain electrode, the first gate insulation layer and first grid Gate insulation layer, and form an etch-protecting layer above second gate insulation layer；Substrate formed with second gate insulation layer and the etch-protecting layer is placed in hydrofluoric acid clean device and carries out oxygen Change processing and hydrofluoric acid clean, to remove the etch-protecting layer during the hydrofluoric acid clean；Second grid is prepared on the substrate after by the hydrofluoric acid clean.
- 2. preparation method according to claim 1 a, it is characterised in that etching is formed above second gate insulation layer Protective layer includes：One layer of amorphous silicon membrane is formed above second gate insulation layer.
- 3. preparation method according to claim 2, it is characterised in that will be formed with second gate insulation layer and the quarter The substrate of erosion protective layer, which is placed in progress oxidation processes in hydrofluoric acid clean device, to be included：Substrate formed with second gate insulation layer and the amorphous silicon membrane is placed in hydrofluoric acid clean device carry out it is smelly Oxygen oxidation processes, so that the amorphous silicon membrane is converted to silicon oxide film.
- 4. preparation method according to claim 1 a, it is characterised in that etching is formed above second gate insulation layer Protective layer includes：One layer of silicon oxide film is formed above second gate insulation layer.
- 5. according to the preparation method described in claim any one of 1-4, it is characterised in that the thickness of the etch-protecting layer is
- 6. preparation method according to claim 1, it is characterised in that second gate insulation layer and the etch-protecting layer Prepared in same film deposition equipment.
- 7. preparation method according to claim 6, it is characterised in that formed with semiconductor active layer, source electrode and drain electrode, The second gate insulation layer is prepared on the substrate of first gate insulation layer and first grid to be included：Nitridation is formed on the substrate formed with semiconductor active layer, source electrode and drain electrode, the first gate insulation layer and first grid One or more in silicon thin film, silicon oxide film and silicon oxynitride film.
- 8. preparation method according to claim 1, it is characterised in that described formed with semiconductor active layer, source electrode and leakage The substrate of pole, the first gate insulation layer and first grid includes：Underlay substrate；The source electrode being formed above the underlay substrate and drain electrode；The semiconductor active layer being formed above the source electrode and the drain electrode；The first gate insulation layer being formed above the semiconductor active layer；AndThe first grid being formed above first gate insulation layer.
- 9. preparation method according to claim 8, it is characterised in that described formed with semiconductor active layer, source electrode and leakage The substrate of pole, the first gate insulation layer and first grid also includes：The underlay substrate is formed at towards the cushion of the semiconductor active layer side.
- 10. a kind of top gate type thin film transistor, it is characterised in that the top gate type thin film transistor is appointed using claim 1-9 Preparation method described in one is prepared.
- 11. a kind of array base palte, it is characterised in that including the top gate type thin film transistor described in claim 10.
- 12. a kind of display panel, it is characterised in that including the top gate type thin film transistor described in claim 10.
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Cited By (1)
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| WO2020232946A1 (en) * | 2019-05-22 | 2020-11-26 | 深圳市华星光电半导体显示技术有限公司 | Structure with improved metal oxide tft characteristics and manufacturing method therefor |
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| US4960719A (en) * | 1988-02-04 | 1990-10-02 | Seikosha Co., Ltd. | Method for producing amorphous silicon thin film transistor array substrate |
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