CN107831391B - A kind of method, apparatus and equipment for burn-in test - Google Patents

A kind of method, apparatus and equipment for burn-in test Download PDF

Info

Publication number
CN107831391B
CN107831391B CN201711212555.2A CN201711212555A CN107831391B CN 107831391 B CN107831391 B CN 107831391B CN 201711212555 A CN201711212555 A CN 201711212555A CN 107831391 B CN107831391 B CN 107831391B
Authority
CN
China
Prior art keywords
test
group
period
burn
functional areas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201711212555.2A
Other languages
Chinese (zh)
Other versions
CN107831391A (en
Inventor
杨涛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Products Chengdu Co Ltd
Intel Corp
Original Assignee
Intel Products Chengdu Co Ltd
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Products Chengdu Co Ltd, Intel Corp filed Critical Intel Products Chengdu Co Ltd
Priority to CN201711212555.2A priority Critical patent/CN107831391B/en
Publication of CN107831391A publication Critical patent/CN107831391A/en
Application granted granted Critical
Publication of CN107831391B publication Critical patent/CN107831391B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer

Abstract

The present invention relates to a kind of method, apparatus and equipment for burn-in test, this method comprises: when carrying out burn-in test to electronic product, during the period each of first at least one period group period of the burn-in test, at least one functional areas of Xiang Suoshu electronic product apply one of test voltage in first group of test voltage;And, during the period each of second at least one period group period of the burn-in test, apply one of test voltage in second group of test voltage at least one described functional areas, wherein, first group of period described in the burn-in test is before second group of period, and the test voltage in first group of test voltage is greater than the test voltage in second group of test voltage.The burn-in test time of electronic product is reduced in the case that this method, device and equipment the risk of thermal runaway can occur not increasing electronic product and ensure burn-in test effect.

Description

A kind of method, apparatus and equipment for burn-in test
Technical field
The present invention relates to burn-in test fields, the more particularly, to method, apparatus and equipment of burn-in test.
Background technique
Electronic product including including chip etc. needs to carry out burn-in test (BI:Burn before factory after producing In) to filter out the electronic product of the meeting initial failure in normal use process, the electronics these meeting initial failures is avoided to produce Product consign to client.Therefore, burn-in test is an essential processing of the electronic product before factory.
The burn-in test process of electronic product is specific as follows: after electronic product is heated to predetermined temperature, to electronics Product, which applies voltage and input test data, makes its work certain time to accelerate its ageing process, and observing it dduring test is No failure is rejected if its failure and is flowed into client's hand to avoid it.
Existing ageing testing method usually in test to all functional areas of electronic product only apply one it is unified Changeless voltage.Since the voltage that electronic product is applied in burn-in test is higher, there is thermal runaway in electronic product Risk is bigger, therefore, the risk of thermal runaway occurs in order to reduce electronic product, and the unified changeless voltage is relatively It is small.However, therefore, it is necessary to carry out the longer time to electronic product since the unified changeless voltage is relatively small Test, could in normal use process can the electronic product of initial failure screen, which increase the burn-in test time, Burn-in test is caused to become the production capacity bottleneck of production electronic product.But it is if opposite in the unified changeless voltage In lesser situation, in order to enable when burn-in test does not become the production capacity bottleneck of production electronic product and shortens burn-in test by force Between, it is likely that the electronic product of some meeting initial failures in normal use process cannot detected, this will lead to aging Test effect is bad.
Summary of the invention
In view of problem above, the embodiment of the present invention provides a kind of method, apparatus and equipment for burn-in test, energy It is enough that the old of electronic product is reduced in the case where not increasing electronic product and the risk of thermal runaway occur and ensure burn-in test effect Change the testing time.
A kind of method for burn-in test of embodiment according to the invention, comprising: aging is being carried out to electronic product When test, during the period each of first at least one period group period of the burn-in test, Apply one of test voltage in first group of test voltage at least one functional areas of the electronic product;And During period each of second at least one period group period of the burn-in test, Xiang Suoshu is at least One functional areas apply one of test voltage in second group of test voltage, wherein the described in the burn-in test One group of period before second group of period, and, test voltage in first group of test voltage is greater than described Test voltage in second group of test voltage.
A kind of device for burn-in test of embodiment according to the invention, comprising: first applies module, for right It is every in first at least one period group period of the burn-in test when electronic product carries out burn-in test During one period, at least one functional areas of Xiang Suoshu electronic product apply one of survey in first group of test voltage Try voltage;And second apply module, for second at least one period group period in the burn-in test Each of during the period, apply one of test electricity in second group of test voltage at least one described functional areas Pressure, wherein first group of period described in the burn-in test before second group of period, and, described first Test voltage in group test voltage is greater than the test voltage in second group of test voltage.
A kind of equipment for burn-in test of embodiment according to the invention, comprising: processor;And memory, On be stored with executable instruction, wherein the executable instruction makes the processor execute method above-mentioned upon being performed.
A kind of machine readable media of embodiment according to the invention, is stored thereon with executable instruction, wherein it is described can It executes instruction and machine is made to execute method above-mentioned upon being performed.
It can be seen from the above that first group time of the scheme of the embodiment of the present invention before burn-in test Apply higher test voltage at least one functional areas for the electronic product for being aging test during section, so that using less survey The examination time can test out the product whether electronic product belongs to the meeting initial failure in normal use process, thus this hair The scheme of bright embodiment can reduce the burn-in test time of electronic product in the case where ensuring burn-in test effect, and And the scheme of the embodiment of the present invention during first group of period before burn-in test to electronic product at least one Functional areas apply higher test voltage and during subsequent second group of period of burn-in test to electronic product at least One functional areas apply lower test voltage, thus, total amount of heat caused by electronic product is not during entire burn-in test Meeting is much and generated heat density will not be very high, therefore the scheme of the embodiment of the present invention not will increase electronic product appearance The risk of thermal runaway.
Detailed description of the invention
The features and advantages of the present invention will become apparent by following description with reference to the accompanying drawings.
Fig. 1 shows the overview flow chart of the method for burn-in test of one embodiment according to the invention;
Fig. 2 shows the flow charts of the method for burn-in test of one embodiment according to the invention;
Fig. 3 shows the schematic diagram of the device for burn-in test of one embodiment according to the invention;
Fig. 4 shows the schematic diagram of the equipment for burn-in test of one embodiment according to the invention.
Specific embodiment
Theme described herein is discussed referring now to example embodiment.It should be understood that discussing these embodiments only It is in order to enable those skilled in the art can better understand that being not to claim to realize theme described herein Protection scope, applicability or the exemplary limitation illustrated in book.It can be in the protection scope for not departing from present disclosure In the case of, the function and arrangement of the element discussed are changed.Each example can according to need, omit, substitute or Add various processes or component.For example, described method can be executed according to described order in a different order, with And each step can be added, omits or combine.In addition, feature described in relatively some examples is in other examples It can be combined.
As used in this article, term " includes " and its modification indicate open term, are meant that " including but not limited to ". Term "based" indicates " being based at least partially on ".Term " one embodiment " and " embodiment " expression " at least one implementation Example ".Term " another embodiment " expression " at least one other embodiment ".Term " first ", " second " etc. may refer to not Same or identical object.Here may include other definition, either specific or implicit.Unless bright in context It really indicates, otherwise the definition of a term is consistent throughout the specification.
Fig. 1 shows the overview flow chart of the method for burn-in test of one embodiment according to the invention.At this In embodiment, method 100 shown in FIG. 1 is described as the example of burn-in test object using chip.
Chip generally includes the functional areas (for example, image processing function area etc.) for being easy to initial failure and is not easy to lose in early days Effect functional areas (for example, core function area, the input and output functional areas (IO:input/output) and System Agent (SA: System agent) functional areas etc.), wherein compared with the functional areas for being not easy to initial failure, it is easy to the functional areas of initial failure With higher defect concentration (DD:Defect Density) and initial failure (IM:Infant Mortality) ratio, In, initial failure ratio indicates that the ratio of initial failure occurs in normal use process in the electronic product including chip.
In the present embodiment, before starting to execute method 100 shown in FIG. 1, three test voltages V1, V2 are preset And V3, wherein V1 > V2 > V3.Such as, but not limited to, V1=1.5v, V2=1.375v and V3=1.35v.
In addition, in the present embodiment, before starting to execute method 100 shown in FIG. 1, also in advance available each survey Examination data sequence is divided into two groups of sequence of test data, i.e. first group of sequence of test data G1 and second group of sequence of test data G2, Wherein, compared with second group of sequence of test data G2, the sequence of test data in first group of sequence of test data G1 can make Chip generates more heats during burn-in test, so that the risk that thermal runaway occurs in chip can be higher.
As shown in Figure 1, tested chip C is heated to predetermined temperature by aging testing apparatus B in box 102.
In box 104, after chip C is heated to predetermined temperature, aging testing apparatus B carries out aging survey to chip C Examination.
The burn-in test of chip C is divided into first stage S1 and second stage S2 in time, wherein the first stage, S1 was accounted for According to the first time period T1 of burn-in test, and second stage S2 occupies the second time period T2 of burn-in test, second time period T2 And then after first time period T1.First time period T1 is certain being carved among burn-in test at the beginning of burn-in test The period of a predetermined instant, second time period T2 are from the finish time of first time period T1 to the finish time of burn-in test Period.Such as, but not limited to, first time period T1 is when being carved into the 80% of burn-in test at the beginning of burn-in test Long period, second time period T2 grow to the period of 100% duration of burn-in test when being from the 80% of burn-in test.
During the first stage S1 of burn-in test, i.e., during the first time period T1 of burn-in test, burn-in test is set Standby B applies voltage V1 to the functional areas for being easy to initial failure of chip C and inputs the test in second group of sequence of test data G2 Data sequence, and, apply second group of test data sequence of voltage V2 and input to the functional areas for being not easy to initial failure of chip C Arrange the sequence of test data in G2.
During the second stage S2 of burn-in test, i.e., during the second time period T2 of burn-in test, burn-in test is set Standby B applies voltage V3 to the functional areas for being easy to initial failure of chip C and inputs the test in first group of sequence of test data G1 Data sequence, and, apply second group of test data sequence of voltage V2 and input to the non-functional areas for being easy to initial failure of chip C Arrange the sequence of test data in G2.
Wherein, the early stage that is not easy to the functional areas input test data sequence of the easy initial failure of chip C and to chip C loses The functional areas input test data sequence of effect can be parallel or it is serial.
In box 106, during burn-in test, aging testing apparatus B checks whether chip C fails.
In box 108, after burn-in test terminates, aging testing apparatus B stops applying voltage to chip C and input is surveyed Try data sequence and cooled wafer C.
It can be seen from the above that in the method for the present embodiment, due to phase first stage S1 in burn-in test Between apply higher voltage V1 to the easy initial failure functional areas of chip C and therefore can test out chip using less time Whether C belongs to the product of the meeting initial failure in normal use process, thus the method for the present embodiment can ensure aging The burn-in test time of electronic product is reduced in the case where test effect.
In addition, in the method for the present embodiment, due to during the first stage S1 before burn-in test to chip C's The functional areas for being easy to initial failure apply higher test voltage V1 and input so that chip C generates less heat in burn-in test The sequence of test data of amount, to the function of being easy to initial failure of chip C during the subsequent second stage S2 of burn-in test Area applies lower test voltage V3 and input so that chip C generates the sequence of test data of more heats in burn-in test, And to the function for being not easy to initial failure of chip C during entire burn-in test (i.e. first stage S1 and second stage S2) Energy area applies moderate test voltage V2 and input so that chip C generates the test data sequence of less heat in burn-in test Column, therefore, during entire burn-in test total amount of heat caused by chip C will not many and generated heat density will not be very Height, because there is the risk of thermal runaway without increased core piece C.
Other modifications
Although it will be understood by those skilled in the art that in the above embodiments, during the first stage S1 of burn-in test It inputs to the functional areas for being easy to initial failure of chip C so that chip C generates the test data of less heat in burn-in test Sequence, and, it is inputted to the functional areas for being easy to initial failure of chip C so that chip during the second stage S2 of burn-in test C generates the sequence of test data of more heats in burn-in test, so that the functional areas for being easy to initial failure of chip C can obtain To more comprehensive test, however, the present invention is not limited thereto.In some other embodiment of the invention, for example, old It is all inputted to the functional areas for being easy to initial failure of chip C so that chip during changing the first stage S1 and second stage S2 of test C generates the sequence of test data of less heat in burn-in test, so that the heat that chip C is generated in burn-in test is more It is few, it further decreases chip C and the risk of thermal runaway occurs.
Although it will be understood by those skilled in the art that in the above embodiments, in the first stage S1 of burn-in test and V3 all is applied more than to the functional areas for being not easy to initial failure of chip C during two-stage S2 and is less than the test voltage V2 of V1, However, the present invention is not limited thereto.In some other embodiment of the invention, it is also possible to the first rank in burn-in test To the functional areas for being not easy to initial failure of chip C apply higher test voltage V1 during section S1 and behind burn-in test Second stage S2 during to the functional areas for being not easy to initial failure of chip C apply lower test voltage V3.In this feelings Under condition, second group can be inputted to the functional areas for being not easy to initial failure of chip C during the first stage S1 of burn-in test Sequence of test data in sequence of test data G2 and early stage is not easy to chip C during the second stage S2 of burn-in test The functional areas of failure input the sequence of test data in first group of sequence of test data G1, alternatively, can be the of burn-in test Second group of test data sequence all is inputted to the functional areas for being not easy to initial failure of chip C during one stage S1 and second stage S2 Arrange the sequence of test data in G2.
Although it will be understood by those skilled in the art that in the above embodiments, being not easy to early stage to C in burn-in test The functional areas of failure input so that chip C generates the survey in second group of sequence of test data G2 of less heat in burn-in test Data sequence is tried, however, the present invention is not limited thereto.In some other embodiment of the invention, it can also be surveyed in aging It is inputted to the functional areas for being not easy to initial failure of C so that chip C generates first group of more heats in burn-in test when examination Sequence of test data in sequence of test data G1.
Although it will be understood by those skilled in the art that in the above embodiments, during the first stage S1 of burn-in test All only apply to the functional areas for being easy to initial failure of chip C or entire chip C with during the second stage S2 of burn-in test One changeless test voltage (that is, V1 and V3), however, the present invention is not limited thereto.In some other of the invention In embodiment, first stage S1 can also be further divided into multiple periods and be further divided into second stage S2 more A period, wherein in the first stage to chip C's during each period of multiple periods of S1 institute further division The functional areas or entire chip C that are easy to initial failure apply one in first group of voltage including multiple and different test voltages Different test voltages, and, during each period of multiple periods of second stage S2 institute further division to The functional areas for being easy to initial failure of chip C or entire chip C apply second group of voltage including multiple and different test voltages In a different test voltage, wherein each of first group of voltage test voltage is both greater than test voltage V2, and Each of second group of voltage test voltage is both less than test voltage V2.
It will be understood by those skilled in the art that the method for above embodiment is not only applicable to chip, it is also applied in addition to core Other types of suitable electronic product except piece.
Fig. 2 shows a kind of flow charts of method for burn-in test of one embodiment according to the invention.Fig. 2 institute The method 200 shown can for example be executed by aging testing apparatus or any other suitable equipment.
As shown in Fig. 2, method 200 may include, in box 202, when carrying out burn-in test to electronic product, described During period each of first at least one period group period of burn-in test, Xiang Suoshu electronic product At least one functional areas apply first group of test voltage in one of test voltage.
Method 200 can also include, in box 204, in second at least one period of the burn-in test During the group period each of period, apply wherein one in second group of test voltage at least one described functional areas A test voltage, wherein first group of period described in the burn-in test before second group of period, and, Test voltage in first group of test voltage is greater than the test voltage in second group of test voltage.
In one aspect, the electronic product includes first group of functional areas and second group of functional areas, wherein with described second Group functional areas are compared, and first group of functional areas have higher defect concentration and initial failure ratio, and, described at least one A functional areas include first group of functional areas, wherein method 200 can also include: the Xiang Suoshu during the burn-in test Second group of functional areas applies nominative testing voltage, wherein the nominative testing voltage is less than in first group of test voltage Test voltage but the test voltage being greater than in second group of test voltage.
On the other hand, at least one described functional areas include all functional areas of the electronic product.
In yet another aspect, method 200 can also include: in each of second group of period phase period Between, the test data in first group of sequence of test data or second group of sequence of test data is inputted at least one described functional areas Sequence;And during the period each of first group of period, to described in the input of at least one described functional areas Sequence of test data in second group of sequence of test data, wherein compared with second group of sequence of test data, described first Group sequence of test data makes the electronic product generate more heats in the burn-in test.
Fig. 3 shows a kind of schematic diagram of device for burn-in test of one embodiment according to the invention.Fig. 3 institute The device 300 shown can use the mode of software, hardware or software and hardware combining to realize.Device 300 for example may be mounted at always Change in test equipment or any other suitable equipment.
As shown in figure 3, device 300 may include that the first application module 302 and second applies module 304.First applies mould Block 302 is used for when carrying out burn-in test to electronic product, in first at least one period of the burn-in test During period each of group period, at least one functional areas of Xiang Suoshu electronic product apply first group of test voltage In one of test voltage.Second, which applies module 304, was used in the burn-in test at least one period During period each of second group of period, apply its in second group of test voltage at least one described functional areas In a test voltage, wherein first group of period described in the burn-in test before second group of period, with And the test voltage in first group of test voltage is greater than the test voltage in second group of test voltage.
In one aspect, the electronic product includes first group of functional areas and second group of functional areas, wherein with described second Group functional areas are compared, and first group of functional areas have higher defect concentration and initial failure ratio, and, described at least one A functional areas include first group of functional areas, wherein device 300 can also include: that third applies module, for described old During changing test, the second group of functional areas Xiang Suoshu apply nominative testing voltage, wherein the nominative testing voltage is less than described the Test voltage in one group of test voltage but the test voltage being greater than in second group of test voltage.
On the other hand, at least one described functional areas include all functional areas of the electronic product.
In yet another aspect, device 300 can also include: the first input module, in second group of period Each period during, input first group of sequence of test data or second group of test data at least one described functional areas Sequence of test data in sequence;And second input module, in the period each of first group of period Period inputs the sequence of test data in second group of sequence of test data at least one described functional areas, wherein with institute It states second group of sequence of test data to compare, first group of sequence of test data makes the electronic product in the burn-in test When generate more heats.
Fig. 4 shows a kind of schematic diagram of equipment for burn-in test of one embodiment according to the invention.Such as Fig. 4 Shown, equipment 400 may include processor 402 and memory 404, wherein it is stored with executable instruction on memory 404, In, the executable instruction makes processor 402 execute method 100 shown in FIG. 1 or method shown in Fig. 2 upon being performed 200。
The embodiment of the present invention also provides a kind of machine readable media, is stored thereon with executable instruction, wherein it is described can It executes instruction and machine is made to execute method 100 or method shown in Fig. 2 200 shown in FIG. 1 upon being performed.
The specific embodiment illustrated above in conjunction with attached drawing describes exemplary embodiment, it is not intended that may be implemented Or fall into all embodiments of the protection scope of claims." exemplary " meaning of the term used in entire this specification Taste " be used as example, example or illustration ", be not meant to than other embodiments " preferably " or " there is advantage ".For offer pair The purpose of the understanding of described technology, specific embodiment include detail.However, it is possible in these no details In the case of implement these technologies.In some instances, public in order to avoid the concept to described embodiment causes indigestion The construction and device known is shown in block diagram form.
The foregoing description of present disclosure is provided so that any those of ordinary skill in this field can be realized or make Use present disclosure.To those skilled in the art, the various modifications carried out to present disclosure are apparent , also, can also answer generic principles defined herein in the case where not departing from the protection scope of present disclosure For other modifications.Therefore, present disclosure is not limited to examples described herein and design, but disclosed herein with meeting Principle and novel features widest scope it is consistent.

Claims (6)

1. a kind of method for burn-in test, comprising:
When carrying out burn-in test to electronic product, after the electronic product is heated to predetermined temperature, in the aging During period each of first at least one period group period of test, Xiang Suoshu electronic product is extremely Few functional areas apply one of test voltage in first group of test voltage;And
During the period each of second at least one period group period of the burn-in test, to institute One of test voltage in second group of test voltage of at least one functional areas application is stated,
Wherein, in the burn-in test, first group of period before second group of period, and, described Test voltage in one group of test voltage is greater than the test voltage in second group of test voltage,
Wherein, the electronic product includes first group of functional areas and second group of functional areas, wherein with second group of functional areas phase Than, first group of functional areas have higher defect concentration and initial failure ratio, and, at least one functional areas packet First group of functional areas are included,
Wherein, the method also includes: during the burn-in test, the second group of functional areas Xiang Suoshu apply nominative testing electricity Pressure, wherein the nominative testing voltage is less than the test voltage in first group of test voltage but is greater than second group of survey Try the test voltage in voltage.
2. the method for claim 1, wherein further include:
During the period each of second group of period, first group of test is inputted at least one described functional areas Sequence of test data in data sequence or second group of sequence of test data;And
During the period each of first group of period, to described second group of at least one described functional areas input Sequence of test data in sequence of test data,
Wherein, compared with second group of sequence of test data, first group of sequence of test data makes the electronic product More heats are generated in the burn-in test.
3. a kind of device for burn-in test, comprising:
First applies module, for when carrying out burn-in test to electronic product, the electronic product to be heated to predetermined temperature After degree, during the period each of first at least one period group period of the burn-in test, Apply one of test voltage in first group of test voltage at least one functional areas of the electronic product;And
Second applies module, for each in second at least one period group period of the burn-in test During a period, apply one of test voltage in second group of test voltage at least one described functional areas,
Wherein, in the burn-in test, first group of period before second group of period, and, described Test voltage in one group of test voltage is greater than the test voltage in second group of test voltage,
Wherein, the electronic product includes first group of functional areas and second group of functional areas, wherein with second group of functional areas phase Than, first group of functional areas have higher defect concentration and initial failure ratio, and, at least one functional areas packet First group of functional areas are included,
Wherein, described device further include: third applies module, is used for second group of function of Xiang Suoshu during the burn-in test Area apply nominative testing voltage, wherein the nominative testing voltage be less than first group of test voltage in test voltage but Greater than the test voltage in second group of test voltage.
4. device as claimed in claim 3, wherein further include:
First input module is used for during the period each of second group of period, at least one described function Energy area inputs the sequence of test data in first group of sequence of test data or second group of sequence of test data;And
Second input module is used for during the period each of first group of period, at least one described function Energy area inputs the sequence of test data in second group of sequence of test data,
Wherein, compared with second group of sequence of test data, first group of sequence of test data makes the electronic product More heats are generated in the burn-in test.
5. a kind of equipment for burn-in test, comprising:
Processor;And
Memory is stored thereon with executable instruction, wherein the executable instruction holds the processor Any one of method in row claim 1-2.
6. a kind of machine readable media, is stored thereon with executable instruction, wherein the executable instruction makes upon being performed Machine perform claim requires any one of method in 1-2.
CN201711212555.2A 2017-11-28 2017-11-28 A kind of method, apparatus and equipment for burn-in test Active CN107831391B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201711212555.2A CN107831391B (en) 2017-11-28 2017-11-28 A kind of method, apparatus and equipment for burn-in test

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201711212555.2A CN107831391B (en) 2017-11-28 2017-11-28 A kind of method, apparatus and equipment for burn-in test

Publications (2)

Publication Number Publication Date
CN107831391A CN107831391A (en) 2018-03-23
CN107831391B true CN107831391B (en) 2019-06-07

Family

ID=61646105

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711212555.2A Active CN107831391B (en) 2017-11-28 2017-11-28 A kind of method, apparatus and equipment for burn-in test

Country Status (1)

Country Link
CN (1) CN107831391B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11862269B2 (en) 2020-07-17 2024-01-02 Changxin Memory Technologies, Inc. Testing method for packaged chip, testing system for packaged chip, computer device and storage medium

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116665751B (en) * 2022-12-16 2024-04-02 荣耀终端有限公司 Test method and electronic equipment

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1113348A (en) * 1994-03-10 1995-12-13 三星电子株式会社 Semiconductor integrated circuit with a stress circuit and method for suppluing a stress voltage thereof
CN1280386A (en) * 1999-04-20 2001-01-17 国际商业机器公司 Equipment and method for screening test of fault leakage of storage device
CN1714489A (en) * 2003-02-20 2005-12-28 国际商业机器公司 Test by using independently controllable voltage islands
CN101160533A (en) * 2004-12-22 2008-04-09 桑迪士克股份有限公司 Contactless wafer level burn-in
CN101968533A (en) * 2010-08-31 2011-02-09 安徽师范大学 Aging and temperature test method of LED lamp
CN103018646A (en) * 2011-09-21 2013-04-03 北京大学深圳研究生院 High-temperature wafer level burn-in test scheduling method for SoC (system on a chip) chip

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7473568B2 (en) * 2006-05-17 2009-01-06 Kingston Technology Corp. Memory-module manufacturing method with memory-chip burn-in and full functional testing delayed until module burn-in
US9714966B2 (en) * 2012-10-05 2017-07-25 Texas Instruments Incorporated Circuit aging sensor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1113348A (en) * 1994-03-10 1995-12-13 三星电子株式会社 Semiconductor integrated circuit with a stress circuit and method for suppluing a stress voltage thereof
CN1280386A (en) * 1999-04-20 2001-01-17 国际商业机器公司 Equipment and method for screening test of fault leakage of storage device
CN1714489A (en) * 2003-02-20 2005-12-28 国际商业机器公司 Test by using independently controllable voltage islands
CN101160533A (en) * 2004-12-22 2008-04-09 桑迪士克股份有限公司 Contactless wafer level burn-in
CN101968533A (en) * 2010-08-31 2011-02-09 安徽师范大学 Aging and temperature test method of LED lamp
CN103018646A (en) * 2011-09-21 2013-04-03 北京大学深圳研究生院 High-temperature wafer level burn-in test scheduling method for SoC (system on a chip) chip

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11862269B2 (en) 2020-07-17 2024-01-02 Changxin Memory Technologies, Inc. Testing method for packaged chip, testing system for packaged chip, computer device and storage medium

Also Published As

Publication number Publication date
CN107831391A (en) 2018-03-23

Similar Documents

Publication Publication Date Title
CN107831391B (en) A kind of method, apparatus and equipment for burn-in test
CN103946854B (en) The intrinsic fingerprint recognition based on reservation being characterized with fuzzy algorithmic approach and dynamic key
TWI439831B (en) Method and apparatus for scheduling a use of test resources of a test arrangement for the execution of test groups
DE102012024886A1 (en) Boundary scan chain for stacked memory
US9970986B2 (en) Integrated circuit authentication
CN105448348B (en) A kind of chip restorative procedure and device
CN101133340B (en) Test device, test method, electronic device manufacturing method, test simulator, and test simulation method
US11522724B2 (en) SRAM as random number generator
CN102224428A (en) Testing method and program product used therein
CN108334428B (en) Parallel testing method for system functions
WO2021184873A1 (en) Method and apparatus for data synchronization in blockchain network, and computing device
US20180307862A1 (en) Security techniques based on memory timing characteristics
CN108279369A (en) A kind of test method of multi-chip parallel circuit transient current and heat distribution unevenness
US7921344B2 (en) Multi-stage data processor with signal repeater
CN109597728A (en) The control method and device of test equipment, computer readable storage medium
Schmidt et al. From clean room to machine room: commissioning of the first-generation BrainScaleS wafer-scale neuromorphic system
Zhang et al. Reliability analysis of interdependent networks using percolation theory
Argentieri et al. Complete positivity and thermodynamics in a driven open quantum system
CN107305792A (en) A kind of method and apparatus for testing memory
KR20110131634A (en) Bank group refresh control device
Maeda et al. Detailed fluctuation theorem from the one-time measurement scheme
Bordier et al. Time‐resolved detection of stimulus/task‐related networks, via clustering of transient intersubject synchronization
US20220321575A1 (en) Dag-awtc ledger system using bft verification consensus mechanism
CN107679237A (en) A kind of distributed data base management system (DDBMS), method and device
CN105652966B (en) starting method and server device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant