KR20110131634A - Bank group refresh control device - Google Patents

Bank group refresh control device Download PDF

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Publication number
KR20110131634A
KR20110131634A KR1020100051172A KR20100051172A KR20110131634A KR 20110131634 A KR20110131634 A KR 20110131634A KR 1020100051172 A KR1020100051172 A KR 1020100051172A KR 20100051172 A KR20100051172 A KR 20100051172A KR 20110131634 A KR20110131634 A KR 20110131634A
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KR
South Korea
Prior art keywords
refresh
bank group
address
counter
refresh operation
Prior art date
Application number
KR1020100051172A
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Korean (ko)
Inventor
강용구
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020100051172A priority Critical patent/KR20110131634A/en
Publication of KR20110131634A publication Critical patent/KR20110131634A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40618—Refresh operations over multiple banks or interleaving
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

The present invention relates to a bank group refresh control apparatus for controlling a refresh operation for each bank group. According to an aspect of the present invention, there is provided a plurality of bank groups including a plurality of banks, and includes: a refresh counter configured to separately perform refresh operation control for each bank group and refresh operation control of all banks; And an address latch for generating a row address by inputting an external address independently of the refresh operation.

Description

Bank group refresh control unit {BANK GROUP REFRESH CONTROL DEVICE}

The present invention relates to a bank group refresh control apparatus for controlling a refresh operation for each bank group.

The semiconductor memory device has a plurality of banks, one bank is composed of 256MB. FIG. 1 shows a bank structure having 8 banks in 2 Gb density and one bank having 256 MB.

In the conventional bank structure configured as described above, the address latch unit 10 includes an address latch unit 10 that receives an external address A <0:14> and generates LA <0:14> that has passed through the address latch. The row address generated at 10 is configured to be used by the refresh counter 20. That is, the refresh counter 20 is configured to perform a simultaneous refresh operation on all banks during the auto refresh operation using the row address generated by the address latch unit 10.

The refresh counter comprises a counter portion 40, 41... And an address latch 30 shown in FIG. 2. The counter unit generates a RAT <0> address by inputting the signal REFA generated during the refresh operation to the first unit UNIT of the counter. The RAT <0> address is input to the next unit to generate the RAT <1> address. This process is performed sequentially so that the RAT <0:14> addresses are sequentially generated according to the refresh operation.

The address latch 30 included in the refresh counter 20 inputs the address LA <0:14> generated by the address latch 10, and generates a row address (i.e., an active command ACT) during normal operation. RA <0:14>) is output as is.

In addition, the RAT <0:14> signal generated by the counter unit 40, 41 ... is passed through the address latch 30 by the refresh command REFA generated when the refresh command is input. It is output as an address value.

That is, in the normal active operation, the LA <0:14> signal generated by the address latch 10 is controlled to pass through the address latch 30 by the normal active command, and the word is increased while increasing the generated row address. Activate the line. In addition, during the refresh operation, the RAT <0:14> signal generated by the counter unit is controlled to pass through the address latch 30 by a refresh command, and the word line is activated while increasing the generated row address. (tRAS: ACTIVE PRECHARGE COMMAND PERIOD) After precharge operation (PCG), the cell data is restored (RESTORE).

Therefore, conventionally, the address latch 10 for generating row addresses cannot be used in the refresh operation. Therefore, in a bank structure having a plurality of bank group structures, other operations cannot be performed at all until the refresh operation is completed.

In particular, as shown in FIG. 3 in the course of performing the refresh operation of all banks, a time from the refresh command to the refresh command or the refresh command to the active command is performed after the bank activation by the refresh command. There is a problem that a row address signal cannot be obtained for other operations during tRFC. That is, there is a problem in that a dead time of the system occurs because no operation is performed during the auto refresh operation.

Accordingly, an object of the present invention is to provide a bank group refresh control apparatus capable of more efficiently using a row address.

According to an aspect of the present invention, there is provided a plurality of bank groups including a plurality of banks, and includes: a refresh counter configured to separately perform refresh operation control for each bank group and refresh operation control of all banks; And an address latch for generating a row address by inputting an external address independently of the refresh operation.

The present invention is configured to separately use the row address of the latch unit while performing a refresh operation for each bank group. Accordingly, the present invention is configured to allow the access of the other banks according to different operations while one bank performs the refresh operation, thereby minimizing the dead time of the system.

1 is a diagram illustrating a bank structure including a plurality of banks in the related art.
2 is a configuration diagram included in a conventional refresh counter.
3 is a timing diagram of a conventional refresh operation.
4 is a bank structure diagram illustrating a plurality of banks according to the present invention.
5 is a configuration diagram of a counter unit and an address latch included in the refresh counter of the present invention.
FIG. 6 is a detailed configuration diagram of the address latch shown in FIG. 5.
7 is a timing diagram in a refresh operation according to the present invention.

Hereinafter, a bank group refresh control apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

4 shows a bank structure diagram according to an embodiment of the present invention.

As shown, the bank of the present invention is composed of four bank groups BG0, ..., BG3, and each bank group includes a plurality of banks. In addition, a circuit unit for controlling each bank group is provided, wherein the circuit counter includes refresh counters 100, 110, 120, and 130 for controlling refresh operations for each bank group, and one address latch 200 for generating row addresses to be supplied to each circuit unit. ) Is included.

The address latch 200 inputs an external address A <0:14> to generate a row address LA <0:14>. The generated row address is supplied to a circuit unit for each bank group.

Each of the refresh counters 100, 110, 120, and 130 has the same or similar configuration, and includes a counter unit and an address latch 400 shown in FIG.

The counters 310, 320, 330, ... are connected in parallel with counters for generating a RAT <0:14> signal by inputting a refresh command REF. Accordingly, the refresh command REF is input to the first unit 310 to generate an RAT <0> address. The RAT <0> address is input to the second unit 320 to generate an RAT <1> address. In this process, the counter unit sequentially generates the RAT <0:14> address, and the RAT <0:14> address generated by the counter unit is transferred to the address latch 400, so that the RA <0:14: N> signal is output.

The address latch 400 may include a LA <0:14> address transferred through the address latch 200 shown in FIG. 4 in a normal operation process or a RAT <0: transferred through the counter unit in the refresh operation process. 14> are configured to selectively output the address. That is, in the normal operation process, the LA <0:14> is transmitted to the RA <0:14> output terminal by the active command ACT, and in the refresh operation process, the RAT <0:14> is performed by the refresh signal REDF. Deliver the signal to the RA <0> 14> output.

When the refresh signal REFD provided to the address latch 400 is input to any one of a REFA signal for performing a refresh operation on all banks and a REF_BG # signal for performing a refresh operation on a specific bank group, The signal is obtained by delaying the input signal through the delay unit 410.

The detailed configuration of the address latch 400 is shown in FIG. As shown, the address latch 400 includes a transmission gate that opens and closes a passage by an active command ACT, and a transmission gate that opens and closes a passage by a refresh command REFD, and optionally a transmission gate. The signal passing through is configured to be output to the address RA_BG # <0: N> through the latch portion.

Next, an operation process of the bank group refresh control apparatus according to the present invention having the above configuration will be described.

7 illustrates a timing diagram of a refresh operation according to the present invention.

First, the present invention distinguishes and controls the refresh operation process whether the first mode refreshes all banks or the second mode refreshes banks in a specific bank group.

In the first mode of refreshing all the banks, a refresh operation is performed on all banks in all bank groups as in the prior art. At this time, the refresh counters 100, 110, 120, and 130 included in each bank group generate a RAT <0: N> signal according to the REFA signal to control the refresh operation of all banks.

However, in the second mode of refreshing banks in a specific bank group, a corresponding bank group is selected, and a specific bank group refresh command is generated by a combination of the selected bank group and the refresh command.

That is, as shown in Fig. 4, a refresh counter is provided for each bank group. Therefore, in the operation of the second mode, only the bank group in which the bank group refresh command REF_BG # is inputted performs the refresh operation.

At this time, the operation circuits 420 and 430 input the bank group refresh command REF_BG # generate a refresh signal REF, and the refresh signal generates a REFD signal delayed for a predetermined time through the delay circuit 410. The generated signal controls the address latch 400 to output the RAT <0:14> address generated by the counter as a row address. The address thus output sequentially controls the refresh operation of the banks in the bank group.

Meanwhile, as described above, the address latch 200 illustrated in FIG. 4 is in a free state without being involved in the refresh operation process while the refresh operation of the specific bank group is performed.

Therefore, another bank group can perform an active operation, a precharge operation, or a read / write operation as shown in FIG. 7 by using the LA <0:14> address generated by the address latch 200. .

The above-described preferred embodiments of the present invention are disclosed for purposes of illustration, and are configured to control the refresh operation for each bank group, and when the refresh operation for each bank group is controlled, different operations of other bank groups are performed. It can be applied in the case of controlling to enable simultaneous operation. Therefore, those skilled in the art will be able to improve, change, substitute or add other embodiments within the technical spirit and scope of the present invention disclosed in the appended claims.

100 to 130: refresh counter 200: address latch
310, 320, 330: counter unit 400: address latch
410: delay element 420: noah gate
430: inverter

Claims (5)

A plurality of bank groups including a plurality of banks is provided,
A refresh counter configured to separately perform refresh operation control for each bank group and refresh operation control for all banks;
And an address latch configured to generate a row address by inputting an external address independently of the refresh operation.
The method of claim 1,
The refresh counter is a bank group refresh control device, characterized in that configured independently for each bank group.
The method of claim 2,
The refresh counter may include a counter that sequentially generates row addresses by a refresh command;
And an address latch unit controlled by the refresh command to output a row address generated by the counter.
The method of claim 3, wherein
And the address latch unit outputs a row address generated by the counter according to a refresh operation mode signal of all banks and a refresh operation mode signal of a specific bank group.
The method of claim 1,
And the address latch generates a row address for another access operation of another bank group in a refresh operation mode of a specific bank group.
KR1020100051172A 2010-05-31 2010-05-31 Bank group refresh control device KR20110131634A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150052967A (en) * 2013-11-07 2015-05-15 에스케이하이닉스 주식회사 Semiconduct memory device
US9653139B1 (en) 2016-04-01 2017-05-16 SK Hynix Inc. Simultaneous plural wordline within a bank refreshing control device and memory device including the same
US9741422B1 (en) 2016-02-22 2017-08-22 SK Hynix Inc. Device for controlling a refresh operation to a plurality of banks in a semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150052967A (en) * 2013-11-07 2015-05-15 에스케이하이닉스 주식회사 Semiconduct memory device
US9378801B2 (en) 2013-11-07 2016-06-28 SK Hynix Inc. Semiconductor memory device
US9741422B1 (en) 2016-02-22 2017-08-22 SK Hynix Inc. Device for controlling a refresh operation to a plurality of banks in a semiconductor device
US9653139B1 (en) 2016-04-01 2017-05-16 SK Hynix Inc. Simultaneous plural wordline within a bank refreshing control device and memory device including the same

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