CN107818973B - Transistor for increasing signal amplitude range - Google Patents
Transistor for increasing signal amplitude range Download PDFInfo
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- CN107818973B CN107818973B CN201610819368.XA CN201610819368A CN107818973B CN 107818973 B CN107818973 B CN 107818973B CN 201610819368 A CN201610819368 A CN 201610819368A CN 107818973 B CN107818973 B CN 107818973B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
Abstract
the invention discloses a transistor for increasing the signal amplitude range, which comprises a first doped well, a second doped well, a first doped area, a second doped area, a gate layer and at least one compensation capacitor. The first doped well and the second doped well are formed in a structural layer; the first doped region and the second doped region are formed in the first doped well and have a first conductivity type, the second doped well has a second conductivity type, and the first doped region is used for transmitting a signal; the at least one compensation capacitor is used for adjusting the cross voltage of an interface parasitic capacitor between the first doped region and the first doped well, between the first doped well and the second doped well, or between the second doped well and the structural layer.
Description
Technical Field
The present invention relates to a transistor, and more particularly, to a transistor with a compensation capacitor to increase the signal amplitude range.
Background
When a transistor transmits or receives a signal, the amplitude of the signal is spanned on all interface parasitic capacitances between a doped region of a drain (source) electrode of the transistor and a substrate for forming the transistor, wherein the capacitance value of the interface parasitic capacitance corresponding to the substrate in all the interface parasitic capacitances is minimum, and the borne voltage is larger than that of the rest parasitic capacitances in all the interface parasitic capacitances. Since the interface parasitic capacitance corresponding to the substrate has the smallest capacitance value and bears the largest voltage, the parasitic diode corresponding to the substrate is easily turned on, so that the amplitude of the signal is greatly limited. Because the amplitude of the signal is greatly limited, the energy that the signal can carry will also be severely limited. Therefore, how to design a transistor capable of increasing the signal amplitude range becomes an important issue.
disclosure of Invention
In order to overcome the technical problem of limited signal amplitude of the transistor in the prior art, the invention provides a transistor capable of increasing the signal amplitude range.
an embodiment of the present invention provides a transistor for increasing a signal amplitude range. The transistor comprises a first doped well, a second doped well, a first doped region, a second doped region, a gate layer and at least one compensation capacitor. The first doped well is formed in a structural layer; the second doped well is formed in the structural layer, and the second doped well is formed between the first doped well and the structural layer; the first doped region is formed in the first doped well and used for transmitting a signal; the second doped region is formed in the first doped well, wherein the first doped region and the second doped region have a first conductivity type, and the second doped well has a second conductivity type; the gate layer is used for forming a channel between the first doped region and the second doped region; the at least one compensation capacitor is electrically connected between the first doped region and the first doped well, or between the first doped well and the second doped well, or between the second doped well and a first reference potential; a first interface parasitic capacitor is arranged between the first doping area and the first doping well, a second interface parasitic capacitor is arranged between the first doping well and the second doping well, and a third interface parasitic capacitor is arranged between the second doping well and the structural layer; and the at least one compensation capacitor is used for adjusting the voltage across the first interface parasitic capacitor, the second interface parasitic capacitor or the third interface parasitic capacitor.
compared with the prior art, the technical scheme provided by the invention is that when the transistor transmits signals, different preset voltages are respectively applied to different doped wells to increase the reverse bias voltage across each interface parasitic diode, or at least one compensation capacitor is used for compensating at least one interface parasitic capacitor, so that the difference of the cross voltage among at least one interface parasitic capacitor is small, and compared with the prior art, the signal amplitude range can be increased.
Drawings
The advantages and spirit of the present invention can be further understood by the following detailed description of the invention and the accompanying drawings.
FIG. 1 is a schematic diagram of a transistor for increasing the signal amplitude range according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating a circuit configuration corresponding to FIG. 1;
FIG. 3 is a graph illustrating a first voltage amplitude equal to a difference between a first threshold and a first reverse bias voltage, a second voltage amplitude equal to a difference between a second threshold and a second reverse bias voltage, and a third voltage amplitude equal to a difference between a third threshold and a third reverse bias voltage;
FIG. 4 is a schematic diagram of a transistor for increasing the signal amplitude range according to a second embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating a transistor including only a first compensation capacitor;
FIG. 6 is a schematic diagram illustrating a transistor including only a second compensation capacitor;
FIG. 7 is a schematic diagram illustrating a transistor including only a third compensation capacitor;
FIG. 8 is a schematic diagram illustrating a circuit configuration corresponding to FIG. 4;
FIG. 9 is a schematic diagram of a transistor for increasing the signal amplitude range according to a third embodiment of the present invention;
Fig. 10 is a schematic diagram illustrating that the transistor includes only the fourth compensation capacitance.
[ main graphic description ]
100. 400, 600 transistor
102 first doping well
104 second doped well
106 structural layer
108 first doped region
110 second doped region
112 gate layer
113 channel
114 first lightly doped region
116 second lightly doped region
118 third doped region
120 first interface parasitic capacitance
121 first parasitic diode
122 second interface parasitic capacitance
123 second parasitic diode
124 third interface parasitic capacitance
125 third parasitic diode
126 first compensation capacitor
128 second compensation capacitor
130 third compensation capacitance
132 third doped well
134 fourth compensation capacitor
136 fourth interface parasitic capacitance
137 fourth parasitic diode
200 substrate
GND first reference potential
SI signal
VG, VS, VD voltage
VNEG first voltage
Second voltage of VPEG
VP Low reference potential
VN high reference potential
VSW1 first Voltage amplitude
VSW2 second Voltage amplitude
VSW3 third Voltage amplitude
VTH1 first threshold
VTH2 second threshold value
VTH3 third critical value
VR1 first reverse bias
VR2 second reverse bias
VR3 third reverse bias
VFREF second reference potential
Detailed Description
Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, the present invention should be understood not to be limited to such an embodiment described below, and the technical idea of the present invention may be implemented in combination with other known techniques or other techniques having the same functions as those of the known techniques.
Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
Referring to fig. 1, fig. 1 is a diagram illustrating a transistor 100 for increasing a signal amplitude range according to a first embodiment of the invention. As shown in fig. 1, the transistor 100 includes a first doped well 102, a second doped well 104, a structural layer 106, a first doped region 108, a second doped region 110, a gate layer 112, a first lightly doped region 114, a second lightly doped region 116, and a third doped region 118, wherein the structural layer 106 may include a substrate (substrate) for receiving a first reference potential (e.g., ground GND). In addition, the first doped region 108 may be a source of the transistor 100 and the second doped region 110 may be a drain of the transistor 100, or the first doped region 108 may be a drain of the transistor 100 and the second doped region 110 may be a source of the transistor 100. The first doped well 102 and the second doped well 104 are formed in the structural layer 106, and the second doped well 104 is formed between the first doped well 102 and the structural layer 106, for example, the first doped well 102 is formed in the second doped well 104; the first doped region 108, the second doped region 110, the first lightly doped region 114 and the second lightly doped region 116 are formed in the first doped well 102, wherein the first doped region 108 is used for transmitting a signal SI. A first lightly doped region 114 is formed at a side of the first doped region 108 close to the gate layer 112, and a second lightly doped region 116 is formed at a side of the second doped region 110 close to the gate layer 112. The third doped region 118 is formed in the structural layer 106, surrounds the first doped region 108 and the second doped region 110, and is electrically connected to the second doped well 104, wherein the first doped region 108, the second doped region 110, the first lightly doped region 114, the second lightly doped region 116, the second doped well 104, and the third doped region 118 have a first conductivity type, and the first doped well 102 and the structural layer 106 have a second conductivity type. For example, the first doped region 108, the second doped region 110, the first lightly doped region 114, the second lightly doped region 116, the second doped well 104, and the third doped region 118 have an N-type conductivity, and the first doped well 102 and the structural layer 106 have a P-type conductivity. However, the invention is not limited thereto, and the above-mentioned N-type conductivity type and P-type conductivity type may be interchanged. In addition, the doping concentration of the first lightly doped region 114 and the second lightly doped region 116 is lower than the doping concentration of the first doped region 108 and the second doped region 110, wherein the first lightly doped region 114 and the second lightly doped region 116 are used to prevent a short channel effect (short channel effect) between the first doped region 108 and the second doped region 110.
As shown in fig. 1, a first interface parasitic capacitor 120 and a first parasitic diode 121 are disposed between the first doped region 108 and the first doped well 102, a second interface parasitic capacitor 122 and a second parasitic diode 123 are disposed between the first doped well 102 and the second doped well 104, and a third interface parasitic capacitor 124 and a third parasitic diode 125 are disposed between the second doped well 104 and the structural layer 106, wherein the transistor 100 is, for example, a cmos transistor, and the capacitance values of the first interface parasitic capacitor 120, the second interface parasitic capacitor 122 and the third interface parasitic capacitor 124 are gradually reduced. In addition, the first capacitance of the first interface parasitic capacitor 120 and the first threshold VTH1 of the first parasitic diode 121 are determined by the cross-sectional area and doping concentration of the first doped region 108 and the cross-sectional area and doping concentration of the first doped well 102, the second capacitance of the second interface parasitic capacitor 122 and the second threshold VTH2 of the second parasitic diode 123 are determined by the cross-sectional area and doping concentration of the first doped well 102 and the cross-sectional area and doping concentration of the second doped well 104, and the third capacitance of the third interface parasitic capacitor 124 and the third threshold VTH3 of the third parasitic diode 125 are determined by the cross-sectional area and doping concentration of the second doped well 104 and the cross-sectional area and doping concentration of the structural layer 106.
When the first doped region 108 transmits the signal SI, the sum of the voltages across the first interface parasitic capacitor 120, the second interface parasitic capacitor 122, and the third interface parasitic capacitor 124 is equal to the amplitude of the signal SI. Because the capacitance values of the first interface parasitic capacitor 120, the second interface parasitic capacitor 122 and the third interface parasitic capacitor 124 are gradually decreased, and the voltage across one of the first interface parasitic capacitor 120, the second interface parasitic capacitor 122 and the third interface parasitic capacitor 124 is in an inverse relationship with the capacitance value of the interface parasitic capacitor, the voltage across the third interface parasitic capacitor 124 is greater than the voltage across the first interface parasitic capacitor 120 and the second interface parasitic capacitor 122. Therefore, in the embodiment of fig. 1, when the first doped region 108 transmits the signal SI, the gate layer 112 can receive an appropriate voltage VG to form a channel 113 between the first doped region 108 and the second doped region 110 to turn on the transistor 100, the first doped well 102 receives a first voltage VNEG, and the second doped well 104 receives a second voltage VPEG through the third doped region 118, wherein the voltage VG is a positive voltage, the first voltage VNEG is a negative voltage, the second voltage VPEG is a positive voltage, and the voltages VS and VD of the first doped region 108 and the second doped region 110 are respectively about 1/2 VG. In addition, fig. 2 may be referred to as a circuit configuration diagram corresponding to fig. 1. As shown in fig. 2, the voltage VS of the first doping region 108 and the first voltage VNEG received by the first doping well 102 may cause a first reverse bias voltage VR1(VR1 ═ VNEG-VS) to cross the first parasitic diode 121, the first voltage VNEG received by the first doping well 102 and the second voltage VPEG received by the second doping well 104 may cause a second reverse bias voltage VR2(VR2 ═ VNEG-VPEG) to cross the second parasitic diode 123, and the second voltage VPEG received by the second doping well 104 and the first reference potential (e.g., ground GND) received by the structural layer 106 may cause a third reverse bias voltage VR3(VR3 ═ VGND-VPEG) to cross the third parasitic diode 125, where VGND is a potential representing ground. Therefore, as shown in fig. 3, since the first reverse bias voltage VR1 crosses the first parasitic diode 121, the first parasitic diode 121 can bear a first voltage amplitude VSW1 equal to the difference between the first threshold VTH1 and the first reverse bias voltage VR 1; since the second reverse bias voltage VR2 crosses the second parasitic diode 123, the second parasitic diode 123 can sustain a second voltage amplitude VSW2 equal to the difference between the second threshold VTH2 and the second reverse bias voltage VR 2; since the third reverse bias voltage VR3 crosses the third parasitic diode 125, the third parasitic diode 125 can sustain a third voltage swing VSW3 equal to the difference between the third threshold VTH3 and the third reverse bias voltage VR 3. Therefore, as shown in fig. 3, since the first reverse bias voltage VR1, the second reverse bias voltage VR2, and the third reverse bias voltage VR3 can respectively increase the first voltage amplitude VSW1, the second voltage amplitude VSW2, and the third voltage amplitude VSW3, when the first doped region 108 transmits the signal SI, the first voltage VNEG received by the first doped well 102 and the second voltage VPEG received by the second doped well 104 can effectively prevent the first parasitic diode 121, the second parasitic diode 123, and the third parasitic diode 125 from being turned on, i.e., the transistor 100 can increase the amplitude range of the signal SI.
Referring to fig. 4, fig. 4 is a diagram illustrating a transistor 400 for increasing a signal amplitude range according to a second embodiment of the invention. As shown in fig. 4, the difference between the transistor 400 and the transistor 100 is that the transistor 400 further has a first compensation capacitor 126, a second compensation capacitor 128 and a third compensation capacitor 130, the first doped well 102 is electrically connected to a low reference potential VP, and the second doped well 104 is electrically connected to a high reference potential VN, wherein the first compensation capacitor 126 is electrically connected between the first doped region 108 and the first doped well 102 for compensating the first interface parasitic capacitor 120; the second compensation capacitor 128 is electrically connected between the first doped well 102 and the second doped well 104 for compensating the second interface parasitic capacitor 122; the third compensation capacitor 130 is electrically connected between the second doped well 104 and the first reference potential (e.g., ground GND) for compensating the third interface parasitic capacitor 124; the first compensation capacitor 126, the second compensation capacitor 128, and the third compensation capacitor 130 are metal-insulator-metal (MIM) capacitors. In addition, the capacitance values of the first compensation capacitor 126, the second compensation capacitor 128 and the third compensation capacitor 130 are at least determined by the capacitance values of the first interface parasitic capacitor 120, the second interface parasitic capacitor 122 and the third interface parasitic capacitor 124. That is, the capacitance of the first compensation capacitor 126 can be referred to formula (1):
C j is a capacitance of the first compensation capacitor 126, ∈ s is a dielectric constant, N A is an acceptor concentration of the first doped region 108 and the first doped well 102, N D is a donor concentration of the first doped region 108 and the first doped well 102, V bi is a built-in potential (build-in potential), and V R is an external voltage.
In another embodiment, the amplitude of the signal SI may be determined additionally. Since the voltage across a single interface parasitic capacitor among the first interface parasitic capacitor 120, the second interface parasitic capacitor 122, and the third interface parasitic capacitor 124 is in an inverse relationship with the capacitance of the interface parasitic capacitor, the transistor 400 can compensate the first interface parasitic capacitor 120 with the first compensation capacitor 126, compensate the second interface parasitic capacitor 122 with the second compensation capacitor 128, and compensate the third interface parasitic capacitor 124 with the third compensation capacitor 130, so as to reduce the difference between the voltage across the first interface parasitic capacitor 120, the voltage across the second interface parasitic capacitor 122, and the voltage across the third interface parasitic capacitor 124. That is, when the first doped region 108 transmits the signal SI, the transistor 400 can compensate the corresponding first, second and third interface parasitic capacitors 120, 122 and 124 by using the first, second and third compensation capacitors 126, 128 and 130, and simultaneously adjust the voltages respectively allocated to the first, second and third interface parasitic capacitors 120, 122 and 124 by the signal SI, and reduce the difference between the voltages allocated to the interface parasitic capacitors, so as to prevent the first, second and third parasitic diodes 121, 123 and 125 from being turned on. Therefore, the transistor 100 can increase the amplitude range of the signal SI by using the first compensation capacitor 126, the second compensation capacitor 128 and the third compensation capacitor 130. In addition, the present invention is not limited to the transistor 400 having the first compensation capacitor 126, the second compensation capacitor 128 and the third compensation capacitor 130 at the same time, that is, the transistor 400 can adjust the number of the compensation capacitors according to the voltages across the first interface parasitic capacitor 120, the second interface parasitic capacitor 122 and the third interface parasitic capacitor 124, so in another embodiment of the present invention, the transistor 400 can include only one of the first compensation capacitor 126, the second compensation capacitor 128 and the third compensation capacitor 130, or only any two of them, so as to compensate the corresponding interface parasitic capacitors, and adjust the voltages across the first interface parasitic capacitor 120, the second interface parasitic capacitor 122 and the third interface parasitic capacitor 124 at the same time, and reduce the difference of the voltages distributed among the interface parasitic capacitors. Other embodiments of the present invention are illustrated in fig. 5-7, wherein fig. 5 illustrates that the transistor 400 includes only the first compensation capacitor 126, fig. 6 illustrates that the transistor 400 includes only the second compensation capacitor 128, and fig. 7 illustrates that the transistor 400 includes only the third compensation capacitor 130. In addition, fig. 8 may be referred to as a circuit configuration diagram corresponding to fig. 4.
in addition, in another embodiment of the present invention, at least one of the first compensation capacitor 126, the second compensation capacitor 128 and the third compensation capacitor 130 is configured to make a sum of a capacitance value of the first interface parasitic capacitor 120 and a capacitance value of the first compensation capacitor 126, a sum of a capacitance value of the second interface parasitic capacitor 122 and a capacitance value of the second compensation capacitor 128, and a sum of a capacitance value of the third interface parasitic capacitor 124 and a capacitance value of the third compensation capacitor 130 equal to each other. For example, if the capacitance value of the first interface parasitic capacitor 120 is greater than the capacitance value of the second interface parasitic capacitor 122, and the capacitance value of the second interface parasitic capacitor 122 is greater than the capacitance value of the third interface parasitic capacitor 124, the first interface parasitic capacitor 120 is not compensated, the sum of the capacitance value of the second interface parasitic capacitor 122 and the capacitance value of the second compensation capacitor 128 is equal to the capacitance value of the first interface parasitic capacitor 120, and the sum of the capacitance value of the third interface parasitic capacitor 124 and the capacitance value of the third compensation capacitor 130 is equal to the capacitance value of the first interface parasitic capacitor 120. That is, when the capacitance of the first interface parasitic capacitor 120 is greater than the capacitance of the second interface parasitic capacitor 122, and the capacitance of the second interface parasitic capacitor 122 is greater than the capacitance of the third interface parasitic capacitor 124, the capacitance of the second compensation capacitor 128 compensates the capacitance of the second interface parasitic capacitor 122, and the capacitance of the third compensation capacitor 130 compensates the capacitance of the third interface parasitic capacitor 124 to be equal to the capacitance of the first interface parasitic capacitor 120.
In another embodiment of the present invention, an nth interface parasitic capacitor of one of the first interface parasitic capacitor 120, the second interface parasitic capacitor 122 and the third interface parasitic capacitor 124 has a minimum capacitance value, an mth interface parasitic capacitor has a capacitance value (for example, a maximum capacitance value) different from that of the nth interface parasitic capacitor, and a capacitance value of an nth compensation capacitor corresponding to the nth interface parasitic capacitor is a difference between the capacitance value of the mth interface parasitic capacitor and the capacitance value of the nth interface parasitic capacitor. That is, when N is one, the capacitance of the first compensation capacitor 126 is the difference between the capacitance of the mth interface parasitic capacitor and the capacitance of the first interface parasitic capacitor 120; when N is two, the capacitance of the second compensation capacitor 128 is the difference between the capacitance of the mth interface parasitic capacitor and the capacitance of the second interface parasitic capacitor 122; when N is three, the capacitance of the third compensation capacitor 130 is the difference between the capacitance of the mth interface parasitic capacitor and the capacitance of the third interface parasitic capacitor 124. For example, if the third interface parasitic capacitor 124 of one of the first interface parasitic capacitor 120, the second interface parasitic capacitor 122 and the third interface parasitic capacitor 124 has the largest capacitance value X, and the first interface parasitic capacitor 120 has the smallest capacitance value Y, the capacitance value of the first compensation capacitor 126 corresponding to the first interface parasitic capacitor 120 is the difference between the capacitance value X of the third interface parasitic capacitor 124 and the capacitance value Y of the first interface parasitic capacitor 120, which is X-Y. In addition, the nth compensation capacitor is not limited to include only a single capacitor, and may be an nth equivalent compensation capacitor formed by one or more interconnected electronic components, as long as the equivalent capacitance values of the nth compensation capacitor and the nth equivalent compensation capacitor are the same.
Referring to fig. 9, fig. 9 is a diagram illustrating a transistor 600 for increasing a signal amplitude range according to a third embodiment of the invention. As shown in fig. 9, the difference between the transistor 600 and the transistor 400 is that the structural layer 106 of the transistor 600 further includes a third doped well 132 and a substrate 200, and the transistor 600 further has a fourth compensation capacitor 134. As shown in fig. 9, a fourth interface parasitic capacitor 136 and a fourth parasitic diode 137 are disposed between the third doped well 132 and the substrate 200, and the third doped well 132 is disposed between the second doped well 104 and the substrate 200, for example, the second doped well 104 is formed in the third doped well 132, wherein the third doped well 132 has the second conductivity type, a second reference potential VFREF is electrically connected to the third doped well 132, the first reference potential (e.g., ground GND) is electrically connected to the structural layer 106, a fourth compensation capacitor 134 is electrically connected between the third doped well 132 and the first reference potential, and a fourth compensation capacitor 134 is used for compensating the fourth interface parasitic capacitor 136. Since the transistor 600 has the fourth compensation capacitor 134, the capacitance values of the first compensation capacitor 126, the second compensation capacitor 128, the third compensation capacitor 130 and the fourth compensation capacitor 134 are determined at least by the capacitance values of the first interface parasitic capacitor 120, the second interface parasitic capacitor 122, the third interface parasitic capacitor 124 and the fourth interface parasitic capacitor 136, and in another embodiment, may be additionally determined according to the amplitude of the signal SI. That is, when the first doped region 108 transmits the signal SI, the transistor 600 can compensate the corresponding first interface parasitic capacitor 120, second interface parasitic capacitor 122, third interface parasitic capacitor 124 and fourth interface parasitic capacitor 136 by using the first compensation capacitor 126, the second compensation capacitor 128, the third compensation capacitor 130 and the fourth compensation capacitor 134, and simultaneously adjust the voltage steps respectively allocated to the first interface parasitic capacitor 120, the second interface parasitic capacitor 122, the third interface parasitic capacitor 124 and the fourth interface parasitic capacitor 136 by the signal SI, and reduce the voltage step difference allocated to the first interface parasitic capacitor 120, the second interface parasitic capacitor 122, the third interface parasitic capacitor 124 and the fourth interface parasitic capacitor 136, so as to prevent the first parasitic diode 121, the second parasitic diode 123, the third parasitic diode 125 and the fourth parasitic diode 137 from being turned on. In addition, the present invention is not limited to the transistor 600 having the first compensation capacitor 126, the second compensation capacitor 128, the third compensation capacitor 130 and the fourth compensation capacitor 134, that is, the transistor 600 can adjust the number of the compensation capacitors according to the voltages of the first interface parasitic capacitor 120, the second interface parasitic capacitor 122, the third interface parasitic capacitor 124 and the fourth interface parasitic capacitor 136, in another embodiment of the present invention, therefore, the transistor 600 may include only at least one of the first compensation capacitor 126, the second compensation capacitor 128, the third compensation capacitor 130 and the fourth compensation capacitor 134, or only any two, the corresponding interface parasitic capacitances can be compensated, and the voltage across the first interface parasitic capacitance 120, the second interface parasitic capacitance 122, the third interface parasitic capacitance 124, and the fourth interface parasitic capacitance 136 can be adjusted at the same time, and the difference of the voltage across the interface parasitic capacitances distributed among each other can be reduced. In other embodiments of the present invention, as shown in fig. 10, the transistor 600 includes only the fourth compensation capacitor 134.
In addition, in other embodiments of the present invention, the structural layer 106 may further include a fourth doped well and a fifth compensation capacitor, wherein the fourth doped well is formed between the third doped well 132 and the substrate 200, the fourth doped well has a conductivity type different from that of the third doped well 132, a third reference potential is electrically connected to the fourth doped well, a fifth interface parasitic capacitor is formed between the fourth doped well and the substrate 200, and the fifth compensation capacitor is electrically connected between the fourth doped well and the first reference potential for compensating the fifth interface parasitic capacitor.
In addition, in other embodiments of the present invention, the structure layer 106 further includes a plurality of doped wells formed between the third doped well 132 and the substrate 200, wherein a J-th doped well of the plurality of doped wells has a different conductivity type from a (J-1) -th doped well of the plurality of doped wells, a (J-1) -th reference potential is electrically connected to the J-th doped well, a J-th interface parasitic capacitor is disposed between the (J-1) -th doped well and the J-th doped well, a (J +1) -th interface parasitic capacitor is disposed between the J-th doped well and a (J +1) -th doped well of the plurality of doped wells, a corresponding interface parasitic capacitor is disposed between a last doped well of the plurality of doped wells and the substrate 200, and a (J +1) -th compensation capacitor is electrically connected between the J-th doped well and the first reference potential, for compensating the (J +1) th interface parasitic capacitance, wherein J may be a positive integer greater than or equal to four.
Similarly, the nth interface parasitic capacitor of one of the first interface parasitic capacitor 120, the second interface parasitic capacitor 122, the third interface parasitic capacitor 124 and the fourth interface parasitic capacitor 136 has the smallest capacitance value, the mth interface parasitic capacitor has a different capacitance value (for example, the largest capacitance value) from the nth interface parasitic capacitor, and the capacitance value of the nth compensation capacitor corresponding to the nth interface parasitic capacitor is the difference between the capacitance value of the mth interface parasitic capacitor and the capacitance value of the nth interface parasitic capacitor. In addition, the nth compensation capacitor is not limited to include only a single physical capacitor, and may be an nth equivalent compensation capacitor formed by one or more interconnected electronic components, as long as the equivalent capacitance values of the nth compensation capacitor and the nth equivalent compensation capacitor are the same.
In summary, in the present invention, when the transistor transmits a signal, different predetermined voltages are applied to different doped wells to increase the reverse bias voltage across each interface parasitic diode, or at least one compensation capacitor is used to compensate at least one interface parasitic capacitor, so that the difference of the cross voltage between at least one interface parasitic capacitor is not large, so that the signal amplitude range can be increased compared with the prior art.
The terms "first" and "second" as used herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another, unless otherwise specified. Similarly, the appearances of the phrases "a" or "an" in various places herein are not necessarily all referring to the same quantity, but rather to the same quantity, and are intended to cover all technical features not previously described. Similarly, modifiers similar to "about", "approximately" or "approximately" that occur before a numerical term herein typically include the same number, and their specific meaning should be read in conjunction with the context. Similarly, unless a specific number of a claim recitation is intended to cover both the singular and the plural, and embodiments may include a single feature or a plurality of features.
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the claims of the present invention should be covered by the present invention.
Claims (15)
1. A transistor for increasing a signal amplitude range, comprising:
a first doped well formed in a structural layer;
A second doped well formed in the structural layer, wherein the second doped well is formed between the first doped well and the structural layer;
a first doped region formed in the first doped well for transmitting a signal;
A second doped region formed in the first doped well, wherein the first doped region, the second doped region and the second doped well have a first conductivity type, and the first doped well has a second conductivity type;
A gate layer for forming a channel between the first doped region and the second doped region; and
At least one compensation capacitor formed outside the first doped region, the second doped region, the first doped well, the second doped well and the structural layer and electrically connected between the first doped region and the first doped well, or between the first doped well and the second doped well, or between the second doped well and a first reference potential, the first reference potential being electrically connected to the structural layer;
Wherein a first interface parasitic capacitor is arranged between the first doped region and the first doped well, a second interface parasitic capacitor is arranged between the first doped well and the second doped well, and a third interface parasitic capacitor is arranged between the second doped well and the structural layer; and the at least one compensation capacitor is used for adjusting the voltage across the first interface parasitic capacitor, the second interface parasitic capacitor or the third interface parasitic capacitor.
2. the transistor of claim 1, wherein the at least one compensation capacitor is configured to reduce a difference between a voltage across the first interface parasitic capacitor, a voltage across the second interface parasitic capacitor, and a voltage across the third interface parasitic capacitor.
3. The transistor of claim 1, wherein a capacitance of the at least one compensation capacitor is determined by at least a capacitance of the first interface parasitic capacitor, a capacitance of the second interface parasitic capacitor, and a capacitance of the third interface parasitic capacitor.
4. The transistor of claim 1, wherein the capacitance of the first interface parasitic capacitor, the second interface parasitic capacitor, and the third interface parasitic capacitor is gradually decreased, and the voltage across the first interface parasitic capacitor, the second interface parasitic capacitor, and the third interface parasitic capacitor is equal to the amplitude of the signal.
5. The transistor of claim 1, wherein the first doped well receives a first voltage, the second doped well receives a second voltage, and the first voltage and the second voltage are opposite in electrical polarity.
6. The transistor of claim 1, wherein the at least one compensation capacitor is a metal-insulator-metal capacitor.
7. The transistor of claim 1, wherein the at least one compensation capacitor comprises a first compensation capacitor electrically connected between the first doped region and the first doped well for compensating the first interface parasitic capacitance.
8. The transistor of claim 1, wherein the at least one compensation capacitor comprises a second compensation capacitor electrically connected between the first doped well and the second doped well for compensating the second interface parasitic capacitance.
9. The transistor of claim 1, wherein the at least one compensation capacitor comprises a third compensation capacitor electrically connected between the second doped well and the first reference potential for compensating the third interface parasitic capacitance.
10. The transistor of claim 1, wherein the structural layer further comprises a third doped well and a substrate, the third doped well is formed in the substrate, and the third doped well is formed between the second doped well and the substrate, wherein the third doped well has the second conductivity type, a second reference potential is electrically connected to the third doped well, the first reference potential is electrically connected to the structural layer, a fourth interface parasitic capacitor is formed between the third doped well and the substrate, and a capacitance of the at least one compensation capacitor is determined by at least a capacitance of the first interface parasitic capacitor, a capacitance of the second interface parasitic capacitor, a capacitance of the third interface parasitic capacitor, and a capacitance of the fourth interface parasitic capacitor; and the at least one compensation capacitor comprises a fourth compensation capacitor which is electrically connected between the third doped well and the first reference potential and is used for compensating the parasitic capacitor of the fourth interface.
11. The transistor of claim 10, wherein the structural layer further comprises a fourth doped well formed between the third doped well and the substrate, wherein the fourth doped well has a different conductivity type than the third doped well, wherein a third reference potential is electrically connected to the fourth doped well, wherein a fifth interface parasitic capacitor is formed between the fourth doped well and the substrate, and wherein the at least one compensation capacitor comprises a fifth compensation capacitor electrically connected between the fourth doped well and the first reference potential for compensating the fifth interface parasitic capacitor.
12. The transistor of claim 10, wherein the structural layer further comprises a plurality of doped wells formed between the third doped well and the substrate, wherein a J-th doped well of the plurality of doped wells has a different conductivity type than a J-1 th doped well of the plurality of doped wells, and a J-1 th reference potential is electrically connected to the J-th doped well, a J-th interface parasitic capacitor is formed between the J-1 th doped well and the J-th doped well, a J +1 th interface parasitic capacitor is formed between the J-th doped well and a J +1 th doped well of the plurality of doped wells, a corresponding interface parasitic capacitor is formed between a last doped well of the plurality of doped wells and the substrate, and the at least one compensation capacitor comprises a J +1 th compensation capacitor, and the second reference potential is electrically connected between the J-th doped well and the first reference potential and is used for compensating the parasitic capacitance of the J + 1-th interface, wherein J is a positive integer greater than or equal to four.
13. The transistor of claim 1, wherein an Nth interface parasitic capacitor of the first, second and third interface parasitic capacitors has a minimum capacitance, and an Mth interface parasitic capacitor has a capacitance different from the Nth interface parasitic capacitor; wherein
When N is 1, the at least one compensation capacitor includes a first equivalent compensation capacitor electrically connected between the first doped region and the first doped well, and a capacitance of the first equivalent compensation capacitor is a difference between a capacitance of the mth interface parasitic capacitor and a capacitance of the first interface parasitic capacitor;
When N is 2, the at least one compensation capacitor includes a second equivalent compensation capacitor electrically connected between the first doped well and the second doped well, and a capacitance of the second equivalent compensation capacitor is a difference between a capacitance of the mth interface parasitic capacitor and a capacitance of the second interface parasitic capacitor; or
When N is 3, the at least one compensation capacitor includes a third equivalent compensation capacitor electrically connected between the second doped well and the first reference potential, and a capacitance of the third equivalent compensation capacitor is a difference between a capacitance of the mth interface parasitic capacitor and a capacitance of the third interface parasitic capacitor.
14. the transistor for increasing signal amplitude range of claim 1, the transistor for increasing the signal amplitude range further comprises a third doped well formed in a substrate and between the second doped well and the substrate, wherein the third doped well has the second conductivity type, and a second reference potential is electrically connected to the third doped well, the first reference potential is electrically connected to the structural layer, a fourth interface parasitic capacitance is arranged between the third doped well and the structural layer, wherein an Nth interface parasitic capacitor among the first interface parasitic capacitor, the second interface parasitic capacitor, the third interface parasitic capacitor and the fourth interface parasitic capacitor has a minimum capacitance value, and an Mth interface parasitic capacitance has a capacitance value different from the Nth interface parasitic capacitance; wherein
When N is 1, the at least one compensation capacitor includes a first equivalent compensation capacitor electrically connected between the first doped region and the first doped well, and a capacitance of the first equivalent compensation capacitor is a difference between a capacitance of the mth interface parasitic capacitor and a capacitance of the first interface parasitic capacitor;
When N is 2, the at least one compensation capacitor includes a second equivalent compensation capacitor electrically connected between the first doped well and the second doped well, and a capacitance of the second equivalent compensation capacitor is a difference between a capacitance of the mth interface parasitic capacitor and a capacitance of the second interface parasitic capacitor;
When N is 3, the at least one compensation capacitor includes a third equivalent compensation capacitor electrically connected between the second doped well and the first reference potential, and a capacitance of the third equivalent compensation capacitor is a difference between a capacitance of the mth interface parasitic capacitor and a capacitance of the third interface parasitic capacitor; or
When N is 4, the at least one compensation capacitor includes a fourth equivalent compensation capacitor electrically connected between the third doped well and the second reference potential, and a capacitance of the fourth equivalent compensation capacitor is a difference between a capacitance of the mth interface parasitic capacitor and a capacitance of the fourth interface parasitic capacitor.
15. The transistor of claim 13 or 14, wherein the Mth interface parasitic capacitor has a largest capacitance value among the interface parasitic capacitors.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1707813A (en) * | 2004-06-08 | 2005-12-14 | 赛芬半导体有限公司 | MOS capacitor with reduced parasitic capacitance |
| CN103457585A (en) * | 2012-05-31 | 2013-12-18 | 立积电子股份有限公司 | Rf switch and rf switch system |
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| US7952444B2 (en) * | 2006-08-08 | 2011-05-31 | Agency For Science, Technology And Research | CMOS power oscillator with frequency modulation |
| WO2008036047A1 (en) * | 2006-09-21 | 2008-03-27 | Nanyang Technological University | Triple well transmit-receive switch transistor |
| US20110298432A1 (en) * | 2010-06-07 | 2011-12-08 | Skyworks Solutions, Inc | Apparatus and method for variable voltage function |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1707813A (en) * | 2004-06-08 | 2005-12-14 | 赛芬半导体有限公司 | MOS capacitor with reduced parasitic capacitance |
| CN103457585A (en) * | 2012-05-31 | 2013-12-18 | 立积电子股份有限公司 | Rf switch and rf switch system |
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