CN107818973B - A transistor for increasing signal amplitude range - Google Patents

Abstract

the invention discloses a transistor for increasing the signal amplitude range, which comprises a first doped well, a second doped well, a first doped area, a second doped area, a gate layer and at least one compensation capacitor. The first doped well and the second doped well are formed in a structural layer; the first doped region and the second doped region are formed in the first doped well and have a first conductivity type, the second doped well has a second conductivity type, and the first doped region is used for transmitting a signal; the at least one compensation capacitor is used for adjusting the cross voltage of an interface parasitic capacitor between the first doped region and the first doped well, between the first doped well and the second doped well, or between the second doped well and the structural layer.

Description

A transistor for increasing signal amplitude range

technical field

The invention relates to a transistor, in particular to a transistor which uses a compensation capacitance to increase the range of signal amplitude.

Background technique

When a transistor transmits or receives a signal, the amplitude of the signal will straddle all interface parasitic capacitances between the doped region of the drain (source) of the transistor and the substrate on which the transistor is formed, wherein all interface parasitic Among the capacitors, the capacitance value corresponding to the interface parasitic capacitance of the substrate is the smallest and the cross-voltage withstood will be greater than the cross-voltage borne by the other parasitic capacitances of all the interface parasitic capacitances. Since the parasitic capacitance of the interface corresponding to the substrate has the smallest capacitance and bears the largest cross-voltage, the parasitic diode corresponding to the substrate is easily turned on, which greatly limits the amplitude of the signal. Since the amplitude of the signal is greatly limited, the amount of energy the signal can carry will also be severely limited. Therefore, how to design a transistor that can increase the signal amplitude range will become an important issue.

Contents of the invention

In order to overcome the technical problem of limited signal amplitude of the transistor in the prior art, the present invention provides a transistor capable of increasing the signal amplitude range.

An embodiment of the present invention provides a transistor for increasing signal amplitude range. The transistor includes a first doped well, a second doped well, a first doped region, a second doped region, a gate layer and at least one compensation capacitor. The first doping well is formed in a structural layer; the second doping well is formed in the structural layer, and the second doping well is formed between the first doping well and the structural layer; the first doping well is formed in the structural layer; A doped region is formed in the first doped well for transmitting a signal; the second doped region is formed in the first doped well, wherein the first doped region and the second doped region have a The first conductivity type, and the second doped well has a second conductivity type; the gate layer is used to form a channel between the first doped region and the second doped region; the at least one The compensation capacitor is electrically connected between the first doped region and the first doped well, or between the first doped well and the second doped well, or between the second doped well and a first doped well. Between reference potentials; there is a first interface parasitic capacitance between the first doped region and the first doped well, a second interface parasitic capacitance between the first doped well and the second doped well, and There is a third interface parasitic capacitance between the second doped well and the structure layer; and the at least one compensation capacitance is used to adjust the first interface parasitic capacitance, the second interface parasitic capacitance or the third interface parasitic capacitance across pressure.

Compared with the prior art, the technical solution provided by the present invention is to apply different predetermined voltages to different doped wells to increase the reverse bias across the parasitic diodes at each interface when the transistor transmits signals, or to use at least one The compensation capacitor compensates the parasitic capacitance of the at least one interface so that the difference in cross-voltage between the parasitic capacitances of the at least one interface is small, so compared with the prior art, the present invention can increase the signal amplitude range.

Description of drawings

The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings.

FIG. 1 is a schematic diagram illustrating a transistor for increasing the signal amplitude range according to the first embodiment of the present invention;

FIG. 2 is a schematic diagram illustrating a circuit structure diagram corresponding to FIG. 1;

Fig. 3 illustrates that the first voltage amplitude is equal to the difference between the first critical value and the first reverse bias voltage, the second voltage amplitude is equal to the difference between the second critical value and the second reverse bias voltage, and the third voltage amplitude is equal to the third critical value Schematic diagram of the difference with the third reverse bias voltage;

4 is a schematic diagram illustrating a transistor for increasing the signal amplitude range according to the second embodiment of the present invention;

5 is a schematic diagram illustrating that the transistor only includes a first compensation capacitor;

6 is a schematic diagram illustrating that the transistor only includes a second compensation capacitor;

FIG. 7 is a schematic diagram illustrating that the transistor only includes a third compensation capacitor;

FIG. 8 is a schematic diagram illustrating the circuit structure diagram corresponding to FIG. 4;

9 is a schematic diagram illustrating a transistor for increasing the signal amplitude range according to the third embodiment of the present invention;

FIG. 10 is a schematic diagram illustrating that the transistor only includes the fourth compensation capacitor.

【Main icon description】

100, 400, 600 transistors

102 First doping well

104 second doping well

106 Structural layers

108 first doped region

110 second doped region

112 gate layer

113 channels

114 The first lightly doped region

116 Second lightly doped region

118 Third doped region

120 Parasitic capacitance of the first interface

121 First parasitic diode

122 Second interface parasitic capacitance

123 Second parasitic diode

124 Parasitic capacitance of the third interface

125 Third parasitic diode

126 The first compensation capacitor

128 Second compensation capacitor

130 The third compensation capacitor

132 The third doping well

134 The fourth compensation capacitor

136 Parasitic capacitance of the fourth interface

137 Fourth parasitic diode

200 bases

GND first reference potential

SI signal

VG, VS, VD voltage

VNEG first voltage

VPEG second voltage

VP low reference potential

VN High reference potential

VSW1 first voltage amplitude

VSW2 second voltage amplitude

VSW3 third voltage amplitude

VTH1 first critical value

VTH2 second critical value

VTH3 third critical value

VR1 first reverse bias

VR2 Second reverse bias voltage

VR3 Third reverse bias voltage

VFREF Second reference potential

Detailed ways

Specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. However, the present invention should be understood as not limited to such embodiments described below, and the technical idea of the present invention can be implemented in combination with other known technologies or other technologies having the same functions as those known technologies.

Specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Please refer to FIG. 1 . FIG. 1 is a schematic diagram illustrating a transistor 100 for increasing a signal amplitude range according to a first embodiment of the present invention. As shown in Figure 1, the transistor 100 includes a first doped well 102, a second doped well 104, a structural layer 106, a first doped region 108, a second doped region 110, a gate layer 112, a first lightly doped region 114, a second lightly doped region 116 and a third doped region 118, wherein the structural layer 106 may include a substrate for receiving a first reference potential (for example ground terminal GND). In addition, the first doped region 108 can be the source of the transistor 100 and the second doped region 110 can be the drain of the transistor 100 , or the first doped region 108 can be the drain of the transistor 100 and the second doped Region 110 may be the source of transistor 100 . The first doped well 102 and the second doped well 104 are formed in the structural layer 106, and the second doped well 104 is formed between the first doped well 102 and the structural layer 106, for example, the first doped well 102 is formed Within the second doped well 104; the first doped region 108, the second doped region 110, the first lightly doped region 114 and the second lightly doped region 116 are formed in the first doped well 102, wherein The first doped region 108 is used to transmit a signal SI. The first lightly doped region 114 is formed on a side of the first doped region 108 close to the gate layer 112 , and the second lightly doped region 116 is formed on a side of the second doped region 110 close to the gate layer 112 . The third doped region 118 is formed in the structural layer 106, surrounds the first doped region 108 and the second doped region 110, and is electrically connected to the second doped well 104, wherein the first doped region 108, the second doped region The impurity region 110, the first lightly doped region 114, the second lightly doped region 116, the second doped well 104 and the third doped region 118 have a first conductivity type, and the first doped well 102 and the structural layer 106 has a second conductivity type. For example, the first doped region 108, the second doped region 110, the first lightly doped region 114, the second lightly doped region 116, the second doped well 104 and the third doped region 118 have an N-type conductivity type, And the first doped well 102 and the structural layer 106 have a P-type conductivity. However, the present invention is not limited thereto, and the above-mentioned N-type conductivity type and P-type conductivity type can also be interchanged. In addition, the doping concentration of the first lightly doped region 114 and the second lightly doped region 116 is lower than that of the first doped region 108 and the second doped region 110, wherein the first lightly doped region 114 and the second lightly doped region 116 are used to prevent short channel effect between the first doped region 108 and the second doped region 110 .

As shown in Figure 1, there is a first interface parasitic capacitance 120 and a first parasitic diode 121 between the first doped region 108 and the first doped well 102, There is a second interface parasitic capacitance 122 and a second parasitic diode 123, and there is a third interface parasitic capacitance 124 and a third parasitic diode 125 between the second doped well 104 and the structural layer 106, wherein the transistor 100 is, for example, a For the CMOS process transistors, the capacitance values of the first interface parasitic capacitor 120 , the second interface parasitic capacitor 122 and the third interface parasitic capacitor 124 gradually decrease. In addition, the first capacitance value of the first interface parasitic capacitance 120 and the first critical value VTH1 of the first parasitic diode 121 are determined by the cross-sectional area and doping concentration of the first doped region 108 and the cross-sectional area of the first doped well 102 Determined by the doping concentration, the second capacitance value of the second interface parasitic capacitance 122 and the second critical value VTH2 of the second parasitic diode 123 are determined by the cross-sectional area and doping concentration of the first doping well 102 and the second doping well 104 is determined by the cross-sectional area and doping concentration, and the third capacitance value of the third interface parasitic capacitance 124 and the third critical value VTH3 of the third parasitic diode 125 are determined by the cross-sectional area and doping concentration of the second doping well 104 and The cross-sectional area of the structural layer 106 is determined by the doping concentration.

When the first doped region 108 transmits the signal SI, the cross-voltage sum of the first interface parasitic capacitance 120 , the second interface parasitic capacitance 122 , and the third interface parasitic capacitance 124 is equal to the amplitude of the signal SI. Because the capacitance values of the first interface parasitic capacitance 120, the second interface parasitic capacitance 122, and the third interface parasitic capacitance 124 gradually decrease, and the first interface parasitic capacitance 120, the second interface parasitic capacitance 122, and the third interface parasitic capacitance 124 The cross-voltage of an interface parasitic capacitance is inversely related to the capacitance value of the interface parasitic capacitance, so the cross-voltage of the third interface parasitic capacitance 124 will be greater than the cross-voltage of the first interface parasitic capacitance 120 and the second interface parasitic capacitance 122 . Therefore, in the embodiment of FIG. 1, when the first doped region 108 transmits the signal SI, the gate layer 112 can receive an appropriate voltage VG to form a channel 113 in the first doped region 108 and the second doped region. 110 to turn on the transistor 100, the first doped well 102 receives a first voltage VNEG, and the second doped well 104 receives a second voltage VPEG through the third doped region 118, wherein the voltage VG is a positive voltage , the first voltage VNEG is a negative voltage, the second voltage VPEG is a positive voltage, and the voltages VS and VD of the first doped region 108 and the second doped region 110 are about 1/2VG respectively. In addition, reference may be made to FIG. 2 for the circuit structure diagram corresponding to FIG. 1 . As shown in FIG. 2, the voltage VS of the first doped region 108 and the first voltage VNEG received by the first doped well 102 can make a first reverse bias voltage VR1 (VR1=VNEG-VS) across the first parasitic The diode 121, the first voltage VNEG received by the first doped well 102 and the second voltage VPEG received by the second doped well 104 can make a second reverse bias voltage VR2 (VR2=VNEG-VPEG) across the second The parasitic diode 123, and the second voltage VPEG received by the second doped well 104 and the first reference potential (such as the ground terminal GND) received by the structural layer 106 can make a third reverse bias voltage VR3 (VR3=VGND−VPEG ) across the third parasitic diode 125, wherein VGND represents the potential of the ground terminal GND. Therefore, as shown in FIG. 3, since the first reverse bias voltage VR1 is across the first parasitic diode 121, the first voltage amplitude VSW1 that the first parasitic diode 121 can withstand will be equal to the first critical value VTH1 and the first reverse bias voltage The difference of VR1; since the second reverse bias voltage VR2 spans the second parasitic diode 123, the second voltage amplitude VSW2 that the second parasitic diode 123 can withstand will be equal to the difference between the second critical value VTH2 and the second reverse bias voltage VR2; Since the third reverse bias voltage VR3 is across the third parasitic diode 125 , the third voltage amplitude VSW3 that the third parasitic diode 125 can bear is equal to the difference between the third threshold VTH3 and the third reverse bias voltage VR3 . Therefore, as shown in FIG. 3, since the first reverse bias voltage VR1, the second reverse bias voltage VR2 and the third reverse bias voltage VR3 can respectively increase the first voltage amplitude VSW1, the second voltage amplitude VSW2 and the third voltage amplitude VSW3, Therefore, when the first doped region 108 transmits the signal SI, the first voltage VNEG received by the first doped well 102 and the second voltage VPEG received by the second doped well 104 can effectively prevent the first parasitic diode 121, the second The second parasitic diode 123 and the third parasitic diode 125 are turned on, that is, the transistor 100 can increase the amplitude range of the signal SI.

Please refer to FIG. 4 . FIG. 4 is a schematic diagram illustrating a transistor 400 for increasing a signal amplitude range according to a second embodiment of the present invention. As shown in FIG. 4, the difference between the transistor 400 and the transistor 100 is that the transistor 400 has a first compensation capacitor 126, a second compensation capacitor 128 and a third compensation capacitor 130, and the first doped well 102 is electrically connected to a The low reference potential VP, and the second doped well 104 are electrically connected to a high reference potential VN, wherein the first compensation capacitor 126 is electrically connected between the first doped region 108 and the first doped well 102 for Compensate the parasitic capacitance 120 of the first interface; the second compensation capacitor 128 is electrically connected between the first doped well 102 and the second doped well 104 for compensating the parasitic capacitance 122 of the second interface; the third compensation capacitor 130 is electrically connected Connected between the second doped well 104 and the first reference potential (such as the ground terminal GND), used to compensate the third interface parasitic capacitance 124; the first compensation capacitor 126, the second compensation capacitor 128 and the third compensation capacitor 130 are Metal-insulator-metal (metal-insulator-metal, MIM) capacitors. In addition, the capacitance value of the first compensation capacitor 126, the capacitance value of the second compensation capacitor 128, and the capacitance value of the third compensation capacitor 130 are at least the capacitance value of the first interface parasitic capacitance 120, the capacitance value of the second interface parasitic capacitance 122 and the capacitance value of the parasitic capacitance 124 of the third interface. That is to say, the capacitance value of the first compensation capacitor 126 can refer to formula (1):

C _j is the capacitance value of the first compensation capacitor 126, ε _s is the dielectric constant, N _A is the acceptor concentration of the first doped region 108 and the first doped well 102, N _D is the first doped region 108 and The donor concentration of the first doped well 102, V _bi is the built-in potential, and _VR is the external voltage. In addition, the capacitance values of the second compensation capacitor 128 and the third compensation capacitor 130 can refer to formula (1), which will not be repeated here.

In another embodiment, it can be additionally determined according to the amplitude of the signal SI. Because the cross-voltage of a single interface parasitic capacitance in the first interface parasitic capacitance 120, the second interface parasitic capacitance 122, and the third interface parasitic capacitance 124 is respectively inversely related to the capacitance value of the interface parasitic capacitance, the transistor 400 can be used The first compensation capacitor 126 compensates the parasitic capacitance 120 of the first interface, the second compensation capacitor 128 compensates the parasitic capacitance 122 of the second interface, and the third compensation capacitor 130 compensates the parasitic capacitance 124 of the third interface, so as to reduce the cross voltage of the parasitic capacitance 120 of the first interface , the difference between the cross voltage of the second interface parasitic capacitance 122 and the cross voltage of the third interface parasitic capacitance 124 . That is, when the first doped region 108 transmits the signal SI, the transistor 400 can use the first compensation capacitor 126 , the second compensation capacitor 128 and the third compensation capacitor 130 to compensate the corresponding first interface parasitic capacitance 120 and the second interface parasitic capacitance 122 and the third interface parasitic capacitance 124, and at the same time adjust the cross voltages assigned to the first interface parasitic capacitance 120, the second interface parasitic capacitance 122 and the third interface parasitic capacitance 124 due to the signal SI, and reduce the interaction between these interface parasitic capacitances To prevent the first parasitic diode 121 , the second parasitic diode 123 and the third parasitic diode 125 from being turned on. Therefore, the transistor 100 can utilize the first compensation capacitor 126 , the second compensation capacitor 128 and the third compensation capacitor 130 to increase the amplitude range of the signal SI. In addition, the present invention is not limited to the need for the transistor 400 to have the first compensation capacitor 126, the second compensation capacitor 128, and the third compensation capacitor 130 at the same time, that is, the transistor 400 can 122. The number of compensation capacitors is adjusted by the cross-voltage of the third interface parasitic capacitor 124, so in another embodiment of the present invention, the transistor 400 may only include the first compensation capacitor 126, the second compensation capacitor 128, and the third compensation capacitor At least one of 130, or only any two of them, can compensate the corresponding interface parasitic capacitance, and at the same time adjust the cross voltage of the first interface parasitic capacitance 120, the second interface parasitic capacitance 122 and the third interface parasitic capacitance 124 , and reduce the difference in the cross-voltage assigned to each other by these interface parasitic capacitances. Other embodiments of the present invention are shown in Figures 5-7, wherein Figure 5 illustrates that the transistor 400 only includes the first compensation capacitor 126, Figure 6 illustrates that the transistor 400 only includes the second compensation capacitor 128, and Figure 7 illustrates that the transistor 400 only includes A third compensation capacitor 130 is included. In addition, reference may be made to FIG. 8 for the circuit structure diagram corresponding to FIG. 4 .

In addition, in another embodiment of the present invention, at least one of the first compensation capacitor 126, the second compensation capacitor 128, and the third compensation capacitor 130 is used to make the capacitance value of the first interface parasitic capacitor 120 the same as that of the first interface parasitic capacitor 120. The sum of the capacitance value of the compensation capacitor 126, the sum of the capacitance value of the second interface parasitic capacitor 122 and the capacitance value of the second compensation capacitor 128, and the capacitance value of the third interface parasitic capacitor 124 and the capacitance value of the third compensation capacitor 130 , at least two of which are equal to each other. For example, if the capacitance value of the parasitic capacitance 120 of the first interface is greater than the capacitance value of the parasitic capacitance 122 of the second interface, and the capacitance value of the parasitic capacitance 122 of the second interface is greater than the capacitance value of the parasitic capacitance 124 of the third interface, then the first interface The parasitic capacitance 120 does not compensate, and the sum of the capacitance value of the second interface parasitic capacitance 122 and the capacitance value of the second compensation capacitance 128 is equal to the capacitance value of the first interface parasitic capacitance 120, and the capacitance value of the third interface parasitic capacitance 124 and the third The sum of the capacitance values of the compensation capacitors 130 is equal to the capacitance value of the parasitic capacitance 120 of the first interface. That is to say, when the capacitance value of the parasitic capacitance 120 of the first interface is greater than the capacitance value of the parasitic capacitance 122 of the second interface, and the capacitance value of the parasitic capacitance 122 of the second interface is greater than the capacitance value of the parasitic capacitance 124 of the third interface, the second compensation capacitance The capacitance value of 128 compensates the capacitance value of the second interface parasitic capacitance 122 and the third compensation capacitor 130 compensates the capacitance value of the third interface parasitic capacitance 124 to be equal to the capacitance value of the first interface parasitic capacitance 120 .

In another embodiment of the present invention, the Nth interface parasitic capacitance of one of the first interface parasitic capacitance 120, the second interface parasitic capacitance 122, and the third interface parasitic capacitance 124 has the smallest capacitance value, and the Mth interface parasitic capacitance has the smallest capacitance value. The interface parasitic capacitance has a capacitance value different from the Nth interface parasitic capacitance (for example, the largest capacitance value), then the capacitance value of the Nth compensation capacitor corresponding to the Nth interface parasitic capacitance is equal to the capacitance value of the Mth interface parasitic capacitance The capacitance difference of the parasitic capacitance of the Nth interface. That is to say, when N is one, the capacitance value of the first compensation capacitor 126 is the difference between the capacitance value of the Mth interface parasitic capacitance and the capacitance value of the first interface parasitic capacitance 120; when N is two, the capacitance value of the second compensation capacitor 128 The capacitance value is the difference between the capacitance value of the Mth interface parasitic capacitance and the capacitance value of the second interface parasitic capacitance 122; when N is three, the capacitance value of the third compensation capacitor 130 is the capacitance value of the Mth interface parasitic capacitance and the third The difference in the capacitance value of the interface parasitic capacitance 124 . For example, if the third interface parasitic capacitance 124 in one of the first interface parasitic capacitance 120, the second interface parasitic capacitance 122 and the third interface parasitic capacitance 124 has the largest capacitance value X, the first interface parasitic capacitance 120 has the smallest capacitance value Y, then the capacitance value of the first compensation capacitor 126 corresponding to the first interface parasitic capacitance 120 is the difference between the capacitance value X of the third interface parasitic capacitance 124 and the capacitance value Y of the first interface parasitic capacitance 120 =X-Y. In addition, the Nth compensation capacitor is not limited to include only a single capacitor, and can also be an Nth equivalent compensation capacitor formed by one or more interconnected electronic components, as long as the Nth compensation capacitor is equal to the Nth equivalent compensation capacitor The effective capacitor value is the same.

Please refer to FIG. 9 . FIG. 9 is a schematic diagram illustrating a transistor 600 for increasing the signal amplitude range according to the third embodiment of the present invention. As shown in FIG. 9 , the difference between the transistor 600 and the transistor 400 is that the structural layer 106 of the transistor 600 further includes a third doped well 132 and a substrate 200 , and the transistor 600 further has a fourth compensation capacitor 134 . As shown in Figure 9, there is a fourth interface parasitic capacitance 136 and a fourth parasitic diode 137 between the third doped well 132 and the substrate 200, and the third doped well 132 is between the second doped well 104 and the substrate Between 200, for example, the second doped well 104 is formed in the third doped well 132, wherein the third doped well 132 has the second conductivity type, and a second reference potential VFREF is electrically connected to the third doped well 132. Well 132, the first reference potential (such as the ground terminal GND) is electrically connected to the structural layer 106, the fourth compensation capacitor 134 is electrically connected between the third doped well 132 and the first reference potential, and the fourth compensation The capacitor 134 is used to compensate the parasitic capacitance 136 of the fourth interface. Because the transistor 600 has the fourth compensation capacitor 134, the capacitance value of the first compensation capacitor 126, the capacitance value of the second compensation capacitor 128, the capacitance value of the third compensation capacitor 130 and the capacitance value of the fourth compensation capacitor 134 are at least determined by the first compensation capacitor 134. The capacitance value of the parasitic capacitance 120 of the first interface, the capacitance value of the parasitic capacitance 122 of the second interface, the capacitance value of the parasitic capacitance 124 of the third interface and the capacitance value of the parasitic capacitance 136 of the fourth interface are determined, and in another embodiment, also It can be additionally determined according to the amplitude of the signal SI. That is, when the first doped region 108 transmits the signal SI, the transistor 600 can use the first compensation capacitor 126 , the second compensation capacitor 128 , the third compensation capacitor 130 and the fourth compensation capacitor 134 to compensate the corresponding parasitic capacitance 120 of the first interface. , the second interface parasitic capacitance 122, the third interface parasitic capacitance 124, and the fourth interface parasitic capacitance 136, while simultaneously adjusting the first interface parasitic capacitance 120, the second interface parasitic capacitance 122, the third interface parasitic capacitance 124, and the fourth interface parasitic capacitance Capacitor 136 is assigned to the cross-voltage due to the signal SI, and reduces the difference in the cross-voltage distributed between these interface parasitic capacitances, so as to prevent the first parasitic diode 121, the second parasitic diode 123, the third parasitic diode 125 and The fourth parasitic diode 137 is turned on. In addition, the present invention is not limited to the need for the transistor 600 to have the first compensation capacitor 126, the second compensation capacitor 128, the third compensation capacitor 130, and the fourth compensation capacitor 134, that is, the transistor 600 can , the second interface parasitic capacitance 122, the third interface parasitic capacitance 124 and the fourth interface parasitic capacitance 136 to adjust the number of compensation capacitors, so in another embodiment of the present invention, the transistor 600 may only include the first compensation At least one of the capacitor 126, the second compensation capacitor 128, the third compensation capacitor 130, and the fourth compensation capacitor 134, or only any two of them, can compensate the corresponding interface parasitic capacitance, while adjusting the first interface parasitic capacitance. The capacitor 120 , the second interface parasitic capacitance 122 , the third interface parasitic capacitance 124 and the fourth interface parasitic capacitance 136 , and reduce the difference of the cross voltage allocated among these interface parasitic capacitances. Other embodiments of the present invention are shown in FIG. 10 , where the transistor 600 only includes the fourth compensation capacitor 134 .

Besides, in other embodiments of the present invention, the structural layer 106 may further include a fourth doped well and a fifth compensation capacitor, wherein the fourth doped well is formed between the third doped well 132 and the third doped well 132 Between the substrate 200, the fourth doped well has a conductivity type different from that of the third doped well 132, a third reference potential is electrically connected to the fourth doped well, and the fourth doped well is connected to the substrate 200. There is a fifth interface parasitic capacitance between them, and a fifth compensation capacitance is electrically connected between the fourth doped well and the first reference potential for compensating the fifth interface parasitic capacitance.

In addition, in other embodiments of the present invention, the structural layer 106 further includes a plurality of doping wells, and the plurality of doping wells are formed between the third doping well 132 and the substrate 200, wherein the doping wells in the plurality of doping wells are The J-th doped well has a conductivity type different from that of the (J-1)-th doped well of the plurality of doped wells, and a (J-1)-th reference potential is electrically connected to the J-th doped well, and the J-th doped well is electrically connected to the J-th doped well. There is a J-th interface parasitic capacitance between the (J-1)th doped well and the J-th doped well, the J-th doped well and the (J+1)-th doped well among the plurality of doped wells There is a (J+1)th interface parasitic capacitance between them, there is a corresponding interface parasitic capacitance between the last doping well of the plurality of doping wells and the substrate 200, and a (J+1)th compensation capacitance, It is electrically connected between the Jth doped well and the first reference potential for compensating the (J+1)th interface parasitic capacitance, wherein J can be a positive integer greater than or equal to four.

Similarly, the Nth interface parasitic capacitance of one of the first interface parasitic capacitance 120, the second interface parasitic capacitance 122, the third interface parasitic capacitance 124, and the fourth interface parasitic capacitance 136 has the smallest capacitance value, and the Mth interface parasitic capacitance has a capacitance value different from the Nth interface parasitic capacitance (for example, the maximum capacitance value), then the capacitance value of the Nth compensation capacitor corresponding to the Nth interface parasitic capacitance is the same as the capacitance value of the Nth interface parasitic capacitance. The difference in the capacitance value of the parasitic capacitance. In addition, the Nth compensation capacitor is not limited to only include a single physical capacitor, but can also be an Nth equivalent compensation capacitor formed by one or more interconnected electronic components, as long as the Nth compensation capacitor is the same as the Nth equivalent compensation capacitor. It is sufficient that the equivalent capacitance values of the capacitors are the same.

To sum up, because the present invention applies different predetermined voltages to different doped wells to increase the reverse bias voltage across the parasitic diodes of each interface when the transistor transmits signals, or uses at least one compensation capacitor to compensate at least one interface The parasitic capacitance makes the cross-voltage difference between the parasitic capacitances of at least one interface small, so compared with the prior art, the present invention can increase the signal amplitude range.

Unless otherwise specified, the qualifiers similar to "first" and "second" appearing in this article do not refer to the limitation of time sequence, quantity, or importance, but are only for the purpose of combining one technology in this technical solution A characteristic is distinguished from another technical characteristic. Similarly, the qualifiers similar to "a" appearing in this article do not refer to a limitation on quantity, but describe technical features that have not appeared above. Likewise, modifiers like "about" and "approximately" that appear before numerals in this article generally include the original number, and their specific meanings should be understood in conjunction with the context. Similarly, unless it is a noun modified by a specific quantitative quantifier, it should be deemed to include both the singular form and the plural form in this article. In this technical solution, the singular number of the technical features can also be included. technical characteristics.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims (15)

1. A transistor for increasing a signal amplitude range, comprising:

a first doped well formed in a structural layer;

A second doped well formed in the structural layer, wherein the second doped well is formed between the first doped well and the structural layer;

a first doped region formed in the first doped well for transmitting a signal;

A second doped region formed in the first doped well, wherein the first doped region, the second doped region and the second doped well have a first conductivity type, and the first doped well has a second conductivity type;

A gate layer for forming a channel between the first doped region and the second doped region; and

At least one compensation capacitor formed outside the first doped region, the second doped region, the first doped well, the second doped well and the structural layer and electrically connected between the first doped region and the first doped well, or between the first doped well and the second doped well, or between the second doped well and a first reference potential, the first reference potential being electrically connected to the structural layer;

Wherein a first interface parasitic capacitor is arranged between the first doped region and the first doped well, a second interface parasitic capacitor is arranged between the first doped well and the second doped well, and a third interface parasitic capacitor is arranged between the second doped well and the structural layer; and the at least one compensation capacitor is used for adjusting the voltage across the first interface parasitic capacitor, the second interface parasitic capacitor or the third interface parasitic capacitor.

2. the transistor of claim 1, wherein the at least one compensation capacitor is configured to reduce a difference between a voltage across the first interface parasitic capacitor, a voltage across the second interface parasitic capacitor, and a voltage across the third interface parasitic capacitor.

3. The transistor of claim 1, wherein a capacitance of the at least one compensation capacitor is determined by at least a capacitance of the first interface parasitic capacitor, a capacitance of the second interface parasitic capacitor, and a capacitance of the third interface parasitic capacitor.

4. The transistor of claim 1, wherein the capacitance of the first interface parasitic capacitor, the second interface parasitic capacitor, and the third interface parasitic capacitor is gradually decreased, and the voltage across the first interface parasitic capacitor, the second interface parasitic capacitor, and the third interface parasitic capacitor is equal to the amplitude of the signal.

5. The transistor of claim 1, wherein the first doped well receives a first voltage, the second doped well receives a second voltage, and the first voltage and the second voltage are opposite in electrical polarity.

6. The transistor of claim 1, wherein the at least one compensation capacitor is a metal-insulator-metal capacitor.

7. The transistor of claim 1, wherein the at least one compensation capacitor comprises a first compensation capacitor electrically connected between the first doped region and the first doped well for compensating the first interface parasitic capacitance.

8. The transistor of claim 1, wherein the at least one compensation capacitor comprises a second compensation capacitor electrically connected between the first doped well and the second doped well for compensating the second interface parasitic capacitance.

9. The transistor of claim 1, wherein the at least one compensation capacitor comprises a third compensation capacitor electrically connected between the second doped well and the first reference potential for compensating the third interface parasitic capacitance.

10. The transistor of claim 1, wherein the structural layer further comprises a third doped well and a substrate, the third doped well is formed in the substrate, and the third doped well is formed between the second doped well and the substrate, wherein the third doped well has the second conductivity type, a second reference potential is electrically connected to the third doped well, the first reference potential is electrically connected to the structural layer, a fourth interface parasitic capacitor is formed between the third doped well and the substrate, and a capacitance of the at least one compensation capacitor is determined by at least a capacitance of the first interface parasitic capacitor, a capacitance of the second interface parasitic capacitor, a capacitance of the third interface parasitic capacitor, and a capacitance of the fourth interface parasitic capacitor; and the at least one compensation capacitor comprises a fourth compensation capacitor which is electrically connected between the third doped well and the first reference potential and is used for compensating the parasitic capacitor of the fourth interface.

11. The transistor of claim 10, wherein the structural layer further comprises a fourth doped well formed between the third doped well and the substrate, wherein the fourth doped well has a different conductivity type than the third doped well, wherein a third reference potential is electrically connected to the fourth doped well, wherein a fifth interface parasitic capacitor is formed between the fourth doped well and the substrate, and wherein the at least one compensation capacitor comprises a fifth compensation capacitor electrically connected between the fourth doped well and the first reference potential for compensating the fifth interface parasitic capacitor.

12. The transistor of claim 10, wherein the structural layer further comprises a plurality of doped wells formed between the third doped well and the substrate, wherein a J-th doped well of the plurality of doped wells has a different conductivity type than a J-1 th doped well of the plurality of doped wells, and a J-1 th reference potential is electrically connected to the J-th doped well, a J-th interface parasitic capacitor is formed between the J-1 th doped well and the J-th doped well, a J +1 th interface parasitic capacitor is formed between the J-th doped well and a J +1 th doped well of the plurality of doped wells, a corresponding interface parasitic capacitor is formed between a last doped well of the plurality of doped wells and the substrate, and the at least one compensation capacitor comprises a J +1 th compensation capacitor, and the second reference potential is electrically connected between the J-th doped well and the first reference potential and is used for compensating the parasitic capacitance of the J + 1-th interface, wherein J is a positive integer greater than or equal to four.

13. The transistor of claim 1, wherein an Nth interface parasitic capacitor of the first, second and third interface parasitic capacitors has a minimum capacitance, and an Mth interface parasitic capacitor has a capacitance different from the Nth interface parasitic capacitor; wherein

When N is 1, the at least one compensation capacitor includes a first equivalent compensation capacitor electrically connected between the first doped region and the first doped well, and a capacitance of the first equivalent compensation capacitor is a difference between a capacitance of the mth interface parasitic capacitor and a capacitance of the first interface parasitic capacitor;

When N is 2, the at least one compensation capacitor includes a second equivalent compensation capacitor electrically connected between the first doped well and the second doped well, and a capacitance of the second equivalent compensation capacitor is a difference between a capacitance of the mth interface parasitic capacitor and a capacitance of the second interface parasitic capacitor; or

When N is 3, the at least one compensation capacitor includes a third equivalent compensation capacitor electrically connected between the second doped well and the first reference potential, and a capacitance of the third equivalent compensation capacitor is a difference between a capacitance of the mth interface parasitic capacitor and a capacitance of the third interface parasitic capacitor.

14. the transistor for increasing signal amplitude range of claim 1, the transistor for increasing the signal amplitude range further comprises a third doped well formed in a substrate and between the second doped well and the substrate, wherein the third doped well has the second conductivity type, and a second reference potential is electrically connected to the third doped well, the first reference potential is electrically connected to the structural layer, a fourth interface parasitic capacitance is arranged between the third doped well and the structural layer, wherein an Nth interface parasitic capacitor among the first interface parasitic capacitor, the second interface parasitic capacitor, the third interface parasitic capacitor and the fourth interface parasitic capacitor has a minimum capacitance value, and an Mth interface parasitic capacitance has a capacitance value different from the Nth interface parasitic capacitance; wherein

When N is 1, the at least one compensation capacitor includes a first equivalent compensation capacitor electrically connected between the first doped region and the first doped well, and a capacitance of the first equivalent compensation capacitor is a difference between a capacitance of the mth interface parasitic capacitor and a capacitance of the first interface parasitic capacitor;

When N is 2, the at least one compensation capacitor includes a second equivalent compensation capacitor electrically connected between the first doped well and the second doped well, and a capacitance of the second equivalent compensation capacitor is a difference between a capacitance of the mth interface parasitic capacitor and a capacitance of the second interface parasitic capacitor;

When N is 3, the at least one compensation capacitor includes a third equivalent compensation capacitor electrically connected between the second doped well and the first reference potential, and a capacitance of the third equivalent compensation capacitor is a difference between a capacitance of the mth interface parasitic capacitor and a capacitance of the third interface parasitic capacitor; or

When N is 4, the at least one compensation capacitor includes a fourth equivalent compensation capacitor electrically connected between the third doped well and the second reference potential, and a capacitance of the fourth equivalent compensation capacitor is a difference between a capacitance of the mth interface parasitic capacitor and a capacitance of the fourth interface parasitic capacitor.

15. The transistor of claim 13 or 14, wherein the Mth interface parasitic capacitor has a largest capacitance value among the interface parasitic capacitors.