CN107808863B - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN107808863B CN107808863B CN201711047610.7A CN201711047610A CN107808863B CN 107808863 B CN107808863 B CN 107808863B CN 201711047610 A CN201711047610 A CN 201711047610A CN 107808863 B CN107808863 B CN 107808863B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/40—OLEDs integrated with touch screens
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1414—Circular array, i.e. array with radial symmetry
- H01L2224/14141—Circular array, i.e. array with radial symmetry being uniform, i.e. having a uniform pitch across the array
Abstract
The invention relates to the technical field of display, in particular to an array substrate and a display panel. The array substrate includes: the bonding pad comprises a bonding pad area and a plurality of bonding pads, wherein the bonding pad area is provided with at least one arc-shaped edge; each bonding pad is sequentially arranged in the bonding pad area along the arc-shaped edge, each bonding pad comprises a first edge and a second edge which are opposite and not intersected, the first edge is adjacent to the arc-shaped edge, and the distance between two end points of the first edge is not equal to the distance between two end points of the second edge. In this embodiment, when the pad on the array substrate is bonded to other structures, because the distance between the two end points of the first edge and the distance between the two end points of the second edge, which are opposite and non-intersecting, on the pad are not equal, the situation that one edge of the pad deviates and the other edge deviates integrally can be alleviated, so that the situation that the bonding pad is poorly bonded can be alleviated.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate and a display panel.
Background
Along with the popularization of the display screen in the application of vehicle-mounted equipment (automobile instrument panel), intelligent wearable equipment and other portable electronic equipment, the special-shaped display screen is favored by consumers.
Compared with a conventional display screen, the special-shaped display screen is mainly different in that an array area of the special-shaped display screen is in a non-rectangular special shape. Generally speaking, the pad in the display screen is mostly the rectangle structure, and when this rectangle pad was applied to special-shaped display screen, especially when being applied to circular display screen, the border of rectangle pad and array region can not completely cooperate to reduced the area of contact of pad, be difficult for the pad to bind, and bind the in-process at it and cause easily and bind badly.
Disclosure of Invention
The invention provides an array substrate and a display panel, which can relieve the condition of poor bonding of a bonding pad.
The present invention provides an array substrate, which includes:
a pad region having at least one arcuate edge;
the bonding pads are sequentially arranged in the bonding pad area along the arc-shaped edge and comprise a first edge and a second edge which are opposite and not intersected, the first edge is adjacent to the arc-shaped edge, and the distance between two end points of the first edge is not equal to the distance between two end points of the second edge.
The invention also provides a display panel which comprises the array substrate.
The technical scheme provided by the invention can achieve the following beneficial effects:
the array substrate provided by the invention comprises a bonding pad area with at least one arc-shaped edge and a plurality of bonding pads which are sequentially arranged in the bonding pad area along the arc-shaped edge, each bonding pad comprises a first edge and a second edge which are opposite and not intersected, and the distance between two end points of the first edge is not equal to the distance between two end points of the second edge. When the bonding pad on the array substrate is bonded with other structures (such as a chip on film), because the distance between the two end points of the first edge and the distance between the two end points of the second edge, which are opposite and not intersected, on the bonding pad are not equal, the situation that one edge of the bonding pad deviates and the other edge deviates integrally can be relieved, and the situation that the bonding pad is bonded badly can be relieved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
Fig. 1 is a top view of an array substrate according to an embodiment of the invention;
fig. 2 is a top view of a pixel unit in the array substrate according to an embodiment of the present invention;
FIG. 3 is a sectional view taken along line A-A of FIG. 2;
fig. 4 is a top view of an array substrate according to another embodiment of the present invention;
fig. 5 to 21 are schematic partial structural views of array substrates according to different embodiments of the present invention.
Reference numerals:
1-an array substrate;
10-a pad region;
100-a first arc-shaped edge;
102-a second arc-shaped edge;
12-a pad;
120-first side;
122-a second edge;
124-third side;
126-fourth side;
14-an array region;
140-pixel cells;
140 a-source;
140 b-drain;
140 c-a gate;
140 d-pixel electrode;
142-a lead;
144-touch electrodes;
16-substrate base plate.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
Detailed Description
The present invention will be described in further detail below with reference to specific embodiments and with reference to the attached drawings. In order to make the aforementioned objects, features and advantages of the present invention comprehensible, the present invention is further described with reference to the accompanying drawings and examples. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their repetitive description will be omitted. The words expressing the position and direction described in the present invention are illustrated in the accompanying drawings, but may be changed as required and still be within the scope of the present invention. The drawings of the present invention are only for illustrating the relative positional relationship, the layer thicknesses of some parts are exaggerated in a drawing manner for easy understanding, and the layer thicknesses in the drawings do not represent the proportional relationship of the actual layer thicknesses.
It should be noted that in the following description, specific details are set forth in order to provide a thorough understanding of the present invention. The invention can be implemented in a number of ways different from those described herein and similar generalizations can be made by those skilled in the art without departing from the spirit of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. The following description is of the preferred embodiment for carrying out the invention and is made for the purpose of illustrating the general principles of the invention and not for the purpose of limiting the scope of the invention. The scope of the present invention is defined by the appended claims.
The present invention will be described in further detail below with reference to specific embodiments and with reference to the attached drawings. The thicknesses and shapes of the respective components in the drawings do not reflect the true scale of the display device, and are merely intended to schematically illustrate the present invention. It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
Fig. 1 is a top view of an array substrate 1 according to an embodiment of the present invention, where the array substrate 1 may be applied to a liquid crystal display panel, an organic light emitting display panel, and a touch sensor.
As shown in fig. 1, the array substrate 1 at least includes a pad region 10 and an array region 14 adjacent to the pad region 10, wherein the array region 14 is a working region of the array substrate 1 and may include a lead 142 (signal line) such as a gate line, a data line and a touch line, a pixel unit 140, a touch electrode, and other components; the pad area 10 is a region for bonding the signal lines of the array substrate 1 and the signal lines of an external driving circuit board (e.g., a chip on film), and generally has only leads, and does not require components such as pixel units.
In order to facilitate the electrical connection between the external driving circuit board and the signal lines of the array substrate 1, a plurality of pads 12 may be disposed on the pad region 10, and each pad 12 is electrically connected to the signal lines of the pad region 10, and is equivalent to a pin of a signal line and used for electrically connecting to the external driving circuit board.
Specifically, the array substrate 1 may further include a substrate 16, and the array region 14 includes a plurality of pixel units 140, each pixel unit 140 is located on the substrate 16 and arranged in an array, a row direction of the array is an x direction shown in fig. 1, and a column direction of the array is a y direction shown in fig. 1, it should be noted that the number of the pixel units 140 in each row or each column may not be equal, that is, each pixel unit 140 may be arranged in a non-rectangular array.
Fig. 2 is a schematic structural diagram of the pixel unit 140, and fig. 3 is a cross-sectional view taken along line a-a of fig. 2. As shown in fig. 2 and 3, each pixel unit 140 includes a thin film transistor and a pixel electrode 140d, the thin film transistor includes a source 140a, a drain 140b and a gate 140c, wherein the source 140a, the drain 140b, the gate 140c and the pixel electrode 140d are sequentially disposed on the substrate 16, the gate 140c is electrically connected to the gate line, and the source 140 a/the drain 140b are respectively electrically connected to the data line and the pixel electrode 140 d.
As shown in fig. 1 and 2, the array region 14 includes a plurality of leads 142, and one end of the lead 142 enters the pad region 10 and is electrically connected to the pad 12. Alternatively, the source electrode 140a or the drain electrode 140b of the thin film transistor may be electrically connected to the other end of the wire 142, that is, at least a portion of the wire 142 of the array region 14 may be a data line, one end of which is electrically connected to the pad 12, and the other end of which is electrically connected to the source electrode 140a or the drain electrode 140b of the thin film transistor.
When the array substrate 1 is applied to a touch sensor, as shown in fig. 4, the array region 14 includes a plurality of touch electrodes 144 for sensing a touch. Specifically, the touch electrode 144 can be electrically connected to another end of the lead 142, that is, at least a portion of the lead 142 in the array region 14 can be a touch line, and two ends of the touch line are electrically connected to the touch electrode 144 and the pad 12, respectively.
In the thickness direction of the array substrate 1, the touch electrode 144 may be reused as a common electrode, and the common electrode is preferably rectangular block-shaped. As shown in fig. 1 and 4, the pad region 10 has at least one arc-shaped edge, and the arc-shaped edge is curved, so as to sufficiently improve the space utilization rate of the pad region 10, each pad 12 may be sequentially disposed in the pad region 10 along the arc-shaped edge, that is, the arrangement direction of each pad 12 is the same as the extension direction of the arc-shaped edge, such that the space utilization rate of the pad region 10 may be improved, so as to increase the contact area of the pad 12, and as the contact area of the pad 12 is increased, on one hand, the pad 12 on the pad region 10 is used for being bound with other structures, on the other hand, the binding resistance of the pad 12 may be reduced, and the display effect of the array region 14 may be improved.
Each pad 12 includes a first edge 120 and a second edge 122 that are opposite and do not intersect each other, the first edge 120 is adjacent to the arc-shaped edge, and a distance between two end points of the first edge 120 is not equal to a distance between two end points of the second edge 122. That is, if the side with a smaller distance between the two end points of the first side 120 and the second side 122 is offset relative to other structures during the bonding process of the pad 12 on the array substrate 1 and other structures, because the distance between the two end points of the other side is relatively larger, at least a part of the other side with a larger distance between the two end points can still be opposite to other structures and can realize the bonding of the pad 12 and other structures in the thickness direction of the array substrate 1, and the condition of poor bonding of the pad 12 is alleviated.
It should be noted that the other structure mentioned above for binding with the pad 12 of the pad area 10 may be a pad on a chip on film (cof) or a Flexible Printed Circuit (FPC), that is, the pad 12 on the pad area 10 may be bound with a pad on the cof or the FPC to provide a signal to the array area 14.
Optionally, at least one arc-shaped edge of the pad region 10 is a boundary between the array region 14 and the pad region 10. That is, the array region 14 adjacent to the pad region 10 is a shaped region (i.e., a non-rectangular region), for example, a circular region as shown in fig. 1 and 4, and the array substrate 1 having this shaped array region 14 can be applied to a wearable display (e.g., a watch) and a shaped display panel (i.e., a non-rectangular display panel) that is easily equipped on a dashboard of an automobile.
In one embodiment of the present invention, the arc-shaped edge has a convex side B and a concave side C (as shown in fig. 5), when the bonding pad 12 is located on the convex side B of the arc-shaped edge, the distance between the two end points of the first edge 120 is smaller than the distance between the two end points of the second edge 122, and when the bonding pad 12 is located on the concave side C of the arc-shaped edge, the distance between the two end points of the first edge 120 is larger than the distance between the two end points of the second edge 122.
Since the first edge 120 and the second edge 122 are part of the pad 12, when the pad 12 is located on the convex side B of the arc-shaped edge, it is indicated that the first edge 120 and the second edge 122 of the pad 12 are also located on the convex side B of the arc-shaped edge. Since the first edge 120 is adjacent to the arc-shaped edge, that is, the first edge 120 is closer to the convex side B of the arc-shaped edge than the second edge 122, the distance between two end points of the first edge 120 can be designed to be smaller than the distance between two end points of the second edge 122, and by designing the distance between two end points of the first edge 120 to be relatively smaller, the space at the convex side B of the arc-shaped edge can be fully utilized, so as to increase the bonding area of each bonding pad 12 and enable more bonding pads 12 to be disposed on the bonding pad region 10.
Similarly, when the pad 12 is located on the concave side C of the arc-shaped edge, it is indicated that the first edge 120 and the second edge 122 of the pad 12 are also located on the concave side C of the arc-shaped edge. Since the first edge 120 is adjacent to the arc-shaped edge, that is, the first edge 120 is closer to the concave side C of the arc-shaped edge than the second edge 122, the distance between two end points of the first edge 120 can be designed to be larger than the distance between two end points of the second edge 122, and by designing the distance between two end points of the first edge 120 to be relatively larger, the space at the concave side C of the arc-shaped edge can be fully utilized, so as to increase the bonding area of each pad 12 and enable more pads 12 to be disposed on the pad region 10.
Fig. 5 to 21 are schematic partial structural views of an array substrate 1 according to different embodiments of the present invention. Optionally, at least two arc-shaped sides of the pad region 10 include a first arc-shaped side 100 and a second arc-shaped side 102 which are opposite to each other, and the concave-convex directions of the first arc-shaped side 100 and the second arc-shaped side 102 are the same. The bonding pad 12 is located between the first arc-shaped edge 100 and the second arc-shaped edge 102, the first edge 120 of the bonding pad 12 is close to the first arc-shaped edge 100, the second edge 122 of the bonding pad 12 is close to the second arc-shaped edge 102, and the distance between two end points of the first edge 120 is smaller than the distance between two end points of the second edge 122. That is, the pad 12 is disposed on the pad region 10 and located on the convex side B of the first arc-shaped side 100 and the concave side C of the second arc-shaped side 102, so that the space of the pad region 10 can be fully utilized by the design: the space at the convex side B of the first arc-shaped edge 100 and the space at the concave side C of the second arc-shaped edge 102 can be sufficiently utilized to enable more pads 12 to be disposed on the pad region 10 while increasing the bonding area of each pad 12.
The first arc-shaped edge 100 and the second arc-shaped edge 102 of the pad area 10 may both be arc-shaped, and the center of circle of the first arc-shaped edge 100 coincides with the center of circle of the second arc-shaped edge 102, that is, in the direction in which the first arc-shaped edge 100 points to the second arc-shaped edge 102 and passes through the center of circle of the first arc-shaped edge 100 (the second arc-shaped edge 102), the distance between two relative points on the first arc-shaped edge 100 and the second arc-shaped edge 102 is equal everywhere, so that the pads 12 sequentially arranged along the arc-shaped edges of the pad area 10 can adopt the same specification, thereby reducing the design difficulty of the array substrate 1, and facilitating the binding of the array substrate 1 with other structures.
Since the first arc-shaped edge 100 and the second arc-shaped edge 102 of the pad region 10 can both be arc-shaped, the pad region 10 can be adapted to the array region 14 having an arc-shaped boundary, for example: the array region 14 is circular, and the pad region 10 is a circular pad region 10 disposed around the array region 14, as shown in fig. 1 and 4, wherein the first arc-shaped edge 100 may be a portion of an inner ring edge of the circular pad region 10, and the second arc-shaped edge 102 may be a portion of an outer ring edge of the circular pad region 10.
As shown in fig. 5 to 16, in an embodiment of the present invention, at least one of the first edge 120 and the second edge 122 is a circular arc edge, and a center of the circular arc edge coincides with a center of the first arc edge 100, so as to ensure that a distance between two opposite points on the circular arc edge and the first arc edge 100 (the second arc edge 102) is equal everywhere in a direction in which the first arc edge 100 points to the second arc edge 102 and passes through the center of the first arc edge 100 (the second arc edge 102). When the distance between two opposite points on the arc edge and the first arc edge 100 is equal to zero or equal to the difference between the radius of the second arc edge 102 and the radius of the first arc edge 100, it indicates that the arc edge is overlapped with the first arc edge 100 or the second arc edge 102 without a gap, so that the pad 12 can fully utilize the space at the first arc edge 100 or the second arc edge 102 on the pad region 10, effectively increase the binding area of the pad 12, and alleviate the situation that the pad 12 is poorly bound with other structures.
In addition, according to the resistance formula, when the material and the thickness of each pad 12 (the thickness direction of the pad 12 is the same as the thickness direction of the array substrate 1) are constant, the larger the cross-sectional area (i.e., the bonding area) of the pad 12 is, the smaller the bonding resistance of the pad 12 is, and the bonding resistance of the pad 12 is reduced, so that the energy consumed by the pad 12 is reduced, and the display effect of the array region 14 can be improved.
In an optional scheme, as shown in fig. 5, the first edge 120 and the second edge 122 are both arc edges, and the first edge 120 coincides with the first arc edge 100, and the second edge 122 coincides with the second arc edge 102, that is, there is no gap between the first edge 120 and the first arc edge 100, and there is no gap between the second edge 122 and the second arc edge 102, so that the space at the first arc edge 100 and the second arc edge 102 on the pad region 10 is fully utilized by the pad 12, and the binding area of the pad 12 is greatly increased. Because the bonding area of the bonding pad 12 is increased, the bonding resistance of the bonding pad 12 is effectively reduced, and the alignment difficulty of the bonding pad 12 on the bonding pad region 10 and other structures is reduced. In addition, since the first edge 120 is overlapped with the first arc-shaped edge 100 and the second edge 122 is overlapped with the second arc-shaped edge 102, when the pad 12 is disposed on the pad region 10, only the positional relationship between the first edge 120 and the first arc-shaped edge 100 or the positional relationship between the second edge 122 and the second arc-shaped edge 102 need to be positioned, and the positional relationship between the first edge 120 and the first arc-shaped edge 100 and the positional relationship between the second edge 122 and the second arc-shaped edge 102 do not need to be positioned at the same time, so that the assembly efficiency of the pad 12 and the pad region 10 is improved.
Preferably, a connection line between two opposite end points of the first edge 120 and the second edge 122 passes through a center of the first arc-shaped edge 100 (the second arc-shaped edge 102), that is, central angles corresponding to the first edge 120 and the second edge 122 are the same, and according to the similar triangle theorem, a ratio of a side length of the first edge 120 to a side length of the second edge 122 is: the ratio of the radius of the first arc-shaped edge 100 to the radius of the second arc-shaped edge 102 is designed such that the difference between the side length of the second edge 122 and the side length of the first edge 120 is prevented from being too large, that is, the design such that the second edge 122 is prevented from being too long and occupying a large space at the second arc-shaped edge 102 is prevented from being too short and occupying a small space at the first arc-shaped edge 100 is prevented from being too short, thereby causing the situation that the space at the first arc-shaped edge 100 is wasted, the ratio of the side length of the first edge 120 to the side length of the second edge 122 is reasonably designed, the binding area of each pad 12 can be increased, and meanwhile, the space of the pad area is reasonably utilized, so that more pads 12 are arranged on the pad area 10. In another alternative, as shown in fig. 9, the first edge 120 is a straight edge, and the first edge 120 is designed as a straight edge, so that the processing difficulty of the pad 12 can be reduced, and the first edge 120 is tangent to the first arc-shaped edge 100, so that the space at the first arc-shaped edge 100 on the pad region 10 can be fully utilized to increase the bonding area of the pad 12; the second edge 122 is an arc edge, and the second edge 122 coincides with the second arc edge 102 (i.e., there is no gap), so that the space at the second arc edge 102 on the pad region 10 can be fully utilized, the bonding area of the pad 12 is further increased, and the poor bonding between the pad 12 and other structures is alleviated. Because the second edge 122 and the second arc-shaped edge 102 are both arc edges, and the second edge 122 and the second arc-shaped edge 102 can be overlapped, when the pad 12 is positioned in the pad region 10, the second edge 122 and the second arc-shaped edge 102 can be positioned first, and specifically, the second edge 122 and the second arc-shaped edge 102 can be positioned only by completely overlapping the second edge 122 and the second arc-shaped edge 102. When the second edge 122 completely overlaps the second arc-shaped edge 102, the first edge 120 is naturally tangent to the first arc-shaped edge 100 due to the design of the pad, and the first edge 120 and the first arc-shaped edge 100 do not need to be positioned, thereby improving the assembly efficiency of the pad 12 and the pad region 10. It should be noted that, since the second arc-shaped edge 102 is an edge far from the array region 14, the second edge 122 and the second arc-shaped edge 102 are positioned to realize the assembly of the pad 12 and the pad region 10, which can alleviate the situation that the assembly jig or the pad 12 damages the array region 14 during the assembly process.
In addition, since the second arc-shaped edge 102 is an edge far from the array region 14, and when the circle center angles corresponding to the second arc-shaped edge 102 and the first arc-shaped edge 100 are the same, the length of the second arc-shaped edge 102 is greater than that of the first arc-shaped edge 100, by overlapping the second edge 122 and the second arc-shaped edge 102, the bonding area of the pad 12 is increased, and at the same time, more pads 12 can be arranged on the pad region 10.
In yet another alternative, as shown in fig. 13, the first edge 120 is an arc edge, and the first edge 120 coincides with the first arc edge 100 (i.e., there is no gap), so that the space at the first arc edge 100 on the pad region 10 can be fully utilized to increase the bonding area of the pad 12; the second edge 122 is a straight edge, the processing difficulty of the pad 12 can be reduced by designing the second edge 122 as a straight edge, and the two end points of the second edge 122 are located on the second arc-shaped edge 102, so that the space at the second arc-shaped edge 102 on the pad region 10 can be fully utilized, the binding area of the pad 12 is further increased, and the condition that the pad 12 is poorly bound with other structures is alleviated.
Based on the above three schemes, there are overlapping portions between the first edge 120 and the first arc-shaped edge 100 and between the second edge 122 and the second arc-shaped edge 102, so that the pads 12 are disposed on the pad region 10 in a single row along the extending direction of the first arc-shaped edge 100 (the second arc-shaped edge 102). In this embodiment, the pads 12 are arranged on the pad region 10 in a single row, so that the bonding area of the pads can be increased, and the difficulty of arranging the pads 12 on the pad region 10 can be reduced.
As shown in fig. 17 to 20, in another embodiment of the present invention, the first side 120 and the second side 122 are both straight sides, and the first side 120 and the second side 122 of the pad region 10 are both processed into straight sides, so that the processing difficulty of the pad 12 can be greatly reduced, and the first side 120 and the second side 122 are parallel, so that the bonding area of the pad 12 can be increased, and the space utilization rate of the pad region 10 can be increased, so as to provide more pads 12 on the pad region 10.
Alternatively, as shown in fig. 17, the first edge 120 is tangent to the first arc-shaped edge 100, and two end points of the second edge 122 are located on the second arc-shaped edge 102, so that the space at the first arc-shaped edge 100 and the second arc-shaped edge 10 on the pad region 10 is fully utilized, and the bonding area of the pad 12 is increased.
Optionally, the distances between the two end points of the first edge 120 and the center of the first arc-shaped edge 100 are equal, so that a connection line between the midpoint of the first edge 120 and the center of the first arc-shaped edge 100 is perpendicular to the first edge 120, wherein the midpoint of the first edge 120 is the tangent point between the first edge 120 and the first arc-shaped edge 100, and thus the design can ensure that the areas of the gaps between the first edges 120 at the two sides of the tangent point and the first arc-shaped edge 100 are the same, and avoid the situation that the area of the gap at one side is too large and the area of the gap at the other side is too small, which causes the space waste at the first arc-shaped edge 100, effectively improve the space utilization rate of the pad area 10, and increase the binding area of each pad 12 and enable more pads 12 to be arranged on the.
It should be noted that, when the first edge 120 and the second edge 122 are both arc edges, as shown in fig. 6 to 8, the first edge 120 and the first arc edge 100 may be separately disposed, and the second edge 122 and the second arc edge 102 may also be separately disposed; when the first edge 120 is a straight edge and the second edge 122 is a circular arc edge, as shown in fig. 10 to 12, the first edge 120 and the first arc edge 100 can be separated from each other, and the second edge 122 and the second arc edge 102 can also be separated from each other; when the first edge 120 is a circular arc edge and the second edge 122 is a straight edge, as shown in fig. 14 to 16, the first edge 120 and the first arc edge 100 can be separated from each other, and the second edge 122 and the second arc edge 102 can also be separated from each other; when the first edge 120 and the second edge 122 are both straight edges, as shown in fig. 18 to 20, the first edge 120 may be provided separately from the first arc-shaped edge 100, and the second edge 122 may be provided separately from the second arc-shaped edge 102.
The above design can appropriately reduce the processing difficulty of the pad 12 while avoiding the pad 12 exceeding the pad region 10, thereby improving the processing efficiency of the pad 12.
As shown in fig. 5 to 20, the bonding pad 12 in each embodiment further includes a third side 124 and a fourth side 126 connecting the first side 120 and the second side 122, and the third side 124 and the fourth side 126 are both straight sides. By designing the third edge 124 and the fourth edge 126 as straight edges, on one hand, the processing difficulty of the bonding pad 12 can be reduced, and the production efficiency of the bonding pad 12 can be improved, and on the other hand, the bonding pad 12 on the array substrate 1 can be aligned with other structures conveniently, so that the bonding efficiency of the bonding pad 12 on the array substrate 1 and other structures can be improved.
Preferably, the length of the third side 124 is equal to the length of the fourth side 126. That is, the bonding pad 12 has an axisymmetric structure, wherein the symmetry axis of the bonding pad 12 passes through the midpoints of the first side 120 and the second side 122. By arranging the pads 12 in an axisymmetric structure, on one hand, the processing difficulty of the pads 12 can be reduced, and on the other hand, the space of the pad region 10 can be fully utilized, so that the bonding area of each pad 12 is increased, and at the same time, more pads 12 can be arranged on the pad region 10.
As mentioned above, the array region 14 includes a plurality of leads 142, one end of each lead 142 enters the pad region 10 and is electrically connected to one pad 12, and when the number of leads 142 is large and the space of the pad region 10 is limited, as shown in fig. 21, each pad 12 may be divided into at least two rows, and each row of pads includes a plurality of pads 12 sequentially arranged along the extending direction of the arc-shaped edge. The shape of each pad in fig. 21 is not limited to this, and may be the shape of any pad 12 shown in fig. 5, 9, 13, and 17.
Preferably, the pads 12 in two adjacent rows are offset in the direction that the second edge 122 points to the first edge 120, so that the routing path of the lead 142 can be reduced, and the connection difficulty between the lead 142 and the pads 12 can be reduced.
Based on the above structure, the present invention further provides a display panel including the array substrate 1 described in any of the above embodiments. The display panel can be a liquid crystal display panel or an organic light emitting display panel.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. An array substrate, comprising:
a pad region having at least one arcuate edge;
the bonding pads are sequentially arranged in the bonding pad area along the arc-shaped edge and comprise a first edge and a second edge which are opposite and not intersected, the first edge is adjacent to the arc-shaped edge, and the distance between two end points of the first edge is not equal to the distance between two end points of the second edge;
the bonding pad is positioned between the first arc-shaped edge and the second arc-shaped edge, the concave-convex directions of the first arc-shaped edge and the second arc-shaped edge are the same, the first edge is close to the first arc-shaped edge, the second edge is close to the second arc-shaped edge, and the distance between two end points of the first edge is smaller than the distance between two end points of the second edge;
the first arc-shaped edge and the second arc-shaped edge are both arc-shaped, and the circle center of the first arc-shaped edge is superposed with the circle center of the second arc-shaped edge;
the ratio of the side length of the first edge to the side length of the second edge is as follows: a ratio of a radius of the first arcuate edge to a radius of the second arcuate edge;
wherein the content of the first and second substances,
the first edge and the second edge are both arc edges, the first edge is overlapped with the first arc edge, and the second edge is overlapped with the second arc edge;
alternatively, the first and second electrodes may be,
the first edge is a straight line edge, the second edge is an arc edge, the first edge is tangent to the first arc edge, and the second edge is superposed with the second arc edge;
alternatively, the first and second electrodes may be,
the first edge and the second edge are both straight edges, the first edge and the second edge are parallel, the first edge is tangent to the first arc-shaped edge, and two end points of the second edge are located on the second arc-shaped edge;
alternatively, the first and second electrodes may be,
the first edge and the second edge are both straight edges, the first edge and the second edge are parallel, and the distance between the two end points of the first edge and the circle center of the first arc-shaped edge is equal.
2. The array substrate of claim 1,
when the bonding pad is positioned on the convex side of the arc-shaped edge, the distance between two end points of the first edge is smaller than the distance between two end points of the second edge;
when the bonding pad is positioned on the concave side of the arc-shaped edge, the distance between two end points of the first edge is larger than the distance between two end points of the second edge.
3. The array substrate of claim 1,
each of the pads further includes a third edge and a fourth edge connecting the first edge and the second edge, and the third edge and the fourth edge are both straight edges.
4. The array substrate of claim 3,
the length of the third side is equal to the length of the fourth side.
5. The array substrate of claim 1,
each bonding pad is divided into at least two rows of bonding pad groups, and each row of bonding pad group comprises a plurality of bonding pads which are sequentially arranged along the extending direction of the arc-shaped edge.
6. The array substrate of claim 5,
and the bonding pads in the two adjacent rows of bonding pad groups are arranged in a staggered manner in the direction of the second edge pointing to the first edge.
7. The array substrate of claim 1, further comprising:
the array area is adjacent to the pad area and comprises a plurality of leads, and one ends of the leads enter the pad area and are electrically connected with the pads;
at least one of the arc-shaped edges is a boundary between the array region and the pad region.
8. The array substrate of claim 7, wherein the array region further comprises a plurality of thin film transistors, and the source or drain of each thin film transistor is electrically connected to the other end of the lead.
9. The array substrate of claim 7, wherein the array region further comprises a plurality of touch electrodes electrically connected to the other ends of the leads.
10. A display panel comprising the array substrate of any one of claims 1 to 9.
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| US10546912B2 (en) | 2018-04-19 | 2020-01-28 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel and display device |
| CN110265445B (en) | 2019-06-21 | 2021-09-21 | 京东方科技集团股份有限公司 | Display device and electronic device |
| CN113421491A (en) * | 2021-06-17 | 2021-09-21 | 合肥维信诺科技有限公司 | Chip on film, display panel and display device |
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| CN105044960A (en) * | 2015-09-15 | 2015-11-11 | 京东方科技集团股份有限公司 | Substrate for display and wearable equipment |
| CN206363681U (en) * | 2016-10-20 | 2017-07-28 | 昆山国显光电有限公司 | Display device, display panel, flexible PCB |
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| CN105044960A (en) * | 2015-09-15 | 2015-11-11 | 京东方科技集团股份有限公司 | Substrate for display and wearable equipment |
| CN206363681U (en) * | 2016-10-20 | 2017-07-28 | 昆山国显光电有限公司 | Display device, display panel, flexible PCB |
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