CN107808364B - Medical image block reconstruction system and method based on multiple FPGA - Google Patents
Medical image block reconstruction system and method based on multiple FPGA Download PDFInfo
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Abstract
The invention discloses a medical image block reconstruction system and method based on multiple FPGAs (field programmable gate arrays). The reconstruction system comprises a control unit, multiple FPGA processing units and a control unit, wherein the control unit is connected to a unified Internet network, and the FPGA processing units are used for being connectedAnd connecting parts of the FPGA. The reconstruction method utilizes the medical image block reconstruction system to divide the image content f and the measurement data g into image blocks f respectively through the division of the image content and the fitting method of the measurement dataiAnd measurement data block giWhile blocking the measurement data in the solution processiSelf-updating is performed, thereby improving the existing image reconstruction method to a new block reconstruction method. The technical scheme of the invention realizes the high-energy-efficiency reconstruction of medical images of any size based on the interconnection of multiple FPGAs, can obtain the high-energy-efficiency acceleration effect, and can fully meet the requirements of the future high-resolution image reconstruction.
Description
Technical Field
The invention relates to an image reconstruction technology, in particular to a medical image fast block reconstruction system of a multi-FPGA (Field-Programmable gate array) and a method thereof.
Background
Currently, in the field of medical images, the need for fast image reconstruction has existed from the first day of the emergence of algorithms. In clinical treatment, reconstruction algorithms based on X-ray Computed Tomography (XCT) are widely used. The current iterative XCT algorithm has various problems of large data volume, high calculation complexity and long reconstruction time. Therefore, the XCT image reconstruction speed is a very important index. Currently, accelerated research on XCT reconstruction is a hotspot and difficulty in this field.
In recent years, research has been focused mainly on acceleration methods using a series of hardware such as an FPGA (Field-Programmable Gate Array) and a GPU (Graphics Processing Unit). An FPGA is a general-purpose programmable device that is customizable and reconfigurable to allow for high flexibility. At present, the rapid reconstruction of medical images by using the FPGA is an important research direction in the field.
In the research of accelerating XCT reconstruction by FPGA, a general problem is how to store and access large-scale images. Early studies were conducted to avoid data storage in the FPGA by interacting with external mass storage and computing modules. The method is limited by factors such as communication bandwidth and data reuse rate, and cannot fully exert the speed advantage of the block RAM of the FPGA.
In the latest commercial FPGA suite, abundant Configurable L g-Block resources (C L B), DSP units, and Block RAM (Random Access Memory) are integrated, meanwhile, in order to facilitate writing and debugging by users, various FPGA manufacturers also provide a high-level comprehensive tool (such as Vivado H L S of Xilinx corporation), so that customization becomes easier.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a distributed image reconstruction system based on multiple FPGAs and a medical image block reconstruction method based on multiple FPGAs. The invention can realize the high-energy-efficiency reconstruction of XCT images with any size based on the multi-FPGA interconnection technology.
In order to match with the design of a plurality of FPGA chips and aim at a rapid reconstruction algorithm (the reconstruction algorithm comprises methods such as algebra and iteration) of a plurality of FPGAs, the method introduces a parallel computing technology based on a plurality of FPGAs to establish a new reconstruction algorithm, wherein f and g need to be blocked. In order to ensure the correctness of the blocking, the invention adopts a method of iterative estimation of the projection value of the block image to update g. The method of the invention can overcome the performance limit of single hardware and meet the high performance requirement of XCT, and provides a very good solution.
The present invention promises the following XCT image reconstruction terms, notation and variable definitions:
f: a target image reconstructed from the XCT image;
g: raw measurement data in XCT;
m: the whole image is divided into m blocks with the same size;
fi: segmented images, i.e. block reconstruction algorithms, segmented images comprising f1To fm。fiThe intersection between them is empty and the union is f (covering the whole f without repetition and omission); in general, get fiThe segmentation method of (2) is to cut equal parts in each dimension.
gi: the block projection data is equivalent to the divided measurement data in the block reconstruction algorithm, and contains g1To gm. One giCorresponds to one fiIs actually fiThis portion corresponds to the measurement data.
The technical scheme provided by the invention is as follows:
a medical image block reconstruction system comprises a control unit, a plurality of FPGA processing units and a connecting component, wherein the control unit is connected to a unified interconnection network, the connecting component is used for connecting an FPGA, and the system realizes high-energy-efficiency reconstruction of medical images of any size based on interconnection of a plurality of FPGAs.
For the medical image block reconstruction system, further, the interconnection network adopts a bus-type master-slave distribution structure.
For the medical image block reconstruction system, further, the control unit is implemented by software or hardware; the control unit is a central processing unit with the capability of scheduling and transmitting data, an embedded processor or a soft processor on a certain FPGA.
For the medical image block reconstruction system, the control unit further comprises a data sending module, a data receiving module, a command sending module, a response receiving module, an interconnection control module and a calculation synchronization module; the data sending module is used for sending images and measurement data to the FPGA processing unit; the data receiving module acquires data from the FPGA processing unit and is used for measuring data g in each iteration stageiUpdating of (1); the command sending module is used for driving different FPGA processing units in an iteration process; the response receiving module is used for recording the running state of the FPGA processing unit; the interconnected control moduleThe block is used for connecting the control unit and the FPGA processing unit on a physical layer; the calculation synchronization module updates the measurement data g of each iteration stage after each iteration is finishedi。
For the medical image block reconstruction system, further, the FPGA processing unit is an FPGA; or a plurality of FPGAs are used as the FPGA by an FPGA dividing method; the FPGA processing unit comprises a data receiving module, a data transmission module and an interconnection control module; the data receiving module is used for receiving data sent from the control unit; the data transmission module is used for sending data to the control unit and communicating with other FPGA processing units; and the interconnection control module is used for controlling the communication with other FPGAs.
Further, when a plurality of computing elements PE exist inside a single FPGA processing element, each PE internally includes a storage element and a computing module.
The invention also provides a multi-FPGA-based medical image block reconstruction method, which is characterized in that the medical image block reconstruction system comprising the control unit connected to the unified internet, the plurality of FPGA processing units and the connecting part used for connecting the FPGA is utilized to divide the image content f and the measurement data g into image blocks f respectively through the division of the image content and the fitting method of the measurement dataiAnd measurement data block giWhile blocking the measurement data in the solution processiPerforming a self-update, thereby improving the existing image reconstruction method to a new block reconstruction method; the method comprises the following steps:
A. initializing image content f, image blocks fiThe number of (2) is m;
B. initializing block information for different blocks fiThe boundary of the buffer area is provided with a buffer area;
C. each block fiLoading the data into an FPGA processing unit;
D. iteratively solving for the image content f by:
D1. adjacent each fiTransmitting the respective boundary information to each other, and updating the boundary buffer area of each block;
D2. using an asynchronous parallel iterative method according to fiAnd giUpdate each fiA value of (d);
D3. according to new fiUpdating g by using block image projection value iterative estimation methodi；
D4. If the data still does not converge, jump D1;
FPGA processing unit outputs respective result f to control uniti；
F. Control unit synthesis fiAnd outputting the result f.
For the block reconstruction method, the control unit further comprises a data sending module, a data receiving module, a command sending module, a response receiving module, an interconnection control module and a calculation synchronization module; when the image is blocked by fiWhen the number m of the FPGA processing units exceeds the number of the FPGA processing units, the FPGA processing units are controlled through the calculation synchronization module of the control unit, and on the premise of not damaging synchronization, the redundant calculation tasks are completed in batches.
For the block reconstruction method, further, the existing image reconstruction algorithm includes an algebraic reconstruction method and an iterative algorithm; preferably, the existing image reconstruction method adopts a reconstruction method based on a Mumford-Shah model.
In the block reconstruction method, the self-updating method is one of a least square method, a regularization method and a regularization method using a Kullback-L eibler difference, and in the embodiment of the present invention, the regularization method using a Kullback-L eibler difference is preferably used.
In order to ensure the quality of the image, in all the above procedures, data is stored in a floating point format, and all operations related to the image content are floating point calculations. There is no limit to the number of bits of the floating-point number.
Compared with the prior art, the invention has the beneficial effects that:
the invention provides a distributed image reconstruction system based on multiple FPGAs (field programmable gate arrays) and a medical image block reconstruction method based on the multiple FPGAs. The invention can realize the high-energy-efficiency reconstruction of XCT images with any size based on the multi-FPGA interconnection technology.
The invention can realize the high-energy-efficiency reconstruction of medical images (XCT images) with any size based on the multi-FPGA interconnection technology, can fully meet the requirements of the reconstruction of high-resolution images in the future and can obtain the high-energy-efficiency acceleration effect. At present, the multi-FPGA-based block image reconstruction technology which can reconstruct XCT images with any size is not available, and is the same as or similar to the multi-FPGA-based block image reconstruction technology. Compared with the existing XCT image reconstruction scheme, the present invention has the following advantages (including but not limited to):
A. before the complete calculation is finished, the data are all stored in the block RAM on the FPGA chip, so that the data transmission quantity is minimized;
B. all FPGA processing units can be executed without mutual interference, and have very high parallelism; meanwhile, as the dependency relationship between the data is eliminated, further asynchronous parallelism can be supported.
Drawings
FIG. 1 is a schematic diagram of a connection topology of a multi-FPGA-based distributed image reconstruction system according to an embodiment of the present invention;
the control unit is connected with the FPGA by adopting a PCI-e protocol; the FPGA processing units adopt VC707 development boards, and the FPGA processing units communicate with each other by adopting FMC XM 104.
FIG. 2 is a schematic diagram of the control unit of the system of the present invention;
FIG. 3 is a schematic diagram of an FPGA processing unit of the system of the present invention;
fig. 4 is a flow chart of an image block reconstruction method provided by the present invention.
FIG. 5 is a block diagram of an embodiment of the invention;
the side length of the whole image is N, and the side length of each small block is N/2; (a) an area managed by the FPGA processing unit 1; (b) an area managed by the FPGA processing unit 2; (c) an area managed by the FPGA processing unit 3; (d) an area managed by the FPGA processing unit 4.
FIG. 6 is a schematic representation of the reconstruction results of the present system;
wherein (a) is the image result of 10 iterations; (b) image results for 20 iterations; (c) image results for 50 iterations; (d) image segmentation results for 10 iterations; (e) image segmentation results for 20 iterations; (f) the image segmentation result is obtained by 50 times of iteration.
Detailed Description
The invention will be further described by way of examples, without in any way limiting the scope of the invention, with reference to the accompanying drawings.
The invention provides a multi-FPGA distributed image reconstruction system which comprises a control unit, a plurality of FPGA processing units and a connecting part, wherein the control unit is connected into a unified interconnection system, and the connecting part is used for connecting an FPGA. The system adopts a master-slave distributed structure with bus connection, and necessary connection exists between the FPGAs to assist necessary data exchange.
The control unit can be realized by software and hardware, and has the capabilities of scheduling and transmitting data. In particular, the control unit may be implemented by a general central processing unit, an embedded processor, or a soft processor on a certain FPGA, but not limited thereto. The control unit comprises a data sending module, a data receiving module, a command sending module, a response receiving module, an interconnection control module and a calculation synchronization module; specifically, the method comprises the following steps:
the data sending module is used for sending the image and the measurement data to the FPGA processing unit;
a data receiving module for obtaining data from the FPGA processing unit and measuring the data g in each iteration stageiUpdating of (1);
the command sending module drives different FPGA processing units in an iteration process;
the response receiving module is used for recording the running state of the FPGA processing unit;
the interconnection control module is used for connecting the control unit and the FPGA processing unit on a physical layer;
a calculation synchronization module for updating g after each iterationi。
One FPGA processing unit is served by one FPGA, and can also be born by a plurality of FPGAs through a FPGA dividing method. The FPGA processing unit comprises a data receiving module, a data transmission module and an interconnection control module; specifically, the method comprises the following steps:
the data receiving module is used for receiving the data sent from the control unit;
the data transmission module is used for sending data to the control unit and communicating with other FPGA processing units when necessary;
the interconnection control module is used for controlling the communication with other FPGAs;
when a plurality of computing units (PEs) exist in a single FPGA Processing unit, each PE has a necessary storage unit and a self-required computing module therein.
The invention uses the methods of dividing the image content, fitting the measured data and the like to improve the existing reconstruction algorithm and change the existing reconstruction algorithm into a new block reconstruction algorithm. The new reconstruction algorithm divides the image content f and the measurement data g; meanwhile, g needs to be solvediSelf-refresh is performed.
The image reconstruction can be optimized by adopting algorithms such as asynchronous parallel iterative acceleration, block image projection value iterative estimation and the like. Specifically, in the invention, the image reconstruction adopts the iterative estimation of block image projection values to giSelf-refresh is performed. The introduction of the block image projection value iterative estimation is mainly to modify the original general reconstruction algorithm into the block reconstruction algorithm according to the description of the invention. This approach divides both f and g. Thus, each FPGA processing unit only needs to maintain respective fiAnd gi. To ensure g managed by each FPGA processing unit during iterationiCan continue to pair fiProvides sufficient help for the managed giShould be as close as possible to the global g. The reconstruction algorithm described in the invention continuously updates g by self in the iterative solution processiThe sum of (a) approaches g. Methods for self-updating include least squares, regularization, orThe Kullback-L eibler difference regularization method and the like were used.
In this example, the self-update method is a regularization method using a Kullback-L eibler difference, which is specifically represented by formula 1:
in formula 1, gi' represents the updated f in each iterationiTemporary measurement data obtained by means of the R operator (matrix representation of the XCT image sampling model), i.e. gi′＝Rfi；giIs used to update the g needed for the next iterationi。
The purpose of the regularization method is to align all giGradually approaches to g in the solution.
In summary, the algorithm steps of the multi-FPGA medical image fast block reconstruction method provided by the present invention are as follows:
A. initializing image content f; the number of image blocks is m;
B. initializing blocking information fiSetting buffer areas for the boundaries of different blocks;
C. each f isiLoading the data into an FPGA processing unit;
D. and (3) iterative solution f:
D1. updating boundary buffers of each block (involving data transfer between FPGA processing units, requiring adjacent f's eachiTransmitting the respective boundary information to each other);
D2. using an asynchronous parallel iterative method according to fiAnd giUpdate each fiA value of (d);
D3. according to new fiUpdating g by using block image projection value iterative estimation methodi；
D4. If the data still does not converge, jump D1;
FPGA processing unit outputs respective result f to control uniti；
F. Control unit synthesis fiOutput nodeAnd f, fruits.
Fig. 4 is a flow chart of an image block reconstruction method provided by the present invention. Here, the number m of partitions may exceed the number of FPGA processing units. The number of FPGAs may not be sufficient to correspond to the number of many blocks, and thus a many-to-one relationship is certainly true. However, a calculation synchronization module of the control unit is needed to control the FPGA processing unit, and the redundant calculation tasks are completed in batches without breaking synchronization.
In order to ensure the quality of the image, in all the above procedures, data is stored in a floating point format, and all operations related to the image content are floating point calculations. The system is not limited with respect to the number of bits of the floating-point number.
In the following embodiments of the multi-FPGA distributed image reconstruction system, the control unit of the image reconstruction system is assumed to be performed by a processor (Intel Xeon E2650) of the workstation; the FPGA processing unit is filled by Xilinx VC 707; the control unit is connected with the FPGA processing unit by a PCIe interface; the connection between the FPGA processing units uses the SATA interface of FMC XM 104.
In a general XCT image reconstruction process, a user needs to acquire raw measurement data g to solve a real image f. In this example, a two-dimensional 512-sized image is used; the measurement data contains 180 sampled projections, each containing 768 detectors of information. In this embodiment, a multi-FPGA distributed image reconstruction system is established, an image is divided into 4 blocks, and 4 FPGA processing units are used to independently complete calculation. The structure of the whole system is shown in fig. 1, wherein 4 FPGA processing units are connected with a control unit through a bus, and the FPGA processing units are connected with each other through a SATA interface of FMC XM 104.
The data transmission part is a key part in the design of the FPGA hardware acceleration system. The FMC XM104 connection function card is designed to access 8 serial transceivers on the development on-board FMC HPC connector supported by the Xilinx FMC. These 8 serial transceivers may be accessed through 1 CX4(x4 transceiver), 2 SATA (x2 transceiver), and 8 SMA (x2 transceiver) connectors. The FPGA processing unit can carry out data transmission and communication through a PCIe interface of the VC707 and the control unit.
In this example, the user uses the processor of the workstation as the control unit. As shown in fig. 2, the control unit includes: the data sending module is used for sending the image and the measurement data to the FPGA processing unit; a data receiving module for acquiring data from the FPGA processing unit and performing block projection data g at each iteration stageiUpdating of (1); the command sending module drives different FPGA processing units in an iteration process; the response receiving module is used for recording the running state of the FPGA; the interconnection control module is used for connecting the control unit and the FPGA processing unit on a physical layer; a calculation synchronization module for updating g after each iterationi。
In this example, a Xilinx VC707FPGA is used as the FPGA processing unit therein. As shown in fig. 3, the FPGA processing unit includes: the data receiving module is used for receiving the data sent from the control unit; the data transmission module is used for sending data to the control unit and communicating with other FPGAs when necessary; the method comprises the following steps that a plurality of PEs exist in a single FPGA processing unit, and a necessary storage unit and a calculation module required by each PE are arranged in each PE; and the interconnection control module is used for controlling the communication with other FPGAs. These modules need to be pre-programmed and downloaded to the FPGA.
In this example, to ensure the quality of the reconstructed image, all data is stored in 32-bit floating point format; meanwhile, the calculation realized in the FPGA is floating point calculation so as to ensure the precision.
The reconstruction method is selected from many options for the system. The user can use a direct algebraic reconstruction method or use an iterative algorithm to solve. Wherein, the direct algebraic reconstruction method comprises an SART algorithm; iterative algorithms include the EM + TV algorithm (Expectation Maximization + Total Variation), the reconstruction algorithm of Mumford-Shah. To show the specific steps, how the Mumford-Shah model-based reconstruction method in the iterative algorithm is specifically applied to the system is described below. The formula of the Mumford-Shah model is:
where R represents a matrix representation of the sampling model of the XCT instrument, v represents a boundary indicator for indicating where the boundary of the image is located, the closer the value of v is to 0, the closer this position is to the boundary α, β, and kThe Mumford-Shah model has two empirical parameters, and a user can adjust the parameters according to actual conditions.
In this example, the user may use an optimization method such as a gradient descent method or a conjugate gradient to solve the objective function, which is expressed by equations 5 and 6:
in the iterative solution process, the user needs to use the two formulas to calculate the exploration direction in the solution space, and f and v are repeatedly updated.
In the FPGA processing unit, the whole computation part is divided into two large blocks: the device comprises a memory access module and a computing part. The memory access module is used for receiving memory access requests of the computing part and returning corresponding results from a block RAM of the FPGA processing unit; and the calculation part is used for calculating the Mumford-Shah model objective function. In the specific implementation of the FPGA, a user can streamline the two parts, so that the throughput is improved; at the same time, these two modules can be duplicated to achieve better parallel optimization within a single FPGA processing unit.
Next, it is described how the Mumford-Shah model can be modified to be applied to the present system according to the blocking concept described in the summary of the invention. Both f and g are partitioned in accordance with the block reconstruction algorithm described in the present invention. The division into a two-dimensional image is shown in fig. 5. Thus, each FPGA processing unit only needs to maintain respective fiAnd giIt is right. To guarantee f per FPGA processing unitiAnd giCan help it output an effective solution, g it managesiShould fit as best as g of the whole. In this example, all g's are normalized by solving equation 1iGradually approaches to g in the solution, thereby obtaining the solution.
After mathematical derivation, we can solve the following equation to guide giUpdate of
Fig. 4 is a flow chart of an image block reconstruction method provided by the present invention. And after the whole algorithm step is executed, outputting a result f. The final reconstruction results are shown in fig. 6, and after a sufficient number of iterations (results after 10, 20 and 50 iterations are shown in the figure), reasonably good reconstruction results are obtained. It can be seen that the blocking artifacts slowly cancel out after 20 iterations; the artifact has completely disappeared after 50 iterations. Meanwhile, all data are stored in the FPGA processing unit during calculation, so that the access cost is reduced to be negligible.
It is noted that the disclosed embodiments are intended to aid in further understanding of the invention, but those skilled in the art will appreciate that: various substitutions and modifications are possible without departing from the spirit and scope of the invention and appended claims. Therefore, the invention should not be limited to the embodiments disclosed, but the scope of the invention is defined by the appended claims.
Claims (10)
1. A medical image block reconstruction method based on multiple FPGAs utilizes a medical image block reconstruction system comprising a control unit, multiple FPGA processing units and a connecting component for connecting the FPGAs, wherein the control unit is connected to a unified internet, and image content f and measurement data g are divided into image blocks f respectively through image content division and measurement data fitting methodsiAnd measurement data block giWhile blocking the measurement data in the solution processiPerforming a self-update, thereby improving the existing image reconstruction method to a new block reconstruction method; the method comprises the following steps:
A. initializing image content f, image blocks fiThe number of (2) is m;
B. initializing block information for different blocks fiThe boundary of the buffer area is provided with a buffer area;
C. each block fiSequentially loading the data into corresponding FPGA processing units;
D. iteratively solving for the image content f by:
D1. adjacent each fiTransmitting the respective boundary information to each other, and updating the boundary buffer area of each block;
D2. using an asynchronous parallel iterative method according to fiAnd giUpdate each fiA value of (d);
D3. according to new fiUpdating g by using block image projection value iterative estimation methodi；
D4. If the data still does not converge, jump D1;
FPGA processing unit outputs respective result f to control uniti；
F. Control unit synthesis fiAnd outputting the result f.
2. The block reconstruction method according to claim 1, wherein the control unit includes a data transmission module, a data reception module, a command transmission module, a response reception module, an interconnection control module, and a calculation synchronization module; when the image is blocked by fiWhen the number m of the FPGA processing units exceeds the number of the FPGA processing units, the FPGA processing units are controlled through a calculation synchronization module of the control unit.
3. The block reconstruction method of claim 1, wherein the existing image reconstruction algorithm comprises an algebraic reconstruction method and an iterative algorithm.
4. The block reconstruction method according to claim 1, wherein the method for performing self-update is a regularization method of Kullback-L eibler difference.
5. A medical image block reconstruction system for realizing the block reconstruction method of any one of claims 1 to 4 comprises a control unit connected to a unified interconnection network, a plurality of FPGA processing units and a connecting component used for connecting an FPGA, and the system realizes high-energy-efficiency reconstruction of medical images of any size based on multi-FPGA interconnection.
6. The system of claim 5, wherein the interconnection network employs a bus-based master-slave distribution architecture.
7. The system of claim 5, wherein said control unit is implemented in software or hardware; the control unit is a central processing unit with the capability of scheduling and transmitting data, an embedded processor or a soft processor on an FPGA.
8. The system of claim 5, wherein the control unit comprises a data transmitting module, a data receiving module, a command transmitting module, a response receiving module, an interconnection control module and a calculation synchronization module; the data sending module is used for sending images and measurement data to the FPGA processing unit; the data receiving module acquires data from the FPGA processing unit and is used for measuring data g in each iteration stageiUpdating of (1); the command sending module is used for driving different FPGA processing units in an iteration process; the response receiving module is used for recording the running state of the FPGA processing unit; the interconnection control module is used for connecting the control unit and the FPGA processing unit on a physical layer; the calculation synchronization module updates the measurement data g of each iteration stage after each iteration is finishedi。
9. The system of claim 5, wherein said FPGA processing unit is an FPGA; or a plurality of FPGAs are used as the FPGA by an FPGA dividing method; the FPGA processing unit comprises a data receiving module, a data transmission module and an interconnection control module; the data receiving module is used for receiving data sent from the control unit; the data transmission module is used for sending data to the control unit and communicating with other FPGA processing units; and the interconnection control module is used for controlling the communication with other FPGAs.
10. A system as claimed in any one of claims 5 to 9, wherein when there are multiple compute units PE within a single FPGA processing unit, each PE includes internally a memory unit and a compute module.
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