CN107785303A - A kind of preparation method of SOI silicon substrate materials - Google Patents
A kind of preparation method of SOI silicon substrate materials Download PDFInfo
- Publication number
- CN107785303A CN107785303A CN201610786116.1A CN201610786116A CN107785303A CN 107785303 A CN107785303 A CN 107785303A CN 201610786116 A CN201610786116 A CN 201610786116A CN 107785303 A CN107785303 A CN 107785303A
- Authority
- CN
- China
- Prior art keywords
- silicon
- doping
- layer
- soi
- preparation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 81
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 80
- 239000010703 silicon Substances 0.000 title claims abstract description 80
- 239000000758 substrate Substances 0.000 title claims abstract description 63
- 238000002360 preparation method Methods 0.000 title claims abstract description 22
- 239000000463 material Substances 0.000 title claims abstract description 19
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 229920005591 polysilicon Polymers 0.000 claims abstract description 20
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 16
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 6
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- 239000003344 environmental pollutant Substances 0.000 claims description 5
- 231100000719 pollutant Toxicity 0.000 claims description 5
- 229910000077 silane Inorganic materials 0.000 claims description 5
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 claims description 5
- 239000005052 trichlorosilane Substances 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 4
- VXEGSRKPIUDPQT-UHFFFAOYSA-N 4-[4-(4-methoxyphenyl)piperazin-1-yl]aniline Chemical compound C1=CC(OC)=CC=C1N1CCN(C=2C=CC(N)=CC=2)CC1 VXEGSRKPIUDPQT-UHFFFAOYSA-N 0.000 claims description 3
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical group P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 3
- 229910000070 arsenic hydride Inorganic materials 0.000 claims description 3
- 229910000085 borane Inorganic materials 0.000 claims description 3
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 239000005049 silicon tetrachloride Substances 0.000 claims description 3
- UORVGPXVDQYIDP-UHFFFAOYSA-N trihydridoboron Substances B UORVGPXVDQYIDP-UHFFFAOYSA-N 0.000 claims description 3
- 238000010792 warming Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 2
- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical compound Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 claims description 2
- -1 silicon Alkane Chemical class 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- 239000000377 silicon dioxide Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 9
- 230000007547 defect Effects 0.000 description 3
- 125000004430 oxygen atom Chemical group O* 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 description 2
- 239000005046 Chlorosilane Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000012876 carrier material Substances 0.000 description 1
- KOPOQZFJUQMUML-UHFFFAOYSA-N chlorosilane Chemical compound Cl[SiH3] KOPOQZFJUQMUML-UHFFFAOYSA-N 0.000 description 1
- 238000009841 combustion method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Recrystallisation Techniques (AREA)
Abstract
The invention discloses a kind of preparation method of SOI silicon substrate materials, belong to the preparing technical field of SOI pieces.The backing material refers to the SOI silicon substrate films of the polysilicon layer with doping or the amorphous silicon layer of doping, and it is prepared as：(1) high resistant silicon chip is provided；(2) silicon oxide layer is prepared in high resistant silicon chip surface, the silicon oxide layer thickness is
Description
Technical field
The present invention relates to the preparing technical field of SOI pieces, and in particular to a kind of preparation method of SOI silicon substrate materials, institute
The silicon substrate of preparation is mainly used in radio-frequency apparatus.
Background technology
Material currently used for RF front end modules is as follows：
1st, SOQ (silicon on silicon on quartz quartz), SOS are (on silicon on sapphire sapphires
Silicon)：SOQ is identical with traditional SOI, and it produces relatively low leakage current, due to its relatively low parasitic capacitance, circuit performance under high frequency
It is improved.SOS advantage is its fabulous electrical insulating property, and it is attached can effectively to prevent that radiation caused by stray electrical current is diffused into
Nearly element.This kind of substrates of SOQ and SOS can obtain fabulous radio-frequency performance, but this structure is considerably less, therefore they are very high
It is expensive.
2nd, High resistivity substrate silicon：For its resistivity in more than 500ohm.cm, this substrate is poorer than the first, this substrate not by
Beneficial to SOI type structure advantages, but their costs are relatively low.
3rd, high resistant SOI substrate：This kind of substrate has structural advantage, but the performance showed is poorer than the first.
Forming a reason of conductive formation is：Because low-resistivity layer on the preceding surface of bonding there may be pollutant,
In bonding process, these pollutants are encapsulated in bonding interface and can be diffused into high resistivity substrate；It is another to form conductive formation
One reason is：Oxygen atom content is higher in substrate, it is necessary to is heat-treated, oxygen atom precipitation is obtained high-resistance substrate.
However, oxygen atom diffusion, heat treatment process cause the surface resistivity of formed substrate low.The two reasons are difficult to control at present
System.
4th, improve high resistant SOI substrate type substrate by adding defect layer on the basis of the third, it is conventional the defects of layer
Growth is natively readily incorporated impurity, influences the final performance of device.
The content of the invention
The purpose of the present invention is to be directed to weak point of the prior art, there is provided a kind of preparation side of SOI silicon substrate materials
Method, the film-substrate refer to the SOI substrate piece of polycrystalline or amorphous silicon layer with doping, the more of doping are quoted in SOI substrate piece
Brilliant or amorphous silicon layer, it enough can effectively suppress the surface parasitic conductance of silicon substrate, limiting capacitance with the effective binding energy of silica
The power of harmonic wave caused by change and reduction, so that the loss of high resistant SOI substrate resistivity minimizes.
To achieve the above object, the technical solution adopted in the present invention is as follows：
A kind of preparation method of SOI silicon substrate materials, the backing material refer to polysilicon layer or doping with doping
Amorphous silicon layer SOI silicon substrate films, its preparation method comprises the following steps：
(1) high resistant silicon chip is provided, is cleaned successively by DHF, SC1 and SC2, removes natural oxidizing layer and the pollution on surface
Thing, obtain the silicon chip surface of high quality；
(2) silicon oxide layer is prepared in high resistant silicon chip surface, the silicon oxide layer thickness is
(3) polysilicon layer of doping or the amorphous silicon layer of doping are prepared on silicon oxide layer surface, is obtained with the more of doping
The SOI silicon substrate films of crystal silicon layer or the amorphous silicon layer of doping.
In step (1), the resistivity of the high resistant silicon chip is more than 500ohm.cm.
In step (3), the thickness of the polysilicon layer or amorphous silicon layer is 1~5 μm, and resistivity is 1~100ohm.cm.
In step (3), the preparation process of the polysilicon layer of the doping or the amorphous silicon layer of doping is as follows：
(A) will grow silicon oxide layer High Resistivity Si piece load enclosed reaction chamber, reaction room pressure for 10torr~
760torr；
(B) 500~1000 DEG C of deposition temperature is warming up to, is passed through silicon source and doped source, deposits required polycrystalline or amorphous
Silicon layer, deposition time are 2min~30min；
(C) hydrogen is passed through in reative cell, after removing the impurity and residual gas body in reative cell, naturally cools to room temperature；
(D) nitrogen is passed through in reative cell, takes out silicon chip after removing hydrogen therein, that is, obtain the polysilicon layer with doping
Or the SOI silicon substrate films of the amorphous silicon layer of doping.
In step (B), the silicon source is silane (SiH4), trichlorosilane (SiHCl3), dichlorosilane (SiH2Cl2) or four
Silicon chloride (SiCl4)；If silicon source is silane or dichlorosilane, it is 50~150sccm to be passed through flow；If silicon source is trichlorine silicon
Alkane or tetrachloro silicane, it is 5~20g/min to be passed through flow.
In step (B), the doped source is p-type doped source or n-type doping source, and p-type doped source is double borine (B2H6), mix
Miscellaneous concentration is 1.30E+14~1.47E+16at/cm3；N-type doping source is phosphine (PH3) or arsine (AsH3), doping concentration is
4.32E+13~4.83E15at/cm3；The doping concentration refers to reach the foreign atom needed for target resistivity unit volume
Number.
The SOI silicon substrate materials that will be prepared using the above method, utilize " TM-SOI smart-cut method (application numbers
200310123080.1 and obtain Patent Office of the People's Republic of China's invention patent mandate.) " prepare SOI materials.Its main process is in two silicon
Among piece, one is square into oxide-film at least in, and wherein the silicon chip hydrogen ion injected above of a side or rare gas from
Son, so as to after the silicon chip is internally formed micro-bubble layer (ion implanted layer), make this to inject the face of ion across oxide-film
Be bonded another side silicon wafer, then annealed, make binding face firm, be then subject to microwave combustion method, using micro-bubble layer as
Splitting surface, the wafer film shape of a wherein side is peeled off, form SOI materials.
SOI substrate piece prepared by the present invention has advantages below：
The SOI pieces formed using the substrate slice prepared by the present invention have advantages below：
1st, the polysilicon layer of doping or the amorphous silicon layer of doping are combined with silica has the defects of higher density, more effectively
The surface parasitic conductance for inhibiting silicon substrate, limiting capacitance change and reduce caused by harmonic wave power.
2nd, the polysilicon layer of doping or the amorphous silicon layer of doping freeze carrier and silicon materials is turned into real high resistant.Reduce
The PSC (parasitic surface conductance) of high resistant SOI substrate.
3rd, the polysilicon layer of doping or the amorphous silicon layer high resistant SOI substrate of doping reduce RF substrate losses, increase substrate lines
Property characteristic, reduce DC voltage bias, it is and compatible with CMOS, reduce the loss of radio frequency.
Brief description of the drawings
Fig. 1 is the process chart that the present invention prepares SOI silicon substrates；In figure：(a) high resistant silicon chip；(b) silica is prepared
Layer；(c) polycrystalline of doping or the amorphous silicon layer of doping are prepared.
Fig. 2 is to carry out CPW (co-planar waveguide) test result to soi wafer in embodiment 1.
Fig. 3 is to carry out CPW (co-planar waveguide) test result to soi wafer in embodiment 2.
Embodiment
The present invention is described in detail below in conjunction with drawings and Examples.
In following examples, the preparation process of the polysilicon layer of the doping or the amorphous silicon layer of doping is as follows：
(A) will grow silicon oxide layer High Resistivity Si piece load enclosed reaction chamber, reaction room pressure for 10torr~
760torr；
(B) 500~1000 DEG C of deposition temperature is warming up to, is passed through silicon source and doped source, deposits required polycrystalline or amorphous
Silicon layer, deposition time are 2min~30min；In step (B), the silicon source is silane (SiH4), trichlorosilane (SiHCl3), two
Chlorosilane (SiH2Cl2) or silicon tetrachloride (SiCl4)；If silicon source is silane or dichlorosilane, be passed through flow for 50~
150sccm；If silicon source is trichlorosilane or tetrachloro silicane, it is 5~20g/min to be passed through flow.In step (B), the doping
Source is p-type doped source or n-type doping source, and p-type doped source is double borine (B2H6), doping concentration is 1.30E+14~1.47E+
16at/cm3；N-type doping source is phosphine (PH3) or arsine (AsH3), doping concentration is 4.32E+13~4.83E15at/cm3；Institute
State doping concentration and refer to reach foreign atom number needed for target resistivity unit volume.
(C) hydrogen is passed through in reative cell, after removing the impurity and residual gas body in reative cell, naturally cools to room temperature；
(D) nitrogen is passed through in reative cell, takes out silicon chip after removing hydrogen therein, that is, obtain the polysilicon layer with doping
Or the SOI silicon substrate films of the amorphous silicon layer of doping.
Embodiment 1：
The present embodiment provides a kind of preparation method of SOI silicon substrates, and the substrate refers to the polycrystalline or doping adulterated
The SOI substrate piece of amorphous silicon layer, its preparation comprise the following steps：
1st, provide high resistant silicon chip (silicon chip resistivity is more than 500ohm.cm), and to its surface successively use DHF, SC1 and
SC2 is cleaned, to remove silicon chip surface natural oxidizing layer and pollutant (Fig. 1 (a)).
2nd, with reference to figure 1 (b), silicon oxide layer, the oxidated layer thickness 200A of growth are prepared on the surface of high resistant silicon chip；
3rd, on the basis of Fig. 1 (b), the polysilicon layer (Fig. 1 (c)) of doping is prepared on silicon oxide layer, thickness is 2 μm,
Doping type is p-type, resistivity 1ohm.cm.
4th, the silicon substrate film formed using Fig. 1 (c), " TM-SOI smart-cuts method " is utilized to form SOI.
5th, CPW (co-planar waveguide) tests (Fig. 2) are carried out to soi wafer, it was demonstrated that use the soi wafer of silicon substrate film of the present invention
Soi wafer of the loss better than the manufacture of other substrates.
Embodiment 2：
The present embodiment provides a kind of preparation method of SOI silicon substrates, and the substrate refers to the polycrystalline or doping adulterated
The SOI substrate piece of amorphous silicon layer, its preparation comprise the following steps：
1st, provide high resistant silicon chip (silicon chip resistivity is more than 500ohm.cm), and to its surface successively use DHF, SC1 and
SC2 is cleaned, to remove silicon chip surface natural oxidizing layer and pollutant (Fig. 1 (a)).
2nd, with reference to figure 1 (b), silicon oxide layer, the oxidated layer thickness 200A of growth are prepared on the surface of high resistant silicon chip；
3rd, on the basis of Fig. 1 (b), the polysilicon layer (Fig. 1 (c)) of doping is prepared on silicon oxide layer, thickness is 2 μm,
Doping type is N-type, resistivity 10ohm.cm..
4th, the silicon substrate film formed using Fig. 1 (c), " TM-SOI smart-cuts method " is utilized to form SOI.
5th, CPW (co-planar waveguide) tests (Fig. 3) are carried out to soi wafer, it was demonstrated that use the soi wafer of silicon substrate film of the present invention
Soi wafer of the loss better than the manufacture of other substrates.
Claims (6)
- A kind of 1. preparation method of SOI silicon substrate materials, it is characterised in that：The backing material refers to the polysilicon with doping The SOI silicon substrate films of layer or the amorphous silicon layer of doping, its preparation method comprise the following steps：(1) high resistant silicon chip is provided, is cleaned successively by DHF, SC1 and SC2, is removed the natural oxidizing layer and pollutant on surface, obtain Obtain the silicon chip surface of high quality；(2) silicon oxide layer is prepared in high resistant silicon chip surface, the silicon oxide layer thickness is(3) polysilicon layer of doping or the amorphous silicon layer of doping are prepared on silicon oxide layer surface, obtains the polysilicon with doping The SOI silicon substrate films of layer or the amorphous silicon layer of doping.
- 2. the preparation method of SOI silicon substrate materials according to claim 1, it is characterised in that：In step (1), the height The resistivity of resistance silicon chip is more than 500ohm.cm.
- 3. the preparation method of SOI silicon substrate materials according to claim 1, it is characterised in that：It is described more in step (3) The thickness of crystal silicon layer or amorphous silicon layer is 1~5 μm, and resistivity is 1~100ohm.cm.
- 4. the preparation method of SOI silicon substrate materials according to claim 1, it is characterised in that：It is described to mix in step (3) Miscellaneous polysilicon layer or the preparation process of the amorphous silicon layer of doping are as follows：(A) will grow silicon oxide layer High Resistivity Si piece load enclosed reaction chamber, reaction room pressure for 10torr~ 760torr；(B) 500~1000 DEG C of deposition temperature is warming up to, is passed through silicon source and doped source, deposits required polycrystalline or amorphous silicon layer, Deposition time is 2min~30min；(C) hydrogen is passed through in reative cell, after removing the impurity and residual gas body in reative cell, naturally cools to room temperature；(D) nitrogen is passed through in reative cell, takes out silicon chip after removing hydrogen therein, that is, obtain the polysilicon layer with doping or mix The SOI silicon substrate films of miscellaneous amorphous silicon layer.
- 5. the preparation method of SOI silicon substrate materials according to claim 4, it is characterised in that：In step (B), the silicon Source is silane (SiH4), trichlorosilane (SiHCl3), dichlorosilane (SiH2Cl2) or silicon tetrachloride (SiCl4)；If silicon source is silicon Alkane or dichlorosilane, it is 50~150sccm to be passed through flow；If silicon source is trichlorosilane or tetrachloro silicane, be passed through flow for 5~ 20g/min。
- 6. the preparation method of SOI silicon substrate materials according to claim 4, it is characterised in that：It is described to mix in step (B) Miscellaneous source is p-type doped source or n-type doping source, and p-type doped source is double borine (B2H6), doping concentration is 1.30E+14~1.47E+ 16at/cm3；N-type doping source is phosphine (PH3) or arsine (AsH3), doping concentration is 4.32E+13~4.83E15at/cm3。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610786116.1A CN107785303A (en) | 2016-08-31 | 2016-08-31 | A kind of preparation method of SOI silicon substrate materials |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610786116.1A CN107785303A (en) | 2016-08-31 | 2016-08-31 | A kind of preparation method of SOI silicon substrate materials |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107785303A true CN107785303A (en) | 2018-03-09 |
Family
ID=61451073
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610786116.1A Pending CN107785303A (en) | 2016-08-31 | 2016-08-31 | A kind of preparation method of SOI silicon substrate materials |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107785303A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113437016A (en) * | 2021-06-25 | 2021-09-24 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090283854A1 (en) * | 2008-05-19 | 2009-11-19 | Levy Max G | Design Structure and Method for Buried Inductors for Ultra-High Resistivity Wafers for SOI/RF SIGE Applications |
| CN103460371A (en) * | 2011-03-22 | 2013-12-18 | Soitec公司 | Manufacturing method for asemiconductor on insulator type substrate for radiofrequency applications |
-
2016
- 2016-08-31 CN CN201610786116.1A patent/CN107785303A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090283854A1 (en) * | 2008-05-19 | 2009-11-19 | Levy Max G | Design Structure and Method for Buried Inductors for Ultra-High Resistivity Wafers for SOI/RF SIGE Applications |
| CN103460371A (en) * | 2011-03-22 | 2013-12-18 | Soitec公司 | Manufacturing method for asemiconductor on insulator type substrate for radiofrequency applications |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113437016A (en) * | 2021-06-25 | 2021-09-24 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102640278B (en) | Method for manufacturing a semiconductor-on-insulator structure having low electrical losses, and corresponding structure | |
| JP5726796B2 (en) | Method of manufacturing a base substrate for a semiconductor-type substrate on an insulator | |
| CN103038863A (en) | Oxygen plasma conversion process for preparing a surface for bonding | |
| CN101207009B (en) | Method for manufacturing an SOI substrate | |
| CN102383198B (en) | Three-step variable-temperature diffusion process for silicon cell | |
| CN107785302A (en) | The preparation method and SOI materials of a kind of SOI silicon substrate materials | |
| CN107408532A (en) | Thermostabilization electric charge capture layer for the manufacture of semiconductor-on-insulator structure | |
| US9230849B2 (en) | Method for preparing ultra-thin material on insulator through adsorption by doped ultra-thin layer | |
| TW201703105A (en) | Bonded semiconductor wafer and method for manufacturing bonded semiconductor wafer | |
| US9824891B1 (en) | Method of manufacturing the thin film | |
| CN101179014A (en) | Method for manufacturing semiconductor substrate | |
| CN114975085A (en) | Radio frequency silicon on insulator structure with superior performance, stability and manufacturability | |
| CN102130211B (en) | Method for improving surface diffusion of solar cell | |
| WO2010060673A1 (en) | Thick epitaxial silicon by grain reorientation annealing and applications thereof | |
| CN101188190A (en) | SOQ substrate and method of manufacturing SOQ substrate | |
| CN107785303A (en) | A kind of preparation method of SOI silicon substrate materials | |
| CN112144117B (en) | Hydrogen, phosphorus and nitrogen doped monocrystalline silicon, preparation method thereof and solar cell | |
| CN110600366B (en) | (100) Crystal orientation diamond n-channel junction field effect transistor and preparation method thereof | |
| CN101179054B (en) | SOQ substrate , and method for manufacturing SOQ substrate | |
| CN102790007A (en) | Method for preparing TM-SOI (Thick-Membrane Silicon-On-Insulator) silicon chip | |
| CN111416011A (en) | P-type PERC crystalline silicon solar cell and preparation method thereof | |
| CN114188362A (en) | SOI (silicon on insulator) with special structure and preparation method thereof | |
| CN115425073A (en) | Semiconductor device and manufacturing method thereof | |
| US20080242067A1 (en) | Semiconductor substrate and method of manufacture thereof | |
| CN110085509B (en) | Preparation method of uniform thick film SOI (silicon on insulator) silicon chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180309 |