CN107785271A - The forming method of semiconductor devices - Google Patents
The forming method of semiconductor devices Download PDFInfo
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- CN107785271A CN107785271A CN201610786851.2A CN201610786851A CN107785271A CN 107785271 A CN107785271 A CN 107785271A CN 201610786851 A CN201610786851 A CN 201610786851A CN 107785271 A CN107785271 A CN 107785271A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 83
- 238000000034 method Methods 0.000 title claims abstract description 74
- 239000011248 coating agent Substances 0.000 claims abstract description 79
- 238000000576 coating method Methods 0.000 claims abstract description 79
- 238000009792 diffusion process Methods 0.000 claims abstract description 71
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000000137 annealing Methods 0.000 claims abstract description 25
- 239000007787 solid Substances 0.000 claims abstract description 20
- 239000000463 material Substances 0.000 claims description 23
- 238000002513 implantation Methods 0.000 claims description 20
- 229910052796 boron Inorganic materials 0.000 claims description 15
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 230000005669 field effect Effects 0.000 claims description 10
- 239000007943 implant Substances 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 9
- 229910052757 nitrogen Inorganic materials 0.000 claims description 7
- 229910052799 carbon Inorganic materials 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 3
- 238000005137 deposition process Methods 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 229910001449 indium ion Inorganic materials 0.000 claims description 3
- 229920000620 organic polymer Polymers 0.000 claims description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims 1
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- 229910052698 phosphorus Inorganic materials 0.000 claims 1
- 239000011574 phosphorus Substances 0.000 claims 1
- 150000002500 ions Chemical class 0.000 description 88
- -1 boron ion Chemical class 0.000 description 22
- 230000008569 process Effects 0.000 description 14
- 230000004888 barrier function Effects 0.000 description 8
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 239000012530 fluid Substances 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000005764 inhibitory process Effects 0.000 description 2
- 230000035755 proliferation Effects 0.000 description 2
- 239000011435 rock Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of forming method of semiconductor devices, including：Semiconductor substrate is provided, the semiconductor substrate surface has fin；Diffusion layer is formed on the surface of the fin, there is anti-break-through ion in the diffusion layer；Coating is formed in the diffusion layer surface, solid solubility of the anti-break-through ion in coating is less than the solid solubility in diffusion layer；The sacrifice layer of covering part coating is formed on a semiconductor substrate, and the surface of the sacrifice layer is less than the top surface of fin；After removing diffusion layer and coating higher than sacrificial layer surface, made annealing treatment, anti-break-through ion is entered in fin.The forming method of the semiconductor devices causes the concentration of anti-break-through ion in fin to increase, so as to enhance anti-break-through ability.Reduce cost simultaneously.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of forming method of semiconductor devices.
Background technology
MOS transistor is one of most important element in modern integrated circuits.The basic structure of MOS transistor includes：Half
Conductor substrate；Positioned at the grid structure of semiconductor substrate surface, source region and position in the Semiconductor substrate of grid structure side
Drain region in grid structure opposite side Semiconductor substrate.The operation principle of MOS transistor is：By applying electricity in grid structure
Pressure, is adjusted by the electric current of grid structure bottom channel to produce switching signal.
With the development of semiconductor technology, the MOS transistor of traditional plane formula dies down to the control ability of channel current,
Cause serious leakage current.And fin formula field effect transistor (Fin FET) is a kind of emerging multi-gate device, protrusion is generally comprised
In the fin of semiconductor substrate surface, the top surface of fin described in covering part and the grid structure of sidewall surfaces, positioned at grid
Source region in the fin of pole structure side and the drain region in the fin of grid structure opposite side.
In order to further reduce influence of the short-channel effect to semiconductor devices, channel leakage stream is reduced.A kind of method is
Doped with anti-break-through ion, the possibility of reduction drain-source break-through, so as to reduce short-channel effect in fin bottom.
But in the prior art, it is impossible to reach：In increase fin cost is reduced while the concentration of anti-break-through ion.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of forming method of semiconductor devices so that anti-break-through ion in fin
Concentration increase, so as to enhance anti-break-through ability, while reduces cost.
To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, including：Semiconductor lining is provided
Bottom, the semiconductor substrate surface have fin；Diffusion layer is formed on the surface of the fin, there is anti-wear in the diffusion layer
Logical ion；Coating is formed in the diffusion layer surface, solid solubility of the anti-break-through ion in coating, which is less than, to spread
Solid solubility in layer；The sacrifice layer of covering part coating is formed on a semiconductor substrate, and the surface of the sacrifice layer is less than fin
The top surface in portion；After removing diffusion layer and coating higher than sacrificial layer surface, made annealing treatment, enter anti-break-through ion
Enter in fin.
Optionally, the material of the diffusion layer is the silica containing anti-break-through ion.
Optionally, when the semiconductor devices is N-type fin formula field effect transistor, the type of the anti-break-through ion is
P-type.
Optionally, the anti-break-through ion is boron ion, BF- 2Ion or indium ion.
Optionally, when the semiconductor devices is p-type fin formula field effect transistor, the type of the anti-break-through ion is
N-type.
Optionally, the anti-break-through ion is phosphonium ion or arsenic ion.
Optionally, the material of the coating is silicon nitride or the non-crystalline silicon doped with gap ion.
Optionally, when the material of the coating is silicon nitride, the technique for forming the coating is ald
Technique, plasma activated chemical vapour deposition technique, low-pressure chemical vapor deposition process or sub-atmospheric pressure chemical vapor deposition work
Skill.
Optionally, when the material of the coating is the non-crystalline silicon doped with gap ion, the coating is formed
Method includes：Cover layer is formed in diffusion layer surface；Gap ion is injected in the cover layer using ion implantation technology, from
And form coating.
Optionally, the gap ion is carbon ion or Nitrogen ion.
Optionally, when the gap ion is carbon ion, the parameter of the ion implantation technology includes：Implantation Energy is
0.5KeV~20KeV, implantation dosage 1.0E13atom/cm2~1.0E16atom/cm2, implant angle is 7 degree~20 degree.
Optionally, when the gap ion is Nitrogen ion, the parameter of the ion implantation technology includes：Implantation Energy is
0.5KeV~15KeV, implantation dosage 1.0E13atom/cm2~1.0E16atom/cm2, implant angle is 7 degree~20 degree.
Optionally, when the material of the coating is the non-crystalline silicon doped with gap ion, the gap ion is being covered
Atomic percent in cap rock is 1%~10%.
Optionally, the thickness of the coating is 10 angstroms~40 angstroms.
Optionally, the material of the sacrifice layer is bottom anti-reflection layer or organic polymer layers.
Optionally, forming the method for the sacrifice layer includes：Form the sacrifice for covering the coating and Semiconductor substrate
Layer；The sacrifice layer is etched back to, the surface of sacrifice layer is less than the top surface of fin.
Optionally, after diffusion layer and coating higher than sacrificial layer surface is removed, and before being made annealing treatment, also wrap
Include：Remove the sacrifice layer.
Optionally, the parameter of the annealing includes：The gas of use includes N2, annealing temperature be 800 degrees Celsius~
1100 degrees Celsius.
Compared with prior art, technical scheme has advantages below：
The forming method of semiconductor devices provided by the invention, due to forming coating on the surface of diffusion layer, and it is described
Solid solubility of the anti-break-through ion in coating is less than solid solubility in diffusion layer, hence in so that coating accommodate anti-break-through from
The ability of son is weaker than the ability that diffusion layer accommodates anti-break-through ion.Therefore anti-break-through ion in annealing process from diffusion layer
The degree overflowed to coating is smaller.And then the coating is enabled to reduce in diffusion layer anti-break-through ion outwardly environment
The degree of spilling.Therefore more anti-break-through ion diffuses into fin, so as to enhance anti-break-through ability.In addition, by
Enter in more anti-break-through ion in fin, improve the utilization rate of anti-break-through ion in diffusion layer, therefore need not to expand
The concentration for dissipating the anti-break-through ion of layer is higher so that process costs reduce.
Brief description of the drawings
Fig. 1 to Fig. 7 is the structural representation of semiconductor devices forming process in one embodiment of the invention.
Embodiment
As described in background, the semiconductor devices that prior art is formed can not reach：Increase fin in anti-break-through from
Cost is reduced while the concentration of son.
A kind of forming method of semiconductor devices, including：Semiconductor substrate is provided, the semiconductor substrate surface has fin
Portion；The silicon oxide layer containing boron ion is formed in the semiconductor substrate surface and fin portion surface；On the semiconductor substrate
The sacrifice layer of covering part diffusion layer is formed, the surface of the sacrifice layer is less than the top surface of fin；Remove the sacrifice layer
The diffusion layer exposed；Then made annealing treatment, the boron ion is diffused into fin.
However, in the above method, because the silicon oxide layer containing boron ion is in the atmosphere of annealing, therefore lead
Causing part boron ion, easily outwardly environment overflows, and is reduced so as to cause to diffuse into the boron ion in fin.So as to drop
Low anti-break-through ability.In order to strengthen the anti-break-through ability of semiconductor devices, it is necessary to make up the damage of the boron ion in annealing
Consumption, it is therefore desirable to the concentration of boron ion in silicon oxide layer of the increase containing boron ion.And increase the silica containing boron ion
The concentration of boron ion, will cause the increase of process costs in layer.
On this basis, the present invention provides a kind of forming method of semiconductor devices, including：Semiconductor substrate, institute are provided
Stating semiconductor substrate surface has fin；Form diffusion layer on the surface of the fin, have in the diffusion layer anti-break-through from
Son；Coating is formed in the diffusion layer surface, solid solubility of the anti-break-through ion in coating is less than in diffusion layer
Solid solubility；The sacrifice layer of covering part coating is formed on a semiconductor substrate, and the surface of the sacrifice layer is less than fin
Top surface；After removing diffusion layer and coating higher than sacrificial layer surface, made annealing treatment, anti-break-through ion is entered fin
In portion.
Due to forming coating on the surface of diffusion layer, and solid solubility of the anti-break-through ion in coating is less than
Solid solubility in diffusion layer, hence in so that the ability that coating accommodates anti-break-through ion is weaker than the anti-break-through ion of diffusion layer receiving
Ability.Therefore the degree that anti-break-through ion overflows in annealing process from diffusion layer to coating is smaller.And then cause institute
The anti-break-through ion degree that outwardly environment overflows in diffusion layer can be reduced by stating coating.Therefore there is more anti-break-through ion
Diffuse into fin, so as to enhance anti-break-through ability.Further, since more anti-break-through ion enters in fin, improve
The utilization rate of anti-break-through ion in diffusion layer, therefore need not make it that the concentration of the anti-break-through ion of diffusion layer is higher so that work
Skill cost reduces.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 1 to Fig. 7 is the structural representation of semiconductor devices forming process in one embodiment of the invention.
With reference to figure 1, there is provided Semiconductor substrate 100, the surface of Semiconductor substrate 100 have fin 110.
The Semiconductor substrate 100 provides technique platform to be subsequently formed semiconductor devices.
In the present embodiment, the material of the Semiconductor substrate 100 is monocrystalline silicon.The Semiconductor substrate 100 can also be
Polysilicon or non-crystalline silicon.The material of the Semiconductor substrate 100 can also be the semi-conducting materials such as germanium, SiGe, GaAs.
In the present embodiment, the fin 110 is formed by the graphical Semiconductor substrate 100.In other embodiments
In, Ke Yishi：Fin material layer is formed in the semiconductor substrate surface；The graphical fin material layer, so as to form fin
Portion.
The forming method of the Semiconductor substrate can also include：Round and smooth processing is carried out to the fin 110 so that fin
The curvature of 110 sharp corner reduces.It is subsequently formed after the grid structure of fin 110, avoids the internal field of fin 110 excessive
And puncture.
The method of the round and smooth processing includes：The surface of fin 110 is aoxidized, oxygen is formed on the surface of fin 110
Change layer；Remove the oxide layer.
Then, with reference to figure 2, diffusion layer 120 is formed on the surface of the fin 110, there is anti-wear in the diffusion layer 120
Logical ion.
In the present embodiment, round and smooth processing is not carried out to fin 110.In other embodiments, round and smooth place is carried out to fin
After reason, diffusion layer is formed on the surface of the fin.
The material of the diffusion layer 120 is the silica containing anti-break-through ion.
When the semiconductor devices is N-type fin formula field effect transistor, the type of the anti-break-through ion is p-type, such as
Boron ion, BF- 2Ion or indium ion.
When the semiconductor devices is p-type fin formula field effect transistor, the type of the anti-break-through ion is N-type, such as
Phosphonium ion or arsenic ion.
In the present embodiment, using the semiconductor devices as N-type fin formula field effect transistor, the anti-break-through ion be boron from
Illustrated exemplified by son.
Specifically, using depositing operation, as plasma activated chemical vapour deposition technique, low-pressure chemical vapor deposition process,
Sub-atmospheric pressure chemical vapor deposition method or atom layer deposition process, on the surface of Semiconductor substrate 100 and the surface shape of fin 110
Into diffusion layer 120, there is anti-break-through ion in the diffusion layer 120.
In the present embodiment, the semiconductor devices is N-type fin formula field effect transistor, and the diffusion layer 120 is to contain boron
The silica of ion.
If non-proliferation ion concentration in diffusion layer 120 is excessive, cause process costs higher；If the non-proliferation from
Concentration of the son in diffusion layer 120 is too small, causes have less anti-break-through ion diffusion to carry out fin during subsequent anneal
In 110.Therefore in the present embodiment, concentration of the anti-break-through ion in diffusion layer 120 is 1.0E19atom/cm3~
5.0E22atom/cm3。
With reference to figure 3, coating 130 is formed on the surface of diffusion layer 120, the anti-break-through ion is in coating 130
Solid solubility be less than solid solubility in diffusion layer 120.
The material of the coating 130 is silicon nitride or the non-crystalline silicon containing gap ion.
Gap ion is filled in the gap between the silicon atom of non-crystalline silicon so that in the non-crystalline silicon containing gap ion
Interatomic gap is smaller.Anti- break-through ion in diffusion layer 120 be difficult to by interatomic gap it is less containing gap from
The non-crystalline silicon of son.So that solid solubility of the anti-break-through ion in coating 130 is less than the solid solubility in diffusion layer 120.
The gap ion is carbon ion or Nitrogen ion.
In the present embodiment, the material of the coating is the non-crystalline silicon doped with gap ion.Accordingly, covered described in formation
The method of cap rock includes：Cover layer is formed in diffusion layer surface；Gap is injected in the cover layer using ion implantation technology
Ion, so as to form coating.
The material of the cover layer is non-crystalline silicon.The technique for forming the cover layer is depositing operation, such as plasmarized
Learn gas-phase deposition, sub-atmospheric pressure chemical vapor deposition method, low-pressure chemical vapor deposition process or ald work
Skill.
If the Implantation Energy of the ion implanting is excessive, cause the depth of injection larger, so as to cause the gap of majority
For ion implanting into diffusion layer 120 and fin 110, the gap ion being injected into coating 130 is less.Therefore can reduce rear
Coating 130 reduces to the inhibition of the anti-break-through ion in diffusion layer 120 in continuous annealing.If the ion implanting
Implantation Energy is too small, causes the depth of injection smaller, so as to cause to be injected into the cover layer of segment thickness, to the profit of cover layer
It is smaller with degree.
If the implantation dosage of the ion implanting is excessive, cause the increase of process costs, and add the difficulty of technique realization
Degree.If the implantation dosage of the ion implanting is too small, causes mass percent concentration of the gap ion in coating to reduce, lead
The coating 130 in subsequent anneal processing is caused to reduce the inhibition of the anti-break-through ion in diffusion layer 120.
In the case where injection depth is certain, the implant angle is relevant with Implantation Energy.The implant angle refers to
The angle formed between Semiconductor substrate normal direction.Implantation Energy is bigger, injection depth it is certain in the case of, it is necessary to
Implant angle is bigger；Implantation Energy is smaller, injection depth it is certain in the case of, it is necessary to implant angle it is smaller.
To sum up, the parameter of the ion implantation technology needs to select suitable scope.And corresponding to different gap ions
Atomic mass is different.In the case where identical injects depth, the larger gap ion of atomic mass need the energy that loses compared with
Greatly, therefore larger Implantation Energy is needed.
When the gap ion is carbon ion, the parameter of the ion implantation technology includes：Implantation Energy is 0.5KeV
~20KeV, implantation dosage 1.0E13atom/cm2~1.0E16atom/cm2, implant angle is 7 degree~20 degree.
When the gap ion is Nitrogen ion, the parameter of the ion implantation technology includes：Implantation Energy is 0.5KeV
~15KeV, implantation dosage 1.0E13atom/cm2~1.0E16atom/cm2, implant angle is 7 degree~20 degree.
When the material of the coating 130 is the non-crystalline silicon doped with gap ion, gap ion is in coating 130
Mass percent concentration more than 1% so that solid solubility of the anti-break-through ion in coating 130 be less than in diffusion layer
Solid solubility in 120.Mass percent concentration of the gap ion in coating 130 is below 10% so that process costs drop
It is low.
When the material of the coating 130 is silicon nitride, the technique for forming the coating 130 is depositing operation, such as
Atom layer deposition process, plasma activated chemical vapour deposition technique, low-pressure chemical vapor deposition process or sub-atmospheric pressure chemistry
Gas-phase deposition.
The thickness of the coating 130 needs to select suitable scope.If the thickness of the coating 130 is excessively thin, cause
Anti- break-through ion easily propagates through relatively thin coating 130 and volatilized away.If after the thickness of the coating 130, cause technique
Cost increase.Therefore in the present embodiment, the thickness of the coating 130 is 10 angstroms~40 angstroms.
With reference to the sacrifice layer 140 of figure 4, on a semiconductor substrate 100 formation covering part coating 130, the sacrifice layer
140 surface is less than the top surface of fin 110.
The material of the sacrifice layer 140 is bottom anti-reflection layer or organic polymer layers.
Forming the method for the sacrifice layer 140 includes：Formed and cover the sacrificial of the coating 130 and Semiconductor substrate 100
Domestic animal layer 140；The sacrifice layer 140 is etched back to, the surface of sacrifice layer 140 is less than the top surface of fin 110.
With reference to figure 5, the diffusion layer 120 and coating 130 higher than the surface of sacrifice layer 140 are removed.
It is dry carving technology or wet etching work to remove higher than the diffusion layer 120 on the surface of sacrifice layer 140 and the method for coating 130
Skill.
With reference to figure 6, remove the sacrifice layer 140 (with reference to figure 5).
The method for removing the sacrifice layer 140 is dry carving technology or wet-etching technique.
With reference to figure 7, after removing the sacrifice layer 140 (with reference to figure 5), made annealing treatment, diffuse into anti-break-through ion
Enter in fin 110.
The parameter of the annealing includes：The gas of use includes N2, annealing temperature is 800 degrees Celsius~1100 Celsius
Degree.
It should be noted that when adjacent fin 110 is used for the type difference of the fin formula field effect transistor of formation, phase
The type of anti-break-through ion in the diffusion layer 120 on the adjacent surface of fin 110 is opposite.In the case, in the present embodiment, institute is removed
After stating sacrifice layer 140, made annealing treatment so that the anti-break-through ion in the diffusion layer on the surface of fin 110 will not be by adjacent
Sacrifice layer 140 between fin 110 enters adjacent fin 110.
In other embodiments or：After removing diffusion layer and coating higher than sacrificial layer surface, annealed
Processing；After being made annealing treatment, the sacrifice layer is removed.
Solid solubility of the anti-break-through ion in coating 130 is less than the solid solubility in diffusion layer 120, hence in so that
The ability that coating 130 accommodates anti-break-through ion is weaker than the ability that diffusion layer 120 accommodates anti-break-through ion.Therefore anti-break-through ion
The degree overflowed in annealing process from diffusion layer 120 to coating 130 is smaller.And then enable the coating 130
Enough reduce the anti-break-through ion degree that outwardly environment overflows in diffusion layer 120.Therefore more anti-break-through ion diffuses into
Enter in fin 110, so as to enhance anti-break-through ability.Further, since more anti-break-through ion enters in fin 110, improve
The utilization rate of anti-break-through ion in diffusion layer, therefore need not make it that the concentration of the anti-break-through ion of diffusion layer is higher so that work
Skill cost reduces.
Then, isolation structure is formed on a semiconductor substrate 100, and the surface of the isolation structure is less than the top table of fin
Face 110.
Forming the method for isolation structure includes：The barrier film of covering coating is formed on the semiconductor substrate, it is described
The whole surface of barrier film is higher than the top surface of fin；Remove the barrier film higher than fin top surface；Then it is etched back to institute
Barrier film is stated, forms isolation structure, the surface of the isolation structure is less than the top surface of fin.
The technique for forming the barrier film is depositing operation, such as fluid chemistry gas-phase deposition.
The method of barrier film is formed using fluid chemistry gas-phase deposition to be included：Formed and covered on the semiconductor substrate
The buffer fluid layer of lid coating；Steam annealing is carried out, the buffer fluid layer is formed barrier film.
It should be noted that the annealing can be one of single technique.It can also utilize and form barrier film
During use steam annealing, anti-break-through ion is diffused into fin 110.
Then, it is developed across the grid structure of the fin 110；Formed in the fin 110 of the grid structure both sides
Source and drain doping area.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (18)
- A kind of 1. forming method of semiconductor devices, it is characterised in that including：Semiconductor substrate is provided, the semiconductor substrate surface has fin；Diffusion layer is formed on the surface of the fin, there is anti-break-through ion in the diffusion layer；Coating is formed in the diffusion layer surface, solid solubility of the anti-break-through ion in coating is less than in diffusion layer Solid solubility；The sacrifice layer of covering part coating is formed on a semiconductor substrate, and the surface of the sacrifice layer is less than the top table of fin Face；After removing diffusion layer and coating higher than sacrificial layer surface, made annealing treatment, anti-break-through ion is entered in fin.
- 2. the forming method of semiconductor devices according to claim 1, it is characterised in that the material of the diffusion layer be containing There is the silica of anti-break-through ion.
- 3. the forming method of semiconductor devices according to claim 1, it is characterised in that when the semiconductor devices is N During type fin formula field effect transistor, the type of the anti-break-through ion is p-type.
- 4. the forming method of semiconductor devices according to claim 3, it is characterised in that the anti-break-through ion be boron from Son, BF- 2Ion or indium ion.
- 5. the forming method of semiconductor devices according to claim 1, it is characterised in that when the semiconductor devices is P During type fin formula field effect transistor, the type of the anti-break-through ion is N-type.
- 6. the forming method of semiconductor devices according to claim 5, it is characterised in that the anti-break-through ion be phosphorus from Son or arsenic ion.
- 7. the forming method of semiconductor devices according to claim 1, it is characterised in that the material of the coating is nitrogen SiClx or the non-crystalline silicon doped with gap ion.
- 8. the forming method of semiconductor devices according to claim 7, it is characterised in that when the material of the coating is During silicon nitride, the technique for forming the coating is atom layer deposition process, plasma activated chemical vapour deposition technique, low pressure Learn gas-phase deposition or sub-atmospheric pressure chemical vapor deposition method.
- 9. the forming method of semiconductor devices according to claim 7, it is characterised in that when the material of the coating is Doped with gap ion non-crystalline silicon when, forming the method for the coating includes：Cover layer is formed in diffusion layer surface；Using Ion implantation technology injects gap ion in the cover layer, so as to form coating.
- 10. the forming method of semiconductor devices according to claim 9, it is characterised in that the gap ion be carbon from Son or Nitrogen ion.
- 11. the forming method of semiconductor devices according to claim 10, it is characterised in that when the gap ion is carbon During ion, the parameter of the ion implantation technology includes：Implantation Energy is 0.5KeV~20KeV, and implantation dosage is 1.0E13atom/cm2~1.0E16atom/cm2, implant angle is 7 degree~20 degree.
- 12. the forming method of semiconductor devices according to claim 10, it is characterised in that when the gap ion is nitrogen During ion, the parameter of the ion implantation technology includes：Implantation Energy is 0.5KeV~15KeV, and implantation dosage is 1.0E13atom/cm2~1.0E16atom/cm2, implant angle is 7 degree~20 degree.
- 13. the forming method of semiconductor devices according to claim 7, it is characterised in that when the material of the coating During for doped with the non-crystalline silicon of gap ion, atomic percent of the gap ion in coating is 1%~10%.
- 14. the forming method of semiconductor devices according to claim 1, it is characterised in that the thickness of the coating is 10 angstroms~40 angstroms.
- 15. the forming method of semiconductor devices according to claim 1, it is characterised in that the material of the sacrifice layer is Bottom anti-reflection layer or organic polymer layers.
- 16. the forming method of semiconductor devices according to claim 1, it is characterised in that form the side of the sacrifice layer Method includes：Form the sacrifice layer for covering the coating and Semiconductor substrate；The sacrifice layer is etched back to, makes the surface of sacrifice layer Less than the top surface of fin.
- 17. the forming method of semiconductor devices according to claim 1, it is characterised in that be higher than sacrifice layer table removing After the diffusion layer and coating in face, and before being made annealing treatment, in addition to：Remove the sacrifice layer.
- 18. the forming method of semiconductor devices according to claim 1, it is characterised in that the parameter of the annealing Including：The gas of use includes N2, annealing temperature is 800 degrees Celsius~1100 degrees Celsius.
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| KR20090079729A (en) * | 2008-01-18 | 2009-07-22 | 주식회사 하이닉스반도체 | Method of manufacturing MOSET device |
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Application publication date: 20180309 |