CN107771372A - System including multi-wafer power model, the method for operation for controlling multi-wafer power model, the device of operation for controlling multi-wafer power model - Google Patents
System including multi-wafer power model, the method for operation for controlling multi-wafer power model, the device of operation for controlling multi-wafer power model Download PDFInfo
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- CN107771372A CN107771372A CN201680033603.9A CN201680033603A CN107771372A CN 107771372 A CN107771372 A CN 107771372A CN 201680033603 A CN201680033603 A CN 201680033603A CN 107771372 A CN107771372 A CN 107771372A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/12—Modifications for increasing the maximum permissible switched current
- H03K17/122—Modifications for increasing the maximum permissible switched current in field-effect transistor switches
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K2017/0806—Modifications for protecting switching circuit against overcurrent or overvoltage against excessive temperature
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Power Conversion In General (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
- Inverter Devices (AREA)
- Electronic Switches (AREA)
Abstract
The present invention relates to a kind of system, the system includes：The multi-wafer power model being made up of chip；And controller, the controller receive multiple continuous input patterns of the chip for starting multi-wafer power model.Chip is grouped into multiple clusters of chip, and controller includes being used for the unit that a grid source signal is exported for each cluster of chip, each output grid source signal is different from other grid source signals, and the startup of chip is reduced during at least one input pattern of the grid source signal of at least one first output in multiple input patterns.
Description
Technical field
This patent disclosure relates generally to the system and method for the operation for controlling multi-wafer power model.
Background technology
Multi-wafer power model is traditionally made up of multiple power dies being connected in parallel, and for current capacity to be carried
A height of current capacity more than single power die.
For example, three-phase transverter is made up of four power dies in parallel of each switch, this provides 24 work(altogether
Rate chip.
Emerging device technique, such as SiC (carborundum) and GaN (gallium nitride) transistor, are typically due to wafer substrate
The limitation of yield and cost and realized in high current density, small-power chip.
In order to realize the module based on SiC of higher-wattage, it is necessary to be largely connected in parallel SiC wafer.With parallel connection even
The module connect is different, and the chip being connected in parallel is formed ideally to the single switch of same load current commutation.
The content of the invention
Technical problem
However, the type regardless of used crystal chip, i.e. diode or voltage-driven switch, for example, (metal aoxidizes MOSFET
Thing semiconductor field effect transistor), all exist in chip statically and dynamically limit the spy that the balance of load current is shared
Property.
In addition, the temperature of each chip in multi-wafer power model is influenceed by its geometric position on substrate.This temperature
Difference causes insufficient utilization of chip, thus, it is desirable to which given rated current is realized in more chip parallel connection, so as to increase work(
The totle drilling cost and physical table area of rate module.
The equalized temperature of chip is set to be solved by feedback control.
For Current Feedback Control loop, it is necessary to use high speed and high-precision sensor and processor.
For temperature feedback control, extra part has an impact to the cost of power model, weight, volume and power consumption.
The example reference picture 1 of this feedback control provides.
Fig. 1 represents the example for being used to control the system of the operation of multi-wafer power model according to prior art.
Multi-wafer power model 10 is for example by being marked as 1001To 1003Three chips composition.
The system of operation for controlling multi-wafer power model 10 includes controller 150, and the controller 150 is from main control
Device receives the control signal that put on multi-wafer power model 10, and the basis before chip is controlled with modified signal
The independent modification control signal in the electric current sensed and/or the temperature sensed each chip ground.
Chip 100 is independently fed to for the control signal that each chip is independently changed1To 1003Be marked as 1101
To 1103Independent gates connector.
Technical scheme
It is an object of the invention to strengthen the balance of chip temperature, the situation of highly dynamic control then need not implemented
The lower maximum capacity for improving multi-wafer power model.
Therefore, the present invention relates to a kind of system, the system includes：The multi-wafer power model being made up of chip；And control
Device, the controller receive multiple continuous input patterns of the chip for starting multi-wafer power model, and the feature of the system exists
In：Chip is grouped into multiple clusters of chip, and is characterised by：Controller includes being used for exporting for each cluster of chip
The unit of one grid source signal, each grid source signal that exports is different from other grid source signals, and at least one first output grid source
The startup of chip is reduced during at least one input pattern of the signal in multiple input patterns.
Thus, it is possible to change the electrical loss of chip between cluster.Because cluster includes at least one chip, relatively
In the quantity of chip, the quantity of the unit for exporting a grid source signal is limited.
According to special characteristic, the startup that chip is reduced during at least one input pattern in multiple input patterns passes through
Forbid the startup of chip during at least one input pattern to carry out.
Thus, the conducting of the chip at least one first cluster and switching loss are during at least one input pattern
It is empty.Loss between the chip of different clusters can be turned to as any damage curve.
According to special characteristic, chip is grouped into cluster according to position of the chip in multi-wafer power model.
Thus, easily aggregation is shared similar to cooling capacity for example due to the distance to Cooling and Heat Source or the presence of ambient heat sources
Chip.When undergoing same loss, the chip of cluster will also undergo identical knot (junction) temperature.
According to special characteristic, the quantity of adjacent chip of the chip according to chip in multi-wafer power model is grouped into group
Collection.
Thus, easily aggregation is shared similar to cooling capacity for example due to the distance to Cooling and Heat Source or the presence of ambient heat sources
Chip.When undergoing same loss, the chip of cluster will also undergo identical junction temperature.
Thus, the electrical loss of chip can change according to the cooling capacity of chip between cluster.Can be between cluster
Wafer loss curve is adjusted, to compensate different chip cooling capacities between cluster.Therefore, chip temperature can be whole more
Become balance on chip module to reach identical junction temperature.Because thermal stress becomes identical among wafers, chip it is old
Change and also become balance.Multi-wafer power model can become to determine chi for average junction temperature degree rather than for peak value chip temperature
Very little, this enables power model to operate and/or obtain at higher currents the longer life-span.
According to special characteristic, at least one second output grid source signal is identical with multiple input patterns.
Thus, it is possible to never disable the chip with optimal cooling capacity.Therefore, it can reach well balanced to realize
The damage curve of temperature, less need for other chips of deactivation with poor cooling capacity.Therefore, electric current is preferable among wafers
Ground is shared, and the chip of comparatively high amts contributes to the shared of electric current simultaneously.
According to special characteristic, controller includes memory cell, and the memory cell is used to store and in multiple input patterns
At least one input pattern during reduce the relevant information of startup of chip.
Thus, the deactivation of cluster can be in the independent junction temperature on need not sensing, estimate, obtaining or handling chip or cluster
Realized in an open-loop manner in the case of degree.Because it is pre-calculated the information relevant with the reduction started, multi-wafer power
The implementation of the control of module is simple.
According to special characteristic, controller also includes：
- it is used for what is arranged according to the continuous input pattern pair received the information relevant with the reduction of the startup of chip
Unit；With
- be used for the information that basis has arranged and the list of the output grid source signal of each cluster is established according to continuous input pattern
Member.
Thus, cluster disable can need not sense estimate chip or cluster on independent junction temperature in the case of
Realize in an open-loop manner.Because it is pre-calculated the information relevant with the reduction started, the control of multi-wafer power model
Implementation it is simple.
According to special characteristic, have for establishing the unit of output grid source signal of each cluster in the reduction of the startup with chip
During the deactivation of the information instruction input pattern of pass, the starting impulse of input pattern, or the reduction in the startup with chip are skipped
When relevant information does not indicate the deactivation of input pattern, then replicate input pattern.
Thus, the foundation for exporting grid source signal is simple from input pattern.When cluster skips starting impulse, chip is defeated
Conducting and the switching loss of multi-wafer power model will not be contributed to during entering pattern.
According to special characteristic, for establish each cluster output grid source signal unit in the relevant letter of the reduction with startup
During the deactivation of breath instruction input pattern, shorten the starting impulse of input pattern, or in the relevant information of the reduction with startup not
When indicating the deactivation of input pattern, then replicate input pattern.
Thus, when shortening starting impulse for cluster, chip will not contribute to multi-wafer work(during input pattern
The switching loss of rate module, but conduction loss will be contributed to.Because the dynamic loss in each chip is usual relative to rectified current
To be linear, so improving controllability of the multi-wafer power model towards equilibrium temperature.
The invention further relates to a kind of method for being used to control the operation for the multi-wafer power model being made up of chip, this method
It is characterised by：Method includes the following steps performed by controller：
- receive multiple continuous input patterns of chip for starting multi-wafer power model；
- a grid source signal is exported for each cluster of chip, each grid source signal that exports is different from other grid source signals, and
And reduce opening for chip during at least one input pattern of at least one first output grid source signal in multiple input patterns
It is dynamic.
Thus, it is possible to change the electrical loss of chip between cluster.Because cluster comprises more than a chip, relatively
In the quantity of chip, the quantity of the unit for exporting a grid source signal is limited.
The invention further relates to a kind of device for being used to control the operation of multi-wafer power model being made up of the cluster of chip,
The device is characterised by：Device includes：
- it is used for the unit that reception is used for the multiple continuous input patterns for the chip for starting multi-wafer power model；With
- the unit for each cluster one grid source signal of output for chip, it is each to export grid source signal and other grid sources
Signal is different, and subtracts during at least one input pattern of at least one first output grid source signal in multiple input patterns
The startup of few chip.
Thus, it is possible to change the electrical loss of chip between cluster.Because cluster includes at least one chip, relatively
In the quantity of chip, the quantity of the unit for exporting a grid source signal is limited.
The characteristic of the present invention will more clearly show from the reading described below of example embodiment, the description reference
Accompanying drawing produces, in accompanying drawing：
Brief description of the drawings
[Fig. 1]
Fig. 1 represents the example for being used to control the system of the operation of multi-wafer power model according to prior art.
[Fig. 2]
Fig. 2 represents the example for being used to control the system of the operation of multi-wafer power model according to the present invention.
[Fig. 3]
Fig. 3 represents the equivalent hot loop of simplification of the chip in thermal steady state in multi-wafer power model.
[Fig. 4 A]
Fig. 4 A represent the first of the framework of the controller of the operation for controlling multi-wafer power model according to the present invention
Example.
[Fig. 4 B]
Fig. 4 B represent the second of the framework of the controller of the operation for controlling multi-wafer power model according to the present invention
Example.
[Fig. 5]
Fig. 5 represents the calculation for being used to determine to be used to control the power mode of the operation of multi-wafer power model according to the present invention
Method.
[Fig. 6 A]
Fig. 6 A are represented according to the present invention by the power for controlling the controller of the operation of multi-wafer power model to use
The example of pattern.
[Fig. 6 B]
Fig. 6 B are represented according to the present invention by the power for controlling the controller of the operation of multi-wafer power model to use
The example of pattern.
[Fig. 6 C]
Fig. 6 C are represented according to the present invention by the power for controlling the controller of the operation of multi-wafer power model to use
The example of pattern.
[Fig. 6 D]
Fig. 6 D are represented according to the present invention by the power for controlling the controller of the operation of multi-wafer power model to use
The example of pattern.
[Fig. 6 E]
Fig. 6 E are represented according to the present invention by the power for controlling the controller of the operation of multi-wafer power model to use
The example of pattern.
[Fig. 7 A]
Fig. 7 A represent the power attenuation and temperature of each chip when the present invention is not carried out.
[Fig. 7 B]
Fig. 7 B represent the power attenuation and temperature of each chip when the present invention is not carried out.
[Fig. 8 A]
Fig. 8 A represent the power attenuation and temperature of each chip according to the present invention.
[Fig. 8 B]
Fig. 8 B represent the power attenuation and temperature of each chip according to the present invention.
Embodiment
Fig. 2 represents the example for being used to control the system of the operation of multi-wafer power model according to the present invention.
Multi-wafer power model 20 is for example by being marked as 2101To 2103Three chips composition.
The system of operation for controlling multi-wafer power model 20 includes controller 250, and the controller 250 is from main control
Device receives the input control signal that put on multi-wafer power model 20, and is deposited according in the memory of controller 250
Store up and the table comprising the enabling mode for each cluster changes the input control signal.
As an example, change input signal by skipping at least one startup period so that by modified signal control
The chip of system does not suffer from conduction loss, or starts the period by shortening to change signal so that is controlled by modified signal
Chip undergo less switching loss.
According to the present invention, the cluster of chip is determined, and controller 250 for chip each cluster according to start-up mode
The grid source signal of the chip of driving cluster is provided with input control signal.
Start-up mode for cluster is different from each other.
For example, multi-wafer power model 20 is divided into three clusters 2001、2002And 2003。
First cluster 2001Including being marked as 2101Chip.
Second cluster 2002Including being marked as 2102Chip.
3rd cluster 2003Including being marked as 2003Chip.
Cluster for example limits according to the symmetry axis of the chip in multi-wafer power model 20 and position.
In modified example, the first cluster and the 3rd cluster are grouped to form single cluster.
In the figure 2 example, the chip with two adjacent chips belongs to the second cluster.Crystalline substance with an adjacent chip
Piece belongs to the second cluster or the 3rd cluster.Chip with four adjacent chips belongs to the 3rd cluster.
The cooling capacity of chip relies on the quantity of surrounding chip.The quantity of surrounding chip is more, can dissipate in the wafer
Heat it is fewer, and if in each chip dissipation identical be lost, then chip temperature is higher.
Cluster for example determines when manufacturing multi-wafer power model 20.
This behavior is more fully described in reference picture 3.
Fig. 3 represents the equivalent hot loop of simplification of the chip in thermal steady state in multi-wafer power model.
Fig. 3 represents the simplification hot loop for three adjacent chips, and in the hot loop, main hot road is from chip to crystalline substance
Piece and from chip to housing.It is heat sink so that power attenuation heat transfer to experience heat sink temperature TsinkMulti-wafer power module package
Outside.
By with circuit analogy, the conducting of reason power die experience or switching loss and caused thermal source Q1To Q3Can be with
It is considered as current source, temperature rise Δ more than heat sink temperatureT1To ΔT3Voltage, material R can be considered asL1To RL4、Rl1To Rl5Performance
It is related to resistance and as the thermal capacity of electric capacity for thermal resistance, thermal conductivity.
RL2To RL3Represent the hot road between three adjacent chips.Rl2To Rl3Represent power die and it is heat sink between hot road.
RL1And RL4Represent the other hot road positioned at power model and/or heat sink edge.
Although loss balancing (the Q between parallel chip1=Q2=Q3), but temperature rise (the Δ T of chip1、ΔT2、ΔT3) due to
Chip it is uneven crowded and uneven.The reason for temperature imbalance is the thermal stress difference between chip, be thus chip it
Between aging differences the reason for.Therefore, the life-span of multi-wafer power model 20 is determined by the life-span of the chip by most stress,
But regardless of the chip by less stress life-span how.
Fig. 4 A represent the first of the framework of the controller of the operation for controlling multi-wafer power model according to the present invention
Example.
Controller 250 based on the part to be linked together by bus 401 and by programme-control to adjust for example with will carry
Supply the grid source signal CL of different clusters and processor 400 framework.
Processor 400 is related to read only memory ROM 402, random access memory ram 403 and electricity by bus 401
Power interface 406.
Memory 403 includes the register for the start-up mode for being intended to receive variable and different clusters.
If start-up mode is to determine in real time, it will be the grid source of different clusters offer that memory 403, which is included from regulation,
The instruction of the relevant program of signal CL algorithm.
Processor 400 receives the input gating signal pattern that put on multi-wafer power model, and is selected for input
Each startup cycle of messenger pattern and the startup of the chip of cluster is determined according to start-up mode for each cluster.
Electricity interface 406 establishes grid source signal CL1 using the start-up mode of the first cluster.Electricity interface 406 uses second
The start-up mode of cluster establishes grid source signal CL2.Electricity interface 406 establishes grid source signal using the start-up mode of the 3rd cluster
CL3。
For each cluster, when determining the startup of chip of cluster according to start-up mode in processor 400, grid source signal is defeated
Enter replicating again for gating signal.
When not yet determining the startup of the chip of cluster according to start-up mode in processor 400, grid source signal skips input choosing
The startup of messenger.
In modified example, when the startup of chip of cluster is not yet determined according to start-up mode in processor 400, grid source signal
Shorten the startup of input gating signal.
Read-only storage 02 includes the instruction of the program relevant with disclosed algorithm in Figure 5, and these instructions are in controller
250 are transferred to random access memory 403 when being powered.
Controller 250 can be by by programmable calculator (such as PC (personal computer), DSP (Digital Signal Processing
Device) or microcontroller) perform one group of instruction or program and implement in software, or (such as FPGA is (existing by machine or special-purpose member
Field programmable gate array) or ASIC (application specific integrated circuit)) implement within hardware.
In other words, controller 250 includes causing the circuit of the algorithm disclosed in the execution of controller 250 Fig. 5 or including circuit
Device.
Controller 250 can for example be realized by pre-programmed CPLD (CPLD).
Fig. 4 B represent the second of the framework of the controller of the operation for controlling multi-wafer power model according to the present invention
Example.
Controller 250 for example with based on sequencer 420 as such as counter, read only memory ROM 422 and
The framework of electricity interface 426.
Read only memory ROM 422 stores the power mode that be supplied to different clusters.
Sequencer 420 receives the input gating signal pattern that put on multi-wafer power model, and orders ROM422
To provide the power mode of the chip of cluster to be put on for each cluster and.Grid source signal CL1 is fed to the crystalline substance of the first cluster
Piece.Grid source signal CL2 is fed to the chip of the second cluster.Grid source signal CL3 is fed to the chip of the 3rd cluster.
Fig. 5 represents the calculation for being used to determine to be used to control the power mode of the operation of multi-wafer power model according to the present invention
Method.
This algorithm can be performed by the processor 400 of controller 250, or can be in the design of multi-wafer power model 20
Period performs.
Basically, this algorithm creates the imbalance power loss for being suitable for suitably being distributed, and which compensates for thermal unbalance.Cause
This, balances the temperature of the chip 200 of multi-wafer power model 20.
At step S50, processor 400 determines symmetry axis and the position of the chip in multi-wafer power model 20.
For example, multi-wafer power model 20 is divided into three clusters.
First cluster 2001Including being marked as 2101Chip.
Second cluster 2002Including being marked as 2102Chip.
3rd cluster 2003Including being marked as 2003Chip.
At next step S51, processor 400 obtains matrix MT..Matrix MTFor such as T=MTQ。
In the steady state, the linear relationship of contact thermal losses and temperature be present, the linear relationship can be expressed as MTQ=T,
Wherein, T represents the vector of the temperature of the cluster of the multi-wafer power model 20 or multi-wafer power model 20 under stable state, and Q tables
Show the vector of the loss of multi-wafer power model 20.Matrix T and Q by the during the design of multi-wafer power model 20 measurement
And/or emulate to determine.MTIt is linear matrix.
Matrix MTThe geometry design of power model is substantially resulted from, and as an example, has once manufactured polycrystalline
The first sample of piece power model 20, it is possible to measure.
As another example, heat supply network can be estimated from the design (geometry and material) of multi-wafer power model 20
Network, such as use 3DCAD systems.Once ther mal network parameter is known, for example, the RL and Rl as disclosed in reference picture 3, then be lost and temperature
Relation between degree is linear and can be using such as Dai Weining-Nortons theorem or using loop and modal equation come in shape
Identified in formula.Then, identified linear relationship is used easily to determine to realize the loss distribution needed for equilibrium temperature.
At next step S52, processor 400 determines to make temperature balance required damage curve q between crystalline substance.Q=
MT -1(1...1)。
At next step S53, processor 400 establishes matrix Mt.Matrix MtRow instruction when according to the present invention have modified use
The expected loss of each chip curve when the pattern of the chip of the given cluster of driving between cluster.According to the first example,
Coefficient Mti,j(wherein, the row of i and j representing matrixs) is identified below：
And MT i, j=N/ (N-Ndi), wherein, N is the number of the power die of multi-wafer power model 20
Amount, and NdiIt is the quantity of the power die of i ' th cluster.
According to the second example, matrix MtFirst row indicate for for driving the pattern of the chip of all clusters not repaiied
Damage curve when changing between cluster.Coefficient Mti,j(wherein, i and j representing matrixs MtRow) be identified below：
At next step S54, processor 400 determines to realize the weighing vector t needed for desired damage curve q, all
Such as t=Mt -1q。
When between cluster in the total ratio and weighing vector t coefficient t for disabling cycle and switch periodskIt is proportional
When, the damage curve realized by total several switch periods matches with identified vectorial q, and temperature curve and uniqueness to
Measure (unicity vector) matching.At next step S55, processor 400 determines Integer N for each clustersk。
For example, Nsk=round (tk*Ns), wherein, NsIt is the sum of pattern.Integer NskAnd NsIt is confirmed as making to be determined
Weighing vector t distance minimization.
At next step S56, processor 400 is according to identified several NskDetermine the start-up mode of cluster.
The example of exit pattern is given in Fig. 6.
Fig. 6 is represented according to the present invention by the power mould for controlling the controller of the operation of multi-wafer power model to use
The example of formula.
Fig. 6 A and Fig. 6 B represent the example of the start-up mode of the cluster of multi-wafer power model.
In Fig. 6 A Fig. 6 B and Fig. 6 E example, multi-wafer power model is broken down into two clusters.First cluster bag
Two chips are included, and the second cluster includes the single wafer between the chip of the first cluster.
Then, following result is for example provided according to the first example, Fig. 5 algorithm：
The pattern for being marked as 600 is input gating signal.
The pattern for being marked as 601 is the start-up mode of the first chip of the first cluster, and the pattern for being marked as 602 is
The start-up mode of the chip of two clusters, and be marked as 603 pattern be the first cluster the second chip start-up mode.
601st, 602 and 603 shadow region represents inactive switch, and white space represents movable switch.Becoming
In type example, 601,602 and 603 shadow region represents modification grid source signal to realize the switch of less switching loss week
Phase, and white space represents that grid source signal is not changed and equal to the switch periods of input gating signal.Therefore, the first cluster
Grid source signal be marked as 604, and including 5 continuous inactive switch periods.The grid source signal of second cluster is marked
605 are designated as, and including 9 continuous movable switch periods.It should be noted that when a cluster is inactive, other clusters
Activity.
The pattern for being marked as 620 is input gating signal.
The pattern for being marked as 621 is the start-up mode of the chip of the first cluster, and the pattern for being marked as 622 is second group
The start-up mode of the chip of collection, and be marked as 623 pattern be applied to the first cluster the second chip start-up mode.
621st, 622 and 623 shadow region represents inactive switch, and white space represents movable switch.
Therefore, the grid source signal of the first cluster is marked as 624, and including 5 inactive switch periods, and second group
The grid source signal of collection is marked as 625, and including 9 inactive switch periods.Dead period between cluster interweaves, with
Thermal stress is spread during total several switch periods.
Fig. 6 C and Fig. 6 D represent to put on the example of the power mode of the cluster of multi-wafer power model.
In Fig. 6 C and Fig. 6 D example, multi-wafer power model is broken down into three clusters.
Then, Fig. 5 algorithm for example provides following result：
The pattern for being marked as 630 is the start-up mode of the chip of the first cluster, and the pattern for being marked as 631 is second group
The start-up mode of the chip of collection, and be marked as 632 pattern be the 3rd cluster chip start-up mode.
The pattern for being marked as 640 is the start-up mode of the chip of the first cluster, and the pattern for being marked as 641 is second group
The start-up mode of the chip of collection, and be marked as 642 pattern be the 3rd cluster chip start-up mode.
630th, 631,632,640,641 and 642 shadow region represents inactive switch, and white space represents to live
Dynamic switch.
Fig. 6 E represent the example of the power mode of the cluster for putting on multi-wafer power model according to the second example.
Then, Fig. 5 algorithm for example provides following result：
The pattern for being marked as 650 is the start-up mode of the chip of the first cluster, and the pattern for being marked as 651 is second group
The start-up mode of the chip of collection, and be marked as 652 pattern be the 3rd cluster chip start-up mode.
650th, 651,652 shadow region represents inactive switch, and white space represents movable switch.
According to the second example, the chip of the first cluster is always off.The chip of second cluster is only continuous defeated at 29
Disabled during entering two in pattern input patterns.
Fig. 7 represents the power attenuation and temperature of each chip when the present invention is not carried out.
Fig. 7 A show the power attenuation of each chip curve in the cluster of chip.Transverse axis represents chip, and the longitudinal axis is shown
The power attenuation of corresponding chip.Power attenuation balances between all wafers.
Fig. 7 B show junction temperature chip.Transverse axis represents chip, and the longitudinal axis shows the junction temperature of corresponding chip.Positioned at multi-wafer
The chip experience preferably cooling, and their temperature is than positioned at the center of multi-wafer power model of the edge of power model
The temperature of the chip at place is low.
Fig. 8 represents the power attenuation and temperature of each chip according to the present invention.
Fig. 8 A show the power attenuation of each chip curve in the cluster of chip.Transverse axis represents chip, and the longitudinal axis is shown
The power attenuation of corresponding chip.Power attenuation is uneven among wafers according to the present invention.Positioned at the side of multi-wafer power model
Chip at edge is configured to loss of the experience than the chip high level at the center of multi-wafer power model.
Fig. 8 B show junction temperature chip.Transverse axis represents chip, and the longitudinal axis shows the junction temperature of corresponding chip.Positioned at multi-wafer
The preferable cooling capacity of the chip of the edge of power model is by compensating the higher contribution of power attenuation.Therefore, temperature
Balance among wafers.
Of course, it is possible to embodiments of the present invention described above are entered in the case of without departing from the scope of the present invention
The many modifications of row.
Claims (13)
1. a kind of system, the system includes：The multi-wafer power model being made up of chip；And controller, the controller, which receives, to be used
In the multiple continuous input patterns for the chip for starting the multi-wafer power model, the system is characterized in that：The crystalline substance
Piece is grouped into multiple clusters of chip, and is characterised by：The controller includes being used for exporting for each cluster of chip
The unit of one grid source signal, each grid source signal that exports is different from other grid source signals, and at least one first output grid source
The startup of chip is reduced during at least one input pattern of the signal in the multiple input pattern.
2. system according to claim 1, it is characterised in that：At least one input mould in the multiple input pattern
The startup for reducing chip during formula is entered by forbidding the startup of chip during at least one input pattern
OK.
3. system according to claim 1 or 2, it is characterised in that：The chip is according to the chip in the multi-wafer
Position in power model is grouped into cluster.
4. system according to claim 1 or 2, it is characterised in that：The chip is according to the chip in the multi-wafer
The quantity of adjacent chip is grouped into cluster in power model.
5. system according to any one of claim 1 to 4, it is characterised in that：At least one second output grid source signal
It is identical with the multiple input pattern.
6. system according to any one of claim 1 to 5, it is characterised in that：The controller includes memory cell, should
Memory cell is used to store and the startup of chip during at least one input pattern in the multiple input pattern
It is described to reduce relevant information.
7. system according to claim 6, it is characterised in that：The controller also includes：
- be used to be entered according to the continuous input pattern pair received the described information relevant with the reduction of the startup of chip
The unit of row arrangement；With
- be used for the information that basis has arranged and the list of the output grid source signal of each cluster is established according to the continuous input pattern
Member.
8. system according to claim 7, it is characterised in that：The unit of output grid source signal for establishing each cluster exists
When the information instruction input pattern relevant with the reduction of the startup of chip disables, the startup of the input pattern is skipped
Pulse, or when the relevant information of the reduction of the startup with chip does not indicate that the input pattern disables, then replicate institute
State input pattern.
9. system according to claim 7, it is characterised in that：The unit of output grid source signal for establishing each cluster exists
When the information instruction input pattern relevant with the reduction of startup disables, shorten the starting impulse of the input pattern,
Or the input pattern is replicated again when the information relevant with the reduction of startup does not indicate that the input pattern disables.
10. a kind of method for being used to control the operation for the multi-wafer power model being made up of chip, the method is characterized in that：Institute
State the following steps that method includes being performed by controller：
- receive multiple continuous input patterns of the chip for starting the multi-wafer power model；And
- a grid source signal is exported for each cluster of chip, each grid source signal that exports is different from other grid source signals, and extremely
The institute of chip is reduced during at least one input pattern of few one first output grid source signal in the multiple input pattern
State startup.
11. according to the method for claim 10, it is characterised in that：At least one input in the multiple input pattern
During pattern reduce chip the startup by forbid the startup of chip during at least one input pattern come
Carry out.
12. the method according to any one of claim 10 or 11, it is characterised in that：At least one second output grid source letter
It is number identical with the multiple input pattern.
13. a kind of device for being used to control the operation for the multi-wafer power model being made up of the cluster of chip, the feature of the device
It is：Described device includes：
- it is used for the unit that reception is used for the multiple continuous input patterns for the chip for starting the multi-wafer power model；
- the unit for each cluster one grid source signal of output for chip, it is each to export grid source signal and other grid source signals
Difference, and subtract during at least one input pattern of at least one first output grid source signal in the multiple input pattern
The startup of few chip.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP15171259.3A EP3104526B1 (en) | 2015-06-09 | 2015-06-09 | System and method for controlling a multi-die power module |
| EP15171259.3 | 2015-06-09 | ||
| PCT/JP2016/067463 WO2016199929A1 (en) | 2015-06-09 | 2016-06-06 | System comprising multi-die power module, method for controlling operation of multi-die power module, device for controlling operation of multi-die power module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107771372A true CN107771372A (en) | 2018-03-06 |
| CN107771372B CN107771372B (en) | 2021-04-20 |
Family
ID=53396307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201680033603.9A Active CN107771372B (en) | 2015-06-09 | 2016-06-06 | System comprising a multi-chip power module, method for controlling the operation of a multi-chip power module, device for controlling the operation of a multi-chip power module |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US10277218B2 (en) |
| EP (1) | EP3104526B1 (en) |
| JP (1) | JP6430026B2 (en) |
| CN (1) | CN107771372B (en) |
| DK (1) | DK3104526T3 (en) |
| WO (1) | WO2016199929A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| EP3336499B1 (en) * | 2016-12-16 | 2019-12-11 | Mitsubishi Electric R & D Centre Europe B.V. | Method for controlling the temperature of a multi-die power module |
| US11258294B2 (en) * | 2019-11-19 | 2022-02-22 | Bloom Energy Corporation | Microgrid with power equalizer bus and method of operating same |
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Also Published As
| Publication number | Publication date |
|---|---|
| JP2018506945A (en) | 2018-03-08 |
| EP3104526B1 (en) | 2020-12-02 |
| CN107771372B (en) | 2021-04-20 |
| DK3104526T3 (en) | 2021-02-22 |
| WO2016199929A1 (en) | 2016-12-15 |
| US20180302079A1 (en) | 2018-10-18 |
| EP3104526A1 (en) | 2016-12-14 |
| US10277218B2 (en) | 2019-04-30 |
| JP6430026B2 (en) | 2018-11-28 |
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