CN107769776B - Modulator circuit capable of reducing high-frequency noise influence in fractional frequency synthesizer - Google Patents
Modulator circuit capable of reducing high-frequency noise influence in fractional frequency synthesizer Download PDFInfo
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- CN107769776B CN107769776B CN201711084846.8A CN201711084846A CN107769776B CN 107769776 B CN107769776 B CN 107769776B CN 201711084846 A CN201711084846 A CN 201711084846A CN 107769776 B CN107769776 B CN 107769776B
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- 230000000694 effects Effects 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 4
- 238000001228 spectrum Methods 0.000 claims abstract description 4
- 239000003990 capacitor Substances 0.000 claims description 15
- 230000009977 dual effect Effects 0.000 claims description 2
- 230000009466 transformation Effects 0.000 claims description 2
- 238000001914 filtration Methods 0.000 abstract description 11
- 238000013139 quantization Methods 0.000 description 7
- 238000004088 simulation Methods 0.000 description 4
- 230000006978 adaptation Effects 0.000 description 2
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- 238000012986 modification Methods 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
The invention discloses a modulator circuit capable of reducing the influence of high-frequency noise in a decimal frequency dividing frequency synthesizer, which comprises a gear selection module, a multistage cascade modulation module and a notch filter module, wherein the gear selection module selects decimal truncated digits and a corresponding notch filter circuit; the notch filter module firstly performs partial interception before the input decimal value enters the multistage cascade modulation module, and then recovers the numerical value to the original expected value through the notch filter circuit after the multistage cascade modulation module processes the numerical value and reduces the noise spectrum density at high frequency; the invention provides a modulator circuit capable of reducing the influence of high-frequency noise in a fractional frequency synthesizer, and the configurable notch filter structure of the modulator circuit can reduce the frequency of high-value output and has additional filtering effect on the high-frequency noise.
Description
Technical Field
The invention relates to the field of radio frequency and analog integrated circuits, in particular to a modulator circuit capable of reducing the influence of high-frequency noise in a fractional frequency synthesizer
Background
Currently, fractional frequency synthesizers use dual mode dividers, which inevitably introduce quantization noise and fractional spurs. To address this problem, it is conventional to introduce a Delta-Sigma modulator (DSM) to address this problem. The module can effectively convert quantization errors in the system to random noise and shift to higher frequencies, which can be suppressed due to the low pass filter characteristics of the loop. However, the noise shaping by using the Delta-Sigma modulator with the conventional structure cannot completely eliminate the quantization noise, and the amplitude of the outputted quantization noise is large, so that on one hand, when the loop bandwidth is large, the high-frequency noise cannot be suppressed by the loop filter, and the out-of-band noise performance is deteriorated, on the other hand, too large variation range of the output level of the Delta-Sigma modulator can cause more remarkable nonlinear effects in the Phase Frequency Detector (PFD) and Charge Pump (CP) circuits, and the in-band noise of the frequency synthesizer is increased.
Disclosure of Invention
The invention overcomes the defects of the prior art, and provides a novel configurable notch filtering structure which can reduce the occurrence frequency of output high values and has additional filtering effect on high-frequency noise.
The modulator circuit capable of reducing the influence of high-frequency noise in the fractional frequency synthesizer comprises a gear selection module, a multistage cascade modulation module and a notch filter module, wherein the gear selection module selects a fractional interception bit number and a corresponding notch filter circuit; the notch filter module firstly intercepts part of the input decimal value before the input decimal value enters the multistage cascade modulation module, and then recovers the numerical value to the original expected value through the notch filter circuit after the multistage cascade modulation module processes the input decimal value, and reduces noise spectrum density at high frequency.
Further, the phase frequency detector is connected with a reference frequency of the reference clock signal.
Further, the modulator circuit also comprises a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, a frequency divider, a modulator for reducing the influence of high-frequency noise and a dual-mode frequency divider;
The phase frequency detector is connected with a switch of the charge pump, the charge pump is connected with the loop filter in series, the loop filter comprises a first resistor, a first capacitor and a second capacitor, the first resistor is connected with the first capacitor in series, one end of the first capacitor is grounded, and one end of the second capacitor is grounded; the voltage-controlled oscillator is connected with one end of the frequency divider and one end of the dual-mode frequency divider, the dual-mode frequency divider is connected with one end of the phase frequency detector, the modulator for reducing the influence of high-frequency noise is connected to the dual-mode frequency divider, and the modulator for reducing the influence of high-frequency noise is provided with an interface of an integer frequency division ratio and a fractional frequency division ratio.
Compared with the prior art, the invention has the advantages that: the new configurable notch filtering structure can reduce the frequency of high value in output, and has additional filtering effect on high frequency noise, so that the Delta-Sigma modulator has better noise suppression capability. The probability of high values (-3, -2, 3, 4) can be greatly reduced; and has a certain filtering effect on noise in the vicinity of a specific frequency (fs/2N, fs/2N-1, etc., wherein fs is the operating frequency of DSM).
Drawings
FIG. 1 is a schematic diagram of the structure of the present invention;
FIG. 2 is a block diagram of a modulator circuit of the present invention;
FIG. 3 is a graph showing the effect of the modulator for reducing the influence of high frequency noise according to the present invention compared with that of a conventional modulator;
FIG. 4 is a graph comparing the spectral density of the output power of the present invention with that of a conventional modulator;
FIG. 5 is a graph comparing the simulation results of the system phase noise of the present invention and the conventional frequency synthesizer.
Detailed Description
The invention is further described below with reference to the drawings and the detailed description.
As shown in fig. 1, a modulator circuit capable of reducing the influence of high-frequency noise in a fractional frequency synthesizer comprises a gear selection module, a multistage cascade modulation module and a notch filter module, wherein the gear selection module selects a fractional truncated digit number and a corresponding notch filter circuit, and enables an integer frequency division ratio to directly enter the multistage cascade modulation module. The notch filter module firstly intercepts part of the input decimal value before the input decimal value enters the multistage cascade modulation module, and then recovers the numerical value to the original expected value through the notch filter circuit after the multistage cascade modulation module processes the input decimal value, and reduces noise spectrum density at high frequency. The phase frequency detector is connected with a reference frequency of a reference clock signal. The noise transfer formula NTF (z) of the modulator for reducing the influence of high-frequency noise is the following formula (1):
Wherein N is the gear of the gear selection module, Z is the input complex variable of the Z transformation formula, and k is the variable in the sum symbol.
As shown in fig. 2, the modulator circuit further includes a phase frequency detector, a charge pump, a loop filter (LPF), a Voltage Controlled Oscillator (VCO), a frequency Divider (DIV), a modulator that reduces the effects of high frequency noise, and a dual-mode frequency divider. The phase frequency detector is connected with a switch of the charge pump, the charge pump is connected with the loop filter in series, the loop filter comprises a first resistor, a first capacitor and a second capacitor, the first resistor is connected with the first capacitor in series, one end of the first capacitor is grounded, and one end of the second capacitor is grounded; the voltage-controlled oscillator is connected with one end of the frequency divider and one end of the dual-mode frequency divider, the dual-mode frequency divider is connected with one end of the phase frequency detector, the modulator for reducing the influence of high-frequency noise is connected to the dual-mode frequency divider, and the modulator for reducing the influence of high-frequency noise is provided with an interface of an integer frequency division ratio and a fractional frequency division ratio.
Conventional Delta Sigma modulators are typically implemented using a three-order multistage cascade modulator architecture that effectively converts quantization errors in the system to random noise and to higher frequencies that are suppressed by the low pass filter characteristics of the loop. However, the Delta-Sigma modulator with the conventional structure cannot completely eliminate quantization noise, and the amplitude of the output quantization noise is large, so that on one hand, when the loop bandwidth is large, high-frequency noise cannot be suppressed by the loop filter, and the performance of out-of-band noise is deteriorated, on the other hand, when the output level of the Delta-Sigma modulator is too large, a more remarkable nonlinear effect is caused in the PFD and CP circuits, and the in-band noise of the frequency synthesizer is increased.
The gear selection module of the novel modulator based on reducing the influence of high-frequency noise can be increased according to actual requirements, and is not limited to four gears as shown in fig. 2. And when N is 0, 1,2 and 3 according to a noise transfer formula NTF (z) by four-gear examples, the noise transfer formulas are respectively as follows:
NTF(z)N＝0＝(1-z-1)3
Taking a mode of n=3 as an example, the newly added notch filtering module is equivalent to performing a divide-by-8 operation before the input decimal value enters the multi-stage cascade modulation module, and then passing through a noise transfer formula (equivalent to performing a multiply-by-8 operation on the signal from the time domain) before the final output after the processing of the multi-stage cascade modulation module, so that the numerical value is restored to the expected value. Thereby greatly reducing the occurrence probability of high values (-3, -2, 3, 4); and has a certain filtering effect on noise in the vicinity of a specific frequency (fs/2N, fs/2N-1, etc., wherein fs is the operating frequency of DSM). The simulation results are shown in fig. 3 to 5:
As shown in FIG. 3, the conventional structure of the Delta-Sigma modulator has an output value ranging from-3 to 4, and the probability of occurrence of high values (-3, -2, 3, 4) is greatly reduced, and the probability of occurrence of-3 and 4 is even almost 0 after the improved structure of the present invention is added.
As shown in fig. 4, the output power spectral density of the conventional structure of the Delta Sigma modulator is shown in the left graph, and after the improved structure of the present invention is added, a filtering effect is provided at a specific frequency point, so that high-frequency noise can be suppressed to a certain extent. The figure shows the result of n=3, in which mode there is a filtering effect of approximately 30dB for fs/8 frequencies and also a certain filtering effect for fs/4 and fs/2.
As shown in fig. 5, the left side of the graph is the simulation result of the system phase noise of the frequency synthesizer adopting the conventional structure of the Delta Sigma modulator, and the right side is the simulation result of the system phase noise of the frequency synthesizer adopting the structure of the invention. Under the condition that other modules and loop parameters are unchanged, the structure of the invention is introduced, so that the high-frequency phase noise of the DSM can be greatly restrained.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the concept of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the present invention.
Claims (3)
1. The modulator circuit capable of reducing the influence of high-frequency noise in the fractional frequency synthesizer is characterized by comprising a gear selection module, a multistage cascade modulation module and a notch filter module, wherein the gear selection module selects a fractional truncated number of bits and a corresponding notch filter circuit; the notch filter module firstly performs partial interception before the input decimal value enters the multistage cascade modulation module, and then recovers the numerical value to the original expected value through the notch filter circuit after the multistage cascade modulation module processes the numerical value and reduces the noise spectrum density at high frequency; the multistage cascade modulation module comprises a plurality of cascaded modulators, the modulators modulate input decimal values through noise transfer, and a noise transfer formula NTF (z) carried out by the modulators is as follows:
Wherein N is the gear of the gear selection module, Z is the input complex variable of the Z transformation formula, and k is the variable in the sum symbol.
2. A modulator circuit for reducing the effects of high frequency noise in a fractional frequency synthesizer according to claim 1, further comprising a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, a frequency divider, a modulator for reducing the effects of high frequency noise, and a dual mode frequency divider;
The phase frequency detector is connected with a switch of the charge pump, the charge pump is connected with the loop filter in series, the loop filter comprises a first resistor, a first capacitor and a second capacitor, the first resistor is connected with the first capacitor in series, one end of the first capacitor is grounded, and one end of the second capacitor is grounded; the voltage-controlled oscillator is connected with one end of the frequency divider and one end of the dual-mode frequency divider, the dual-mode frequency divider is connected with one end of the phase frequency detector, the modulator for reducing the influence of high-frequency noise is connected to the dual-mode frequency divider, and the modulator for reducing the influence of high-frequency noise is provided with an interface of an integer frequency division ratio and a fractional frequency division ratio.
3. A modulator circuit for reducing the effects of high frequency noise in a fractional frequency synthesizer according to claim 2, wherein said phase frequency detector is coupled to a reference frequency of a reference clock signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711084846.8A CN107769776B (en) | 2017-11-07 | 2017-11-07 | Modulator circuit capable of reducing high-frequency noise influence in fractional frequency synthesizer |
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| CN107769776B true CN107769776B (en) | 2024-06-07 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6236703B1 (en) * | 1998-03-31 | 2001-05-22 | Philsar Semiconductor Inc. | Fractional-N divider using a delta-sigma modulator |
| CN103163829A (en) * | 2011-12-13 | 2013-06-19 | 东芝机械株式会社 | Servo-controller and adjusting method thereof |
| US9762259B1 (en) * | 2017-01-09 | 2017-09-12 | Texas Instruments Incorporated | Sigma-delta analog-to-digital converter with auto tunable loop filter |
| CN207732750U (en) * | 2017-11-07 | 2018-08-14 | 杭州城芯科技有限公司 | A kind of modulator reducing the influence of fractional frequency division frequency synthesizer high-frequency noises |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8278982B2 (en) * | 2009-12-29 | 2012-10-02 | Analog Devices, Inc. | Low noise fractional divider using a multiphase oscillator |
| US9143138B2 (en) * | 2013-02-27 | 2015-09-22 | Microsemi Semiconductor Ulc | Phase locked loop frequency synthesizer with reduced jitter |
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2017
- 2017-11-07 CN CN201711084846.8A patent/CN107769776B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6236703B1 (en) * | 1998-03-31 | 2001-05-22 | Philsar Semiconductor Inc. | Fractional-N divider using a delta-sigma modulator |
| CN103163829A (en) * | 2011-12-13 | 2013-06-19 | 东芝机械株式会社 | Servo-controller and adjusting method thereof |
| US9762259B1 (en) * | 2017-01-09 | 2017-09-12 | Texas Instruments Incorporated | Sigma-delta analog-to-digital converter with auto tunable loop filter |
| CN207732750U (en) * | 2017-11-07 | 2018-08-14 | 杭州城芯科技有限公司 | A kind of modulator reducing the influence of fractional frequency division frequency synthesizer high-frequency noises |
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Inventor after: Li Haoming Inventor after: Li Guoru Inventor after: Wang Tengjia Inventor after: Zhou Suping Inventor after: Wang Xiaofeng Inventor after: Shen Yupeng Inventor after: Chen Xubin Inventor before: Li Haoming Inventor before: Li Guoru Inventor before: Liu Jiarui Inventor before: Wang Tengjia Inventor before: Zhou Suping Inventor before: Wang Xiaofeng Inventor before: Shen Yupeng Inventor before: Chen Xubin |
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