CN107768245A - The preparation method and PIN diode of PIN diode - Google Patents

The preparation method and PIN diode of PIN diode Download PDF

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Publication number
CN107768245A
CN107768245A CN201610676716.2A CN201610676716A CN107768245A CN 107768245 A CN107768245 A CN 107768245A CN 201610676716 A CN201610676716 A CN 201610676716A CN 107768245 A CN107768245 A CN 107768245A
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China
Prior art keywords
type
injection region
substrate
pin diode
preparation
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CN201610676716.2A
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Chinese (zh)
Inventor
李理
赵圣哲
马万里
姚雪霞
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Peking University Founder Group Co Ltd
Shenzhen Founder Microelectronics Co Ltd
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Peking University Founder Group Co Ltd
Shenzhen Founder Microelectronics Co Ltd
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Priority to CN201610676716.2A priority Critical patent/CN107768245A/en
Publication of CN107768245A publication Critical patent/CN107768245A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609Diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/868PIN diodes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The present invention provides a kind of preparation method and PIN diode of PIN diode, and preparation method includes:At least two p-type ion ranges are formed in N-type substrate;P-type injection region is formed in the N-type substrate, the p-type injection region contacts each p-type ion range above each p-type ion range;The first metal layer as a lateral electrode is formed on the p-type injection region, and the second metal layer as another lateral electrode is formed on side of the N-type substrate away from the p-type injection region.In accordance with the invention it is possible to improve the resistance to pressure of PIN diode.

Description

The preparation method and PIN diode of PIN diode
Technical field
The present invention relates to the preparation method and PIN diode of semiconductor technology, more particularly to a kind of PIN diode.
Background technology
Common diode is made up of PN junction, i.e., a thin layer is added between p-type semiconductor material and N-type semiconductor material Low-doped intrinsic (Intrinsic) semiconductor layer, the diode of this P-I-N structures of composition is exactly PIN diode.
Just because of there is the presence of intrinsic (Intrinsic) layer, PIN diode application is very extensive, and it is applied to inverse in high frequency Become the various advanced weaponries such as the product for civilian use and satellite receiver, the guided missile and aircrafts such as device, digital product, generator, television set The military scenario of control system and instrumentation devices.
In the prior art, the preparation method of PIN diode is as shown in Figure 1A to Figure 1B.
As shown in Figure 1A, p-type injection region 111 is formed using ion implanting mode in N-type substrate 110.
As shown in Figure 1B, the first metal layer 112 is formed above p-type injection region 111, and in the opposite side of N-type substrate 110 Form second metal layer 113.
The resistance to pressure of PIN diode is its very important characteristic, and resistance to pressure is higher, and its breakdown possibility is got over It is small, and then can prevent because breakdown causes the damage of other elements in circuit.So, the pressure-resistant of PIN diode how is improved The problem of property turns into urgent need to resolve.
The content of the invention
The present invention provides a kind of preparation method and PIN diode of PIN diode, to improve the resistance to pressure of PIN diode.
One side of the invention provides a kind of preparation method of PIN diode, including:
P-type injection region is formed in the N-type substrate, the p-type injection region is located above each p-type ion range, And each p-type ion range of contact;
The first metal layer as a lateral electrode is formed on the p-type injection region, and in the N-type substrate away from described The side of p-type injection region forms the second metal layer as another lateral electrode.
According to preparation method as described above, alternatively, the p-type ion range that formed in N-type substrate includes:
Mask layer is formed in the N-type substrate;
Photoetching process is carried out to mask layer, forms at least two injection windows;
By the injection window to the N-type substrate implanting p-type ion, the p-type ion range is formed;
The mask layer is removed, and carries out annealing process.
According to preparation method as described above, alternatively, the spacing between each injection window is the injection window 3-5 times of width.
According to preparation method as described above, alternatively, the concentration of the p-type injection region and the p-type ion concentration The ratio between be 100-1000.
According to preparation method as described above, alternatively, the N-type substrate includes:N+ types substrate and formation are in the N N-type epitaxial layer on+type substrate.
Another aspect of the invention provides a kind of PIN diode, including:
N-type substrate;
At least two p-type ion ranges, in N-type substrate;
P-type injection region, in N-type substrate, the p-type injection region contacts above each p-type ion range Each p-type ion range;
The first metal layer, on p-type injection region;
Second metal layer, the side away from the p-type injection region in N-type substrate.
According to PIN diode as described above, alternatively, spacing between each p-type ion range for the p-type from 3-5 times of the width of subregion.
According to PIN diode as described above, alternatively, the concentration of the p-type injection region and the p-type ion concentration The ratio between be 100-1000.
According to PIN diode as described above, alternatively, the N-type substrate includes:N+ types substrate and formation are described N-type epitaxial layer on N+ type substrates.
According to PIN diode as described above, alternatively, the concentration of the p-type injection region is 1012Atom/cm2-1013It is former Son/cm2
As shown from the above technical solution, the preparation method and PIN diode of PIN diode provided by the invention, by N At least two p-type ion ranges are formed in type substrate, then form p-type injection region above p-type ion range again, so, When PIN diode loads reverse biased, in addition to forming depletion region with N-type substrate except p-type injection region, p-type ion range Depletion region can be formed with N-type substrate, so, the width of depletion region can be increased, and then improve the resistance to pressure of PIN diode.In addition, Under identical breakdown voltage, due to the presence of p-type ion range, the concentration of p-type injection region can be lower than without p-type ion area Concentration during domain, in such manner, it is possible to reduce the forward voltage drop of PIN diode.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are this hairs Some bright embodiments, for those of ordinary skill in the art, without having to pay creative labor, can be with Other accompanying drawings are obtained according to these accompanying drawings.
Figure 1A and 1B is the structural representation for each step for making PIN diode in the prior art;
Fig. 2 is the schematic flow sheet according to the preparation method of the PIN diode of one embodiment of the invention;
Fig. 3 A to Fig. 3 F are the structure according to each step of the preparation method of the PIN diode of another embodiment of the present invention Schematic diagram;
Fig. 4 is the structural representation according to the PIN diode of yet another embodiment of the invention.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is Part of the embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art The every other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
Embodiment one
The present embodiment provides a kind of preparation method of PIN diode, for making PIN diode.As shown in Fig. 2 it is root According to the schematic flow sheet of the preparation method of the PIN diode of the present embodiment.
Step 201, at least two p-type ion ranges are formed in N-type substrate.
The N-type substrate includes:The N-type epitaxial layer of N+ types substrate and formation on N+ type substrates.Wherein N+ represents N-type Heavy doping, N- represent N-type and are lightly doped.
P-type ion range can be P+ ion ranges, and P+ represents p-type heavy doping.Specific generation type can pass through ion The mode of injection is formed.The number of p-type ion range is at least 2.
Step 202, p-type injection region is formed in N-type substrate, p-type injection region is located above p-type ion range and contact P Type ion range.
P-type injection region is formed on a side surface of N-type substrate, specific generation type can be the side by ion implanting Formula is formed, and the depth of the p-type injection region in N-type substrate is less than the depth of p-type ion range, i.e. the p-type injection region is located at P Above type ion range.
Step 203, the first metal layer as a lateral electrode is formed on p-type injection region, and in N-type substrate away from p-type The second metal layer as another lateral electrode is formed on the side of injection region.
For example, the first metal layer and the material of second metal layer can be copper or aluminium, can specifically use physics gas Phase method forms the first metal layer or second metal layer.
Then, connecting wire is set respectively on the first metal layer and second metal layer, it becomes possible to connect the PIN diode External circuitry is connect to be operated.
According to the present embodiment, by forming at least two p-type ion ranges in N-type substrate, then again in p-type ion area P-type injection region is formed above domain, so, when PIN diode loads reverse biased, except p-type injection region can be with N-type substrate shape Into outside depletion region, p-type ion range also can form depletion region with N-type substrate, so, can increase the width of depletion region, and then Improve the resistance to pressure of PIN diode.In addition, under identical breakdown voltage, due to the presence of p-type ion range, p-type injection region Concentration of concentration when can be lower than without p-type ion range, in such manner, it is possible to reduce the forward voltage drop of PIN diode.
Embodiment two
It is to be shown according to the structure of each step of the preparation method of the PIN diode of the present embodiment as shown in Fig. 3 A to 3F It is intended to.
As shown in Figure 3A, mask layer 301 is formed in N-type substrate 300.
The mask layer 301 can be photoresist layer, specifically can form the photoresist layer by the way of coating.
For example, the N-type substrate 300 includes:The N-type of N+ types substrate 3001 and formation on N+ types substrate 3001 Epitaxial layer 3002.Wherein N+ represents N-type heavy doping, and N- represents N-type and is lightly doped.
As shown in Figure 3 B, photoetching process is carried out to mask layer 301, at least two injection window 302 in formation.
Specifically, can be open according to being actually needed to be formed on mask layer 301, the opening is exactly to be subsequently used for ion The injection window 302 of injection.Each injection window 302 is used to be subsequently formed a p-type ion range.
Alternatively, the spacing respectively between injection window is inject window width 3-5 times.So, can either ensure follow-up The width of the p-type ion range 303 formed, also it can avoid influencing each other for each p-type ion range 303, such as its as far as possible In ion in a p-type ion range 303 be diffused into another p-type ion range 303.
As shown in Figure 3 C, by injecting window 302 to the implanting p-type ion of N-type substrate 300, p-type ion range 303 is formed.
One corresponding p-type ion range 303 of injection window 302.P-type ion range can be P+ ion ranges, P+ Represent p-type heavy doping.Specific generation type can be formed by way of ion implanting.
As shown in Figure 3 D, mask layer 301 is removed, and carries out annealing process.
The mask layer 301 specifically can be removed by the way of ashing.Annealing process is used for the ion for activating injection, and touches Send out the diffusion of p-type ion range intermediate ion.
As shown in FIGURE 3 E, p-type injection region 304 is formed in N-type substrate 300, p-type injection region 304 is located at each p-type ion area The top of domain 303, and contact each p-type ion range 303.
The p-type injection region 304 is located in N-type substrate 300, and each p-type ion range 303 partially overlaps.Do not injected with p-type The p-type ion range that area 304 overlaps is labeled as 303 '.
Alternatively, the concentration of the p-type injection region is 1012Atom/cm2-1013Atom/cm2
As illustrated in Figure 3 F, the first metal layer 305 as a lateral electrode is formed on p-type injection region 304, and in N-type base The second metal layer 306 as another lateral electrode is formed on side of the bottom 300 away from p-type injection region 304.
For example, the first metal layer and the material of second metal layer can be copper or aluminium, can specifically use physics gas Phase method forms the first metal layer or second metal layer.
Then, connecting wire is set respectively on the first metal layer and second metal layer, it becomes possible to connect the PIN diode External circuitry is connect to be operated.
According to the present embodiment, by forming at least two p-type ion ranges in N-type substrate, then again in p-type ion area P-type injection region is formed above domain, so, when PIN diode loads reverse biased, except p-type injection region can be with N-type substrate shape Into outside depletion region, p-type ion range also can form depletion region with N-type substrate, so, can increase the width of depletion region, and then Improve the resistance to pressure of PIN diode.In addition, under identical breakdown voltage, due to the presence of p-type ion range, p-type injection region Concentration of concentration when can be lower than without p-type ion range, in such manner, it is possible to reduce the forward voltage drop of PIN diode.
Embodiment three
The present embodiment provides a kind of PIN diode, can specifically use the method for above-described embodiment to be made.
As shown in figure 4, the PIN diode of the present embodiment includes N-type substrate 401, at least two p-type ion ranges 402, P Type injection region 403, the first metal layer 404 and second metal layer 405.
Wherein, N-type substrate 401 can include:N+ types substrate 4011 and formation are outside the N-type on N+ types substrate 4011 Prolong layer 4012;P-type ion range 402 is located in N-type substrate 401, is particularly located in N+ types substrate 4011;P-type injection region 403 In N-type substrate, p-type injection region 403 contacts each p-type ion range 402 positioned at each top of p-type ion range 402, for example, P-type injection region can be located in N+ types substrate 4011;The first metal layer 404 is located on p-type injection region 403;Second metal layer 405 The side away from p-type injection region 403 in N-type substrate 401, for example, the side of N-type epitaxial layer 4012 can be located at.
Alternatively, the spacing between each p-type ion range is 3-5 times of width of p-type ion range.
Alternatively, the concentration of p-type injection region is 1012Atom/cm2-1013Atom/cm2
Alternatively, the concentration of p-type injection region and the ratio between p-type ion concentration be 100-1000.
According to the PIN diode of the present embodiment, by forming at least two p-type ion ranges, Ran Houzai in N-type substrate P-type injection region is formed above p-type ion range, so, when PIN diode loads reverse biased, except the meeting of p-type injection region Formed with N-type substrate outside depletion region, p-type ion range also can form depletion region with N-type substrate, so, can increase depletion region Width, and then improve PIN diode resistance to pressure.In addition, under identical breakdown voltage, due to depositing for p-type ion range In the concentration when concentration of p-type injection region can be lower than without p-type ion range, in such manner, it is possible to reduce PIN diode just To pressure drop.
Finally it should be noted that:The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations;Although The present invention is described in detail with reference to the foregoing embodiments, it will be understood by those within the art that:It still may be used To be modified to the technical scheme described in foregoing embodiments, or equivalent substitution is carried out to which part technical characteristic; And these modifications or replacement, the essence of appropriate technical solution is departed from the scope of various embodiments of the present invention technical scheme.

Claims (10)

  1. A kind of 1. preparation method of PIN diode, it is characterised in that including:
    At least two p-type ion ranges are formed in N-type substrate;
    P-type injection region is formed in the N-type substrate, the p-type injection region connects above each p-type ion range Touch each p-type ion range;
    The first metal layer as a lateral electrode is formed on the p-type injection region, and in the N-type substrate away from the p-type The side of injection region forms the second metal layer as another lateral electrode.
  2. 2. preparation method according to claim 1, it is characterised in that described that p-type ion range bag is formed in N-type substrate Include:
    Mask layer is formed in the N-type substrate;
    Photoetching process is carried out to mask layer, forms at least two injection windows;
    By the injection window to the N-type substrate implanting p-type ion, the p-type ion range is formed;
    The mask layer is removed, and carries out annealing process.
  3. 3. preparation method according to claim 2, it is characterised in that the spacing between each injection window is the note Enter 3-5 times of window width.
  4. 4. preparation method according to claim 2, it is characterised in that the concentration of the p-type injection region and the p-type from The ratio between sub- concentration is 100-1000.
  5. 5. according to the preparation method any one of claim 1-4, it is characterised in that the N-type substrate includes:N+ types serve as a contrast The N-type epitaxial layer of bottom and formation on the N+ types substrate.
  6. A kind of 6. PIN diode, it is characterised in that including:
    N-type substrate;
    At least two p-type ion ranges, in N-type substrate;
    P-type injection region, in N-type substrate, the p-type injection region contacts each institute above each p-type ion range State p-type ion range;
    The first metal layer, on p-type injection region;
    Second metal layer, the side away from the p-type injection region in N-type substrate.
  7. 7. PIN diode according to claim 6, it is characterised in that the spacing between each p-type ion range is institute State the width of p-type ion range 3-5 times.
  8. 8. PIN diode according to claim 6, it is characterised in that the concentration of the p-type injection region and the p-type The ratio between ion concentration is 100-1000.
  9. 9. according to the PIN diode any one of claim 6-8, it is characterised in that the N-type substrate includes:N+ types The N-type epitaxial layer of substrate and formation on the N+ types substrate.
  10. 10. according to the PIN diode any one of claim 6-8, it is characterised in that the concentration of the p-type injection region For 1012Atom/cm2-1013Atom/cm2
CN201610676716.2A 2016-08-16 2016-08-16 The preparation method and PIN diode of PIN diode Pending CN107768245A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610676716.2A CN107768245A (en) 2016-08-16 2016-08-16 The preparation method and PIN diode of PIN diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610676716.2A CN107768245A (en) 2016-08-16 2016-08-16 The preparation method and PIN diode of PIN diode

Publications (1)

Publication Number Publication Date
CN107768245A true CN107768245A (en) 2018-03-06

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003298072A (en) * 2002-04-02 2003-10-17 Toshiba Corp Semiconductor device
US20030207536A1 (en) * 1999-01-11 2003-11-06 Fuji Electric, Co., Ltd. Semiconductor device with alternating conductivity type layer and method of manufacturing the same
CN103295884A (en) * 2012-03-02 2013-09-11 株式会社东芝 Method of manufacturing semiconductor device
CN103515448A (en) * 2012-06-22 2014-01-15 英飞凌科技股份有限公司 Electrical device and method for manufacturing same
CN104183652A (en) * 2014-09-17 2014-12-03 中航(重庆)微电子有限公司 PIN device with super junction and preparation method of PIN device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030207536A1 (en) * 1999-01-11 2003-11-06 Fuji Electric, Co., Ltd. Semiconductor device with alternating conductivity type layer and method of manufacturing the same
JP2003298072A (en) * 2002-04-02 2003-10-17 Toshiba Corp Semiconductor device
CN103295884A (en) * 2012-03-02 2013-09-11 株式会社东芝 Method of manufacturing semiconductor device
CN103515448A (en) * 2012-06-22 2014-01-15 英飞凌科技股份有限公司 Electrical device and method for manufacturing same
CN104183652A (en) * 2014-09-17 2014-12-03 中航(重庆)微电子有限公司 PIN device with super junction and preparation method of PIN device

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Application publication date: 20180306

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