CN107765133A - A kind of failure detector and method - Google Patents
A kind of failure detector and method Download PDFInfo
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- CN107765133A CN107765133A CN201710991899.1A CN201710991899A CN107765133A CN 107765133 A CN107765133 A CN 107765133A CN 201710991899 A CN201710991899 A CN 201710991899A CN 107765133 A CN107765133 A CN 107765133A
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- processor
- circuit
- amplifying circuit
- failure detector
- data sampling
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/62—Testing of transformers
Abstract
The present invention relates to a kind of failure detector and method, belong to technical field of electric power automation.The failure detector includes:At least one current transformer and device Host, the device Host include:Data sampling device, processor, display device and power module.Each current transformer is connected with the data sampling device, and the data sampling device is connected with the processor, and the processor is connected with the display device.The power module respectively with the data sampling device, the processor and the display device.Compared with prior art, the failure detector can be accurately judged to which kind of earth fault CT secondary circuit multipoint earth faults belong to, it is very convenient, efficient, eliminating conventional method needs to have a power failure, solves the operation such as line, it is strong to reduce maintainer's work, substantially reduce the number the time that maintainer eliminates CT secondary circuit multipoint earth faults.
Description
Technical field
The invention belongs to technical field of electric power automation, and in particular to a kind of failure detector and method.
Background technology
According to the regulation of " relay protection of power system and automatic safety device anti-accident measures main points ":Current transformer and
The secondary circuit of voltage transformer must have and can only have one point earth, but due to reasons such as constructions, often result in transformer two
Multipoint earth faults occur for minor loop, and the safe operation to system brings serious harm.
It is to use to stop electrolytic wire that traditional CT multipoint earth faults, which search judgment mode, and carrying out insulation status with megger judges
Mode, judge that secondary loop of mutual inductor whether there is multipoint earth faults.It is complicated that this method searches judgment mode, need to be by
Root branch road carries out solution line, and workload is big, it is necessary to expend substantial amounts of manpower and materials and time.
The content of the invention
In consideration of it, it is an object of the invention to provide a kind of failure detector and method, effectively to improve above-mentioned ask
Topic.
What embodiments of the invention were realized in:
The embodiments of the invention provide a kind of failure detector, including:At least one current transformer and device Host,
The device Host includes:Data sampling device, processor, display device and power module.Each current transformer is equal
It is connected with the data sampling device, the data sampling device is connected with the processor, the processor and the display
Device connects.The power module respectively with the data sampling device, the processor and the display device.It is described at least
One current transformer is used to gather by A phase, B phase, C phase and the electric current of the power network of N phase compositions.The data sampling device is used for
Data sampling is carried out to the electric current, obtains sample rate current.The processor is used to be adopted to described according to preset failure information table
Sample electric current is compared, and comparison result is sent into the display device.
In preferred embodiments of the present invention, the device Host also includes:Warning device, the warning device with it is described
Processor connects, when the processor according to the preset failure information table to draw the sample rate current be abnormal current when, control
The warning device alarm.
In preferred embodiments of the present invention, the data sampling device includes:Sample circuit and amplifying circuit, it is described to adopt
Sample circuit is connected with least one current transformer, and the sample circuit also connects with the first input end of the amplifying circuit
Connect, the output end of the amplifying circuit is connected with the processor.
In preferred embodiments of the present invention, the amplifying circuit includes:One-level amplifying circuit and second amplifying circuit, institute
The first input end for stating one-level amplifying circuit is connected with the sample circuit, the output end of the one-level amplifying circuit respectively with institute
The first input end that processor is stated with the second amplifying circuit connects, the output end of the second amplifying circuit and the processing
Device is connected, and the second input of the one-level amplifying circuit is connected with its output end, the second input of the second amplifying circuit
End is connected with its output end.
In preferred embodiments of the present invention, the data sampling device also includes:A/d converter, the a/d converter point
The output end of output end, the second amplifying circuit not with the one-level amplifying circuit and it is connected with the processor.
In preferred embodiments of the present invention, the device Host includes:Memory, the processor and the memory
Connection.
In preferred embodiments of the present invention, the device Host also includes:Data-out port, the data output end
Mouth is connected with the processor.
In preferred embodiments of the present invention, the device Host also includes:Input unit, the input unit with it is described
Processor connects.
In preferred embodiments of the present invention, the device Host also includes:Communication module, the communication module with it is described
Processor connects.
The embodiments of the invention provide a kind of fault detection method, applied to above-mentioned failure detector, methods described
Including:The data sampling device samples to the electric current of at least one current transformer collection, and is adopted what is obtained
Sample electric current is transferred to the processor;The sample rate current is compared according to preset failure information table for the processor, and
Comparison result is sent to the display device.
Failure detector provided in an embodiment of the present invention and method, compared with prior art, the failure detector exist
When detecting CT secondary circuit multipoint earth faults, current transformer need to be only connected with the phase line in power network and N, data sampling
Device can obtain sample rate current, then believe based on preset failure by processor to carry out data sampling to the electric current in power network
Obtained sample rate current is compared breath table, you can is accurately judged to which kind of ground connection CT secondary circuit multipoint earth faults belong to
Failure, very convenient, efficient, eliminating conventional method needs to have a power failure, solves the operation such as line, reduces maintainer's work by force, largely
Reduce the time that maintainer eliminates CT secondary circuit multipoint earth faults.
Other features and advantages of the present invention will illustrate in subsequent specification, also, partly become from specification
It is clear that or understood by implementing the embodiment of the present invention.The purpose of the present invention and other advantages can be by being write
Specifically noted structure is realized and obtained in specification, claims and accompanying drawing.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to institute in embodiment
The accompanying drawing needed to use is briefly described, it should be apparent that, drawings in the following description are only some implementations of the present invention
Example, for those of ordinary skill in the art, on the premise of not paying creative work, can also be obtained according to these accompanying drawings
Obtain other accompanying drawings.By the way that shown in accompanying drawing, above and other purpose of the invention, feature and advantage will become apparent from.In whole
Identical reference instruction identical part in accompanying drawing.Deliberately accompanying drawing, emphasis are not drawn by actual size equal proportion scaling
It is the purport for showing the present invention.
Fig. 1 shows a kind of structured flowchart of failure detector provided in an embodiment of the present invention.
Fig. 2 shows the structured flowchart of device Host provided in an embodiment of the present invention.
Fig. 3 shows the circuit theory diagrams of data sampling device provided in an embodiment of the present invention.
Fig. 4 shows in power network provided in an embodiment of the present invention circuit feature figure during without multipoint earthing.
Fig. 5 shows circuit feature figure during phase line one point earth in power network provided in an embodiment of the present invention.
Fig. 6 shows equivalent circuit diagram during phase line one point earth in power network provided in an embodiment of the present invention.
Fig. 7 shows circuit feature figure during N lines one point earth in power network provided in an embodiment of the present invention.
Fig. 8 shows equivalent circuit diagram during N lines one point earth in power network provided in an embodiment of the present invention.
Fig. 9 shows circuit feature figure during phase line two points ground fault in power network provided in an embodiment of the present invention.
Figure 10 shows equivalent circuit diagram during phase line two points ground fault in power network provided in an embodiment of the present invention.
Figure 11 shows circuit feature figure during N lines two points ground fault in power network provided in an embodiment of the present invention.
Figure 12 shows equivalent circuit diagram during N lines two points ground fault in power network provided in an embodiment of the present invention.
Figure 13 shows circuit spy during phase line one point earth+N line one point earths in power network provided in an embodiment of the present invention
Sign figure.
Figure 14 shows equivalent electric during phase line one point earth+N line one point earths in power network provided in an embodiment of the present invention
Lu Tu.
Figure 15 shows circuit feature figure during 3 points of ground connection of phase line in power network provided in an embodiment of the present invention.
Figure 16 shows equivalent circuit diagram during 3 points of ground connection of phase line in power network provided in an embodiment of the present invention.
Figure 17 shows circuit spy during phase line two points ground fault+N line one point earths in power network provided in an embodiment of the present invention
Sign figure.
Figure 18 shows equivalent electric during phase line two points ground fault+N line one point earths in power network provided in an embodiment of the present invention
Lu Tu.
Figure 19 shows a kind of method flow diagram of fault detection method provided in an embodiment of the present invention.
Icon:100- failure detectors;110- current transformers;120- device Hosts;121- data samplings fill
Put;1211- sample circuits;1212- amplifying circuits;1213-AD converters;122- processors;123- display devices;
124- warning devices;125- memories;126- data-out ports;127- input units;128- communication modules;129-
Power module.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
Part of the embodiment of the present invention, rather than whole embodiments.The present invention implementation being generally described and illustrated herein in the accompanying drawings
The component of example can be configured to arrange and design with a variety of.
Therefore, below the detailed description of the embodiments of the invention to providing in the accompanying drawings be not intended to limit it is claimed
The scope of the present invention, but be merely representative of the present invention selected embodiment.It is common based on the embodiment in the present invention, this area
The every other embodiment that technical staff is obtained under the premise of creative work is not made, belong to the model that the present invention protects
Enclose.
It should be noted that:Similar label and letter represents similar terms in following accompanying drawing, therefore, once a certain Xiang Yi
It is defined, then it further need not be defined and explained in subsequent accompanying drawing in individual accompanying drawing.
In the description of the invention, it is necessary to which explanation, term " on ", " under ", "left", "right", " interior ", " outer " etc. indicate
Orientation or position relationship be based on orientation shown in the drawings or position relationship, or the invention product using when usually put
Orientation or position relationship, be for only for ease of the description present invention and simplify description, rather than instruction or imply signified device
Or element there must be specific orientation, with specific azimuth configuration and operation, therefore it is not considered as limiting the invention.
In addition, term " first ", " second ", " the 3rd " etc. are only used for distinguishing description, and it is not intended that indicating or implying relatively important
Property.
In the description of the invention, it is also necessary to explanation, unless otherwise clearly defined and limited, term " setting ",
" installation ", " connected ", " connection " should be interpreted broadly, for example, it may be fixedly connected or be detachably connected, or one
Connect body;Can be mechanical connection or electrical connection;Can be joined directly together, can also be indirect by intermediary
It is connected, can is the connection of two element internals.For the ordinary skill in the art, on being understood with concrete condition
State the concrete meaning of term in the present invention.
The embodiments of the invention provide a kind of failure detector 100, as shown in Figure 1.The failure detector 100 wraps
Include:Current transformer 110 and device Host 120.
The current transformer 110 is connected with the device Host 120, and the current transformer 110 is used to gather by A
Phase, B phases, the electric current of C phases and the power network of N phase compositions.Wherein, the current transformer 110 is open type current transformer.The opening
Formula current transformer can be equivalent to pliers, directly be held in A phase, B phase, C phase and/or N phases during use.The Current Mutual Inductance
The quantity of device 110 can be 1,2,3 and 4.When 4 above-mentioned phases are within close proximity, a Current Mutual Inductance can be used
Device 110 clamps its whole.Can be that a current transformer 110 clamps when the quantity of current transformer 110 is 4
In on a line, for example, current transformer 1 is held in A phases, current transformer 2 is held in B phases, and current transformer 3 clamps
In in C phases, current transformer 4 is held in N phases.In the present embodiment, only illustrated by taking 1 current transformer 110 as an example,
Therefore the failure detector 100 of example in figure can not be understood as being limitation of the present invention.
As shown in Fig. 2 the device Host 120 includes:Data sampling device 121, processor 122, display device 123,
Warning device 124, memory 125, data-out port 126, input unit 127, communication module 128 and power module 129.
The data sampling device 121 is connected with the current transformer 110, for being gathered to current transformer 110
Electric current carry out data sampling, obtain sample rate current, and send it to the processor 122.It is optional in the present embodiment
Ground, as shown in figure 3, the data sampling device 121 includes:Sample circuit 1211, amplifying circuit 1212 and a/d converter 1213.
The sample circuit 1211 samples to the electric current of current transformer 110, and delivers this to the amplification electricity
Road 1212.In the present embodiment, the sample circuit 1211 includes:First resistor R1, second resistance R2,3rd resistor R3,
Four resistance R4 and the 5th resistance R5.
The amplifying circuit 1212 is used to be conveyed to AD turns after being amplified processing to the electric current that sample circuit 1211 gathers
Parallel operation 1213.The first input end of the amplifying circuit 1212 is connected with the sample circuit 1211, the amplifying circuit 1212
Output end be connected with the a/d converter 1213, the second input of the amplifying circuit 1212 is connected with its output end, institute
The second input for stating amplifying circuit 1212 is also grounded.In the present embodiment, alternatively, the amplifying circuit 1212 includes:One-level
Amplifying circuit, second amplifying circuit.
The first input end of the one-level amplifying circuit is connected with the sample circuit 1211, the one-level amplifying circuit
First input end of the output end respectively with the a/d converter 1213 and the second amplifying circuit is connected, the one-level amplification electricity
Second input on road is connected with its output end, in addition, the second input of the one-level amplifying circuit is also grounded.
The output end of the second amplifying circuit is connected with the a/d converter 1213, and the second of the second amplifying circuit
Input is connected with its output end, in addition, the second input of the second amplifying circuit is also grounded.
The a/d converter 1213 is used to the analog signal that amplifying circuit 1212 exports being converted to data signal, further
Ground, the signal of the output end output through one-level amplifying circuit is first input end input of the high current through a/d converter 1213, small
Electric current amplifies the second input input through the a/d converter 1213, the a/d converter 1213 by second amplifying circuit again
Output end be connected with processor 122.
Wherein, it should be appreciated that the a/d converter 1213 in above-mentioned can be using the place for being built-in with AD conversion chip
Reason device 122 substitutes, that is, does not need the a/d converter 1213, using the processor 122 that possesses AD conversion function, now,
The output end of amplifying circuit 1212 is directly connected with processor 122, further, one-level amplification circuit output end and two level amplification
The output end of circuit is connected with processor 122.
Wherein it is preferred to which above-mentioned first input end is input in the same direction, the second input is reverse input end.
The processor 122 is used to the sample rate current be compared according to preset failure information table, and is tied comparing
Fruit is sent to the display device 123.Further, processor 122 is according to utilization circuit superposition theorem analysis circuit characteristic quantity
The sample rate current is compared the fault message table of acquisition, judges that CT secondary circuits whether there is multipoint earthing, and will
The result of comparison is sent to the display device 123.And show that the sample rate current is different according to the preset failure information table
During normal electric current, the warning device 124 is controlled to alarm.And it is additionally operable to data being sent to ancillary equipment through communication module 128.
Wherein, the ancillary equipment, include but is not limited to:PC, tablet personal computer, smart mobile phone etc..
Wherein, the processor 122 can be a kind of IC chip, have the disposal ability of signal.Above-mentioned place
Reason device 122 can be general processor, including central processing unit (Central Processing Unit, CPU), network processes
Device (Network Processor, NP) etc.;Can also be digital signal processor (Digital Signal Processing,
DSP), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), ready-made programmable gate
Array (Field Programmable Gate Array, FPGA) either other PLDs, discrete gate or crystal
Pipe logical device, discrete hardware components.General processor can be microprocessor or the processor 122 can also be it is any often
Processor of rule etc..In the present embodiment, it is preferable that the processor 122 can be the processor of STM32 series, such as
The models such as STM32F103C8T6, STM32F103VET6.
Wherein, above-mentioned preset failure information table is under the various ground fault conditions according to CT secondary circuits, in circuit
Electric current change setting table.The preset failure information table is obtained based on circuit superposition theorem, i.e., in linear circuit,
When the electric current (or voltage) of any branch road can regard that each independent current source acts solely on circuit in circuit as, in the branch road
The superposition of caused electric current (or voltage).When analyzing the effect of some power supply, remaining power supply is considered as zero, and voltage source is zero to be considered as
Short circuit.Current source is zero to be considered as open circuit.Stacked system be it is arbitrary, can independent source independent role one at a time, can also one
Secondary several independent sources act on simultaneously, easy depending on calculating analysis.Below in conjunction with various concrete conditions to the electricity in circuit
The change of stream is described in detail.
When circuit is without multipoint earthing, its circuit feature figure as shown in figure 4, in circuit only have current source independent role, thirdly
Phase out-of-balance current IORepresent.Analyze its circuit feature amount IGroundWith InRespectively:In=Ia+Ib+Ic=I0;IGround=0.
During phase line one point earth, in the present embodiment, only illustrated by taking A phase one point earths as an example, its circuit feature figure is such as
Shown in Fig. 5.Earth mat electrical potential difference between A phase faults earth point and protective ground point is equivalent to voltage source Ud, its equivalent electric
Road figure is as shown in Figure 6.Short circuit is considered as according to superposition theorem voltage source, is that (a) is tried to achieve by circuit reduction during current source independent role
I in figuren1And IGround 1.And current source is considered as open circuit in voltage source independent role, circuit reduction tries to achieve I in figure for figure (b)n2And
IGround 2.Then In=In1+In2=Ib+Ic- Ud/Rln=I0- Ia- Ud/Rln;IGround=IGround 1+IGround 2=Ia+Ud/Rln=Ia+Ud/Rln。
During N line one point earths, its circuit feature figure is as shown in fig. 7, its equivalent circuit diagram is as shown in Figure 8.Wherein, by N lines
Earth mat electrical potential difference between fault ground point and fail-safe earth point is equivalent to voltage source Ud.It is considered as according to superposition theorem voltage source
Short circuit, it is (a) by circuit reduction during current source independent role, tries to achieve I in (a)n1And IGround 1.It is and electric in voltage source independent role
Stream source is considered as open circuit, and circuit reduction is that (b) tries to achieve I in (b)n2And IGround 2.Then In=In1+In2=0-Ud/Rln=-Ud/Rln;
IGround=IGround 1+IGround 2=Ia+Ib+Ic+Ud/Rln=I0+Ud/Rln。
Phase line two points ground fault, in the present embodiment, only illustrated so that simultaneously one point earth occurs for A, B two-phase as an example, its electricity
Road characteristic pattern is as shown in figure 9, its equivalent circuit diagram is as shown in Figure 10.Wherein Ud1For fault ground point 1. with protective ground point
Between earth mat electrical potential difference equivalent voltage source.Ud2For fault ground point 2. between protective ground point earth mat electrical potential difference etc.
Imitate voltage source.Using circuit add-up principle by during current source independent role and Ud1、Ud2Independent role, in Figure 10 (a), (b),
(c).Counting circuit characteristic quantity In1、In2、In3And IGround 1、IGround 2、IGround 3After circuit feature when being overlapped to obtain phase line two points ground fault
Measure In、IGround.Then In=In1+In2+In3=Ic- Ud1/Rln- Ud2/Rln;
IGround=IGround 1+IGround 2+IGround 3=Ia+Ib+Ud1/Rln+Ud2/Rln=I0- Ic+Ud1/Rln+Ud2/Rln。
During N line two points ground faults, its circuit feature figure is as shown in figure 11, and its equivalent circuit diagram is as shown in figure 12.N lines are 1., 2.
2 points have a fault ground point, protective ground point and fault ground point 1. between N lines conductor resistance be Rln1, earth mat potential
Difference is Ud1.Fault ground point 1. with fault ground point 2. between N lines conductor resistance be Rln2, protective ground point connects with failure
Place 2. between earth mat electrical potential difference be Ud2Respectively in current source, voltage source Ud1, voltage source Ud2In the presence of as Figure 12 (a),
(b), then (c) counting circuit characteristic quantity is overlapped and can obtained:
In=In1+In2+In3=0-Ud1/Rln1- Ud2/(Rln1+Rln2);
IGround=IGround 1+IGround 2+IGround 3=Ia+Ib+Ic+Ud1/Rln1+Ud2/(Rln1+Rln2)。
During phase line one point earth+N line one point earths, in the present embodiment, only by taking A phase one point earth+N line one point earths as an example
Illustrate, its circuit feature figure is as shown in figure 13, and its equivalent circuit diagram is as shown in figure 14.Ud1It is N lines fault ground point and guarantor
The earth mat electrical potential difference equivalent voltage source protected between earth point, Ud2Earth mat electricity between A phase faults earth point and protective grounding point
Potential difference equivalent voltage source.Respectively in current source, voltage source Ud1, voltage source Ud2In the presence of as Figure 14 (a), (b), (c) calculate electricity
Then road characteristic quantity is overlapped and can obtained:
In=In1+In2+In3=0-Ud1/Rln- Ud2/Rln=-(Ud1+Ud2)/Rln;
IGround=IGround 1+IGround 2+IGround 3=Ia+Ib+Ic+Ud1/Rln+Ud2/Rln=I0+(Ud1+Ud2)/Rln。
During 3 points of ground connection of phase line, its circuit feature figure is as shown in figure 15, and its equivalent circuit diagram is as shown in figure 16.Ud1For A phases
Earth mat electrical potential difference equivalent voltage source between fault ground point and protective grounding point, Ud2For B phase faults earth point and protective grounding
Earth mat electrical potential difference equivalent voltage source between point, Ud3Earth mat electrical potential difference between C phase faults earth point and protective grounding point etc.
Imitate voltage source.Respectively in current source, voltage source Ud1, voltage source Ud2, voltage source Ud3In the presence of as Figure 16 (a), (b), (c),
(d) then counting circuit characteristic quantity is overlapped and can obtained:In=- (Ud1+Ud2+Ud3)/Rln;
IGround=I0+(Ud1+Ud2+Ud3)/Rln。
During 2 points of+N line one point earths of phase line, in the present embodiment, only by taking A, B two-phase one point earth+N line one point earths as an example
Illustrate, its circuit feature figure is as shown in figure 17, and its equivalent circuit diagram is as shown in figure 18.Ud1It is N lines fault ground point and guarantor
The earth mat electrical potential difference equivalent voltage source protected between earth point, Ud2Earth mat electricity between B phase faults earth point and protective grounding point
Potential difference equivalent voltage source, Ud3Earth mat electrical potential difference equivalent voltage source between A phase faults earth point and protective grounding point.Respectively
In current source, voltage source Ud1, voltage source Ud2, voltage source Ud3In the presence of as Figure 18 (a), (b), (c), (d) counting circuit it is special
Sign amount and then it is overlapped and can obtains:In=- (Ud1+Ud2+Ud3)/Rln;
IGround=I0+(Ud1+Ud2+Ud3)/Rln。
By the way that characteristic quantity calculates result and characteristic quantity under normal condition under various CT second loop groundings states is calculated
As shown in table 1, when Ud and I being present0When, I before and after ground connectionGroundAnd InAmplitude obvious change be present.
Table 1
IGround | In | |
Normal condition | 0 | I0 |
Phase line one point earth | Ia+Ud/Rln | I0-Ia–Ud/Rln |
N line one point earths | I0+Ud/Rln | -Ud/Rln |
Phase line two points ground fault | I0-Ic+Ud1/Rln+Ud2/Rln | Ic–Ud1/Rln-Ud2/Rln |
N line two points ground faults | I0+Ud1/Rln1+Ud2/(Rln1+Rln2) | -Ud1/Rln1-Ud2/(Rln1+Rln2) |
A bit+N line one point earth of phase line | I0+(Ud1+Ud2)/Rln | -(Ud1+Ud2)/Rln |
3 points of ground connection of phase line | -(Ud1+Ud2+Ud3)/Rln | I0+(Ud1+Ud2+Ud3)/Rln |
2 points of+N line one point earths of phase line | -(Ud1+Ud2+Ud3)/Rln | I0+(Ud1+Ud2+Ud3)/Rln |
For the CT of the overwhelming majority, the three-phase of its secondary circuit is in a basic balance, it is contemplated that being I under three-phase equilibrium state0
Situation when=0, characteristic quantity contrast is as shown in table 2 before and after ground connection.
Table 2
IGround | In | |
Normal condition | 0 | 0 |
Phase line one point earth | Ia+Ud/Rln | -Ia–Ud/Rln |
N line one point earths | Ud/Rln | -Ud/Rln |
Phase line two points ground fault | -Ic+Ud1/Rln+Ud2/Rln | Ic–Ud1/Rln-Ud2/Rln |
N line two points ground faults | Ud1/Rln1+Ud2/(Rln1+Rln2) | -Ud1/Rln1-Ud2/(Rln1+Rln2) |
A bit+N line one point earth of phase line | (Ud1+Ud2)/Rln | -(Ud1+Ud2)/Rln |
3 points of ground connection of phase line | -(Ud1+Ud2+Ud3)/Rln | (Ud1+Ud2+Ud3)/Rln |
2 points of+N line one point earths of phase line | -(Ud1+Ud2+Ud3)/Rln | (Ud1+Ud2+Ud3)/Rln |
It can be seen that when three-phase balance, I before ground connectionGroundAnd InIt is 0, I after generation is groundedGroundAnd InFor equal in magnitude, side
To one group of opposite electric current.Based on above-mentioned analysis, it is seen that, under every kind of malfunction, the electric current in circuit can also become therewith
Change, therefore can be as judging to whether there is failure in secondary circuit, and be the fault message table of which kind of failure.Can be with
Understand, the part in the simply fault message table shown in above-mentioned, remaining failure situation can be according to above-mentioned side
Method is calculated, and is no longer illustrated one by one herein.
Referring again to Fig. 3, the display device 123 is used for display data, operation interface etc., so that user is in operation circle
Data input, and comparison result of the processing of video-stream processor 122 etc. are carried out on face.Wherein, the display device 123 can be mesh
The display devices such as the preceding touch-screen commonly used on the market, display screen.
The warning device 124 is connected with the processor 122, when the processor 122 is believed according to the preset failure
Breath table draws the sample rate current when being abnormal current, and the processor 122 controls the warning device 124 to send alarm.
Wherein, the mode of the prompting can be combination of auditory tone cues or signal lamp flash for prompting, or both etc..Yu Ben
In embodiment, the warning device 124 can be audible-visual annunciator or buzzer, can also be warning lamp, Huo Zheyou
The device of buzzer and warning lamp composition.It is not further qualified herein.
The memory 125 is used for data storage information, for example, the fault message table of advance typing is stored, and processing
Result handled by device 122.Wherein, the memory 125 can be a kind of IC chip, have storage capacity.Above-mentioned
Memory 125 may be, but not limited to, random access memory (Random Access Memory, RAM), read-only storage
(Read Only Memory, ROM), programmable read only memory (Programmable Read-Only Memory, PROM),
Erasable read-only memory (Erasable Programmable Read-Only Memory, EPROM), electric erasable is read-only
Memory (Electric Erasable Programmable Read-OnlyMemory, EEPROM), flash memory (Flash
Memory) etc..In the present embodiment, it is preferable that the memory 125 is flash memory, i.e. flash storage.
For the ease of data transfer, and it is the equipment charges such as mobile phone, alternatively, the failure detector 100 also includes
Data-out port 126, such as USB interface.The data-out port 126 respectively with the power module 129 and the processing
Device 122 connects, to realize the transmission of data, and charge function.
The input unit 127 is used to input Various types of data and parameter setting etc., so that processor 122 receives these
Data or parameter setting etc..The input unit 127 can be physical button, for example, keyboard;Can also be virtual key, for example,
Touch-screen.
The communication module 128 be used for communicated with ancillary equipment, i.e., processor 122 by the communication module 128 with
Ancillary equipment is communicated.Wherein, the communication module 128 can be WiFi module, ZigBee module, 3G module, 4G modules, or
Person other meet the wireless transport module of condition.In the present embodiment, it is preferable that the communication module 128 can be 3G module,
For example, it may be the 3G module of the model such as SIM6320C, CEM631, CEM600, WIDE M8800, FWP103, K3G, WM9881.
The power module 129 respectively with above-mentioned input unit 127, processor 122, display device 123, memory
125th, communication module 128, warning device 124 and data sampling apparatus 121 connect, and are powered for it, to ensure its normal work.Can
Selection of land, the power module 129 are rechargable power supplies, for example, lithium battery.
Second embodiment
Figure 19 is referred to, the embodiment of the present invention additionally provides a kind of failure detector being applied in above-described embodiment
100 fault detection method.Below in conjunction with figure to its institute comprising the step of illustrate.
Step S101:The data sampling device samples to the electric current of at least one current transformer collection,
And obtained sample rate current is transferred to the processor.
The circuit that data acquisition device gathers to current transformer is sampled (predominantly by amplification, AD conversion), is obtained
To sample rate current, and it is transmitted to processor.
Step S102:The sample rate current is compared according to preset failure information table for the processor, and will compare
As a result it is sent to the display device.
The processor receives the sample rate current of data acquisition device transmission, just according to default fault message table pair
The electric current is compared, namely the failure that the electric current belongs to that type is searched from the fault message table, and its failure is believed
Breath is sent to display device and shown, and can also be alarmed by warning device.
The preferred embodiments of the present invention are the foregoing is only, are not intended to limit the invention, for the skill of this area
For art personnel, the present invention can have various modifications and variations.Within the spirit and principles of the invention, that is made any repaiies
Change, equivalent substitution, improvement etc., should be included in the scope of the protection.
Claims (10)
- A kind of 1. failure detector, it is characterised in that including:At least one current transformer and device Host, the equipment Main frame includes:Data sampling device, processor, display device and power module, each current transformer with the number Being connected according to sampling apparatus, the data sampling device is connected with the processor, and the processor is connected with the display device, The power module respectively with the data sampling device, the processor and the display device;At least one current transformer is used to gather by A phase, B phase, C phase and the electric current of the power network of N phase compositions;The data sampling device is used to carry out data sampling to the electric current, obtains sample rate current;The processor is used to the sample rate current be compared according to preset failure information table, and comparison result is sent to The display device.
- 2. failure detector according to claim 1, it is characterised in that the device Host also includes:Warning device, The warning device is connected with the processor, when the processor draws the sample rate current according to the preset failure information table For abnormal current when, control the warning device to alarm.
- 3. failure detector according to claim 1, it is characterised in that the data sampling device includes:Sampling electricity Road and amplifying circuit, the sample circuit are connected with least one current transformer, and the sample circuit is also put with described The first input end connection of big circuit, the output end of the amplifying circuit are connected with the processor.
- 4. failure detector according to claim 3, it is characterised in that the amplifying circuit includes:One-level amplification electricity Road and second amplifying circuit, the first input end of the one-level amplifying circuit are connected with the sample circuit, the one-level amplification First input end of the output end of circuit respectively with the processor and the second amplifying circuit is connected, the two level amplification electricity The output end on road is connected with the processor, and the second input of the one-level amplifying circuit is connected with its output end, and described two Second input of level amplifying circuit is connected with its output end.
- 5. failure detector according to claim 4, it is characterised in that the data sampling device also includes:AD turns Parallel operation, the a/d converter respectively the output end with the one-level amplifying circuit, the output end of the second amplifying circuit and It is connected with the processor.
- 6. failure detector according to claim 1, it is characterised in that the device Host includes:Memory, it is described Processor is connected with the memory.
- 7. failure detector according to claim 1, it is characterised in that the device Host also includes:Data output Port, the data-out port are connected with the processor.
- 8. failure detector according to claim 1, it is characterised in that the device Host also includes:Input unit, The input unit is connected with the processor.
- 9. according to the failure detector described in claim 1-8 any one, it is characterised in that the device Host also wraps Include:Communication module, the communication module are connected with the processor.
- 10. a kind of fault detection method, it is characterised in that applied to the fault detect as described in claim 1-9 any one Device, methods described include:The data sampling device samples to the electric current of at least one current transformer collection, and the sampling that will be obtained Electric current is transferred to the processor;The sample rate current is compared according to preset failure information table for the processor, and comparison result is sent to described Display device.
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