CN107758606B

CN107758606B - Packaging method of pressure sensor

Info

Publication number: CN107758606B
Application number: CN201610693394.2A
Authority: CN
Inventors: 刘孟彬; 毛剑宏
Original assignee: Lexvu Opto Microelectronics Technology Shanghai Co Ltd
Current assignee: Zhejiang Core Microelectronics Co ltd
Priority date: 2016-08-19
Filing date: 2016-08-19
Publication date: 2020-01-24
Anticipated expiration: 2036-08-19
Also published as: CN107758606A

Abstract

The invention discloses a packaging method of a pressure sensor, wherein a substrate is bonded on a passivation layer, the substrate covers a first opening to form a second cavity, so that the second cavity of the pressure sensor is sealed through the substrate, and the complexity of a packaging process is reduced through a wafer-level packaging method; and the through hole structures are formed in the substrate and the passivation layer, so that the electrical property of the device structure can be led out, the chip (control circuit) and the pressure sensor are integrated in the longitudinal direction, and the transverse area of the packaging structure is reduced.

Description

Packaging method of pressure sensor

Technical Field

The invention relates to the technical field of micro-electro-mechanical systems, in particular to a packaging method of a pressure sensor.

Background

Micro Electro Mechanical Systems (MEMS) are a leading-edge research field of multidisciplinary crossing developed on the basis of microelectronic technology, and are a technology for manufacturing micro electromechanical devices by using semiconductor process. Compared with the traditional electromechanical device, the MEMS device has obvious advantages in the aspects of high temperature resistance, small volume and low power consumption. After decades of development, the method has become one of the major scientific and technological fields of world attention, relates to various subjects and technologies such as electronics, machinery, materials, physics, chemistry, biology, medicine and the like, and has wide application prospects.

A pressure sensor is a transducer that converts a pressure signal into an electrical signal. The sensor is divided into a resistance type pressure sensor and a capacitance type pressure sensor according to different working principles. Among them, the principle of the capacitive pressure sensor is to measure pressure by changing the capacitance between the top electrode and the bottom electrode by pressure.

In order to integrate the MEMS device with other devices, the MEMS device is often integrated with the CMOS device, and the integrated device is packaged. In the prior art, a chip (chip) integrating an MEMS device and a CMOS device is independently packaged, and the packaging method is complex, high in cost and low in efficiency.

Disclosure of Invention

The invention aims to provide a packaging method of a pressure sensor, which reduces the transverse size of a device, realizes wafer-level packaging, improves the performance of the device and reduces the cost.

In order to solve the above technical problem, the present invention provides a method for packaging a pressure sensor, including:

providing a semiconductor wafer, wherein the semiconductor wafer comprises a plurality of chips, each chip comprises an induction area and a packaging area, a control circuit and an interlayer dielectric layer positioned on the control circuit are arranged in each chip, a first interconnection structure is formed in each interlayer dielectric layer, the top of each first interconnection structure is exposed out of each interlayer dielectric layer in each packaging area, each first interconnection structure is electrically connected with the control circuit, a passivation layer is formed on each chip, a first cavity is formed between each passivation layer and each interlayer dielectric layer in each induction area, a top electrode is formed on the top wall of each first cavity, and a bottom electrode is formed on the bottom wall of each first cavity;

selectively etching the passivation layer to form a first opening and a second opening in the passivation layer, wherein the second opening is located in the first opening, the first opening is located at least on a portion of the first cavity, and the second opening exposes a portion of the top electrode on the first cavity;

forming a passivation layer through hole in the passivation layer on the encapsulation region, the passivation layer through hole exposing the top of the first interconnection structure;

bonding a substrate on the passivation layer, wherein the substrate covers the first opening to form a second cavity;

forming a substrate through hole in the substrate on the packaging area, wherein the substrate through hole is communicated with the passivation layer through hole;

filling a conductive material in the substrate through hole and the passivation layer through hole to form a through hole structure;

and forming a gasket on the substrate, wherein the gasket is communicated with the through hole structure.

Further, a vent hole is formed in the substrate on the sensing area, and the vent hole is communicated with the second cavity.

Further, before the step of forming a substrate via hole in the substrate on the package region, the method further includes:

and thinning one surface of the substrate deviating from the passivation layer.

Further, after the step of forming the spacer on the substrate, the method further includes:

and forming a protective layer on the substrate, wherein the protective layer exposes the gasket, and at least part of the substrate on the sensing area is exposed by the protective layer.

Further, the chip wafer level packaging method further includes:

bonding the gasket with a circuit board through a welding part;

and cutting the semiconductor wafer, the passivation layer, the substrate and the circuit board to form the single-grain pressure sensor wafer-level packaging structure.

Further, the substrate is a wafer.

Further, a substrate is bonded on the passivation layer by fusion bonding.

Further, the temperature of the melt bonding is 200 ℃ to 450 ℃.

Furthermore, the interlayer dielectric layer further comprises a second interconnection structure and a third interconnection structure, the second interconnection structure and the third interconnection structure are respectively electrically connected with the control circuit, the second interconnection structure is electrically connected with the bottom electrode, and the third interconnection structure is electrically connected with the top electrode.

Further, the conductive material is one or more of copper, tungsten and molybdenum.

Compared with the prior art, the packaging method of the pressure sensor provided by the invention has the following advantages:

in the packaging method of the pressure sensor, a substrate is bonded on the passivation layer, the substrate covers the first opening to form a second cavity, so that the second cavity of the pressure sensor is sealed through the substrate, and the complexity of a packaging process is reduced through a wafer-level packaging method; and the through hole structures are formed in the substrate and the passivation layer, so that the electrical property of the device structure can be led out, the chip (control circuit) and the pressure sensor are integrated in the longitudinal direction, and the transverse area of the packaging structure is reduced.

Drawings

FIG. 1 is a flow chart of a method for packaging a pressure sensor according to an embodiment of the present invention;

fig. 2 to 9 are schematic diagrams of device structures in a packaging method of a pressure sensor according to an embodiment of the invention.

Detailed Description

The method of packaging a pressure sensor of the present invention will now be described in more detail with reference to the schematic drawings, in which preferred embodiments of the invention are shown, it being understood that a person skilled in the art may modify the invention described herein while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.

In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.

The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

The invention provides a packaging method of a pressure sensor, as shown in figure 1, comprising the following steps:

step S11, providing a semiconductor wafer, where the semiconductor wafer includes a plurality of chips, where each chip includes an induction area and a package area, a control circuit and an interlayer dielectric layer on the control circuit are disposed in each chip, a first interconnection structure is formed in the interlayer dielectric layer, the interlayer dielectric layer in the package area exposes out of the top of the first interconnection structure, the first interconnection structure is electrically connected to the control circuit, a passivation layer is formed on the chip, a first cavity is formed between the passivation layer and the interlayer dielectric layer in the induction area, a top electrode is formed on the top wall of the first cavity, and a bottom electrode is formed on the bottom wall of the first cavity;

step S12, selectively etching the passivation layer to form a first opening and a second opening in the passivation layer, where the second opening is located in the first opening, the first opening is located at least on a portion of the first cavity, and the second opening exposes a portion of the top electrode on the first cavity;

step S13, forming a passivation layer through hole in the passivation layer on the packaging region, wherein the passivation layer through hole exposes the top of the first interconnection structure;

step S14, bonding a substrate on the passivation layer, wherein the substrate covers the first opening to form a second cavity;

step S15, forming a substrate through hole in the substrate on the packaging area, wherein the substrate through hole is conducted with the passivation layer through hole;

step S16, filling conductive materials in the substrate through hole and the passivation layer through hole to form a through hole structure;

step S17, forming a pad on the substrate, the pad conducting the through hole structure.

The following describes a method for packaging a pressure sensor according to the present invention with reference to fig. 2 to 9, where fig. 2 to 9 are schematic diagrams of device structures in the method for packaging a pressure sensor according to an embodiment of the present invention.

First, step S11 is performed, as shown in fig. 2, step S11 is performed to provide a semiconductor wafer 100, where the semiconductor wafer 100 includes a plurality of chips 1A (for clearly indicating the content of the present application, only one first chip 1A is shown in fig. 2, and it can be understood by those skilled in the art that the first wafer 100 has a plurality of first chips 1A, and a scribe lane may be disposed between adjacent first chips 1A, which is not described herein again). The chip 1A includes a sensing region 100a and a packaging region 100b, in this embodiment, the packaging region 100b surrounds the sensing region 100a, and in other embodiments, the arrangement of the packaging region 100b and the sensing region 100a is not limited to the arrangement shown in fig. 2.

In the embodiment, the semiconductor wafer 100 is used to provide a CMOS device, the control circuit 110 is a CMOS circuit, and the CMOS circuit includes a source, a drain, a gate, and other structures, which can be understood by those skilled in the art and are not described herein. In addition, other device structures, such as amplifiers, digital-to-analog converters, analog processing circuits and/or digital processing circuits, interface circuits, etc., may be formed in the semiconductor wafer 100, and the methods for forming these device structures may be CMOS processes.

The interlayer dielectric layer 120 is generally made of an oxide, a first interconnection structure 101 is formed in the interlayer dielectric layer 120, the interlayer dielectric layer 120 of the package region 100b exposes the top of the first interconnection structure 101, and the first interconnection structure 101 is electrically connected to the control circuit 110. In this embodiment, the interlayer dielectric layer 120 further includes a second interconnect structure 102 and a third interconnect structure 103, and the second interconnect structure 102 and the third interconnect structure 103 are electrically connected to the control circuit 110, respectively. The first interconnect structure 101, the second interconnect structure 102, and the third interconnect structure 103 may include plugs V1, V2, interconnect lines M1, M2, and the like, and the specific structures thereof need to be determined according to actual situations, and the first interconnect structure 101, the second interconnect structure 102, and the third interconnect structure 103 in fig. 2 are only for illustrative purposes and do not limit the present invention.

As shown in fig. 2, a passivation layer 200 is formed on the chip 1A, and the passivation layer 200 is used as a dielectric layer of the MEMS pressure sensor. The passivation layer 200 may be made of oxide, oxynitride, or the like, a first cavity 150 is formed between the passivation layer 200 and the interlayer dielectric layer 120 of the sensing region 100a, a top electrode 140 is formed on a top wall of the first cavity 150, and a bottom electrode 130 is formed on a bottom wall of the first cavity 150. The second interconnect structure 102 is electrically connected to the bottom electrode 130 to conduct the control circuit 110 and the bottom electrode 130, and the third interconnect structure 103 is electrically connected to the top electrode 140 to conduct the control circuit 110 and the top electrode 140.

In fig. 2, the top electrode 140 is further located on the sidewall of the first cavity 150 and the interlayer dielectric layer 120 beside the first cavity 150, the top of the third interconnect structure 103 is connected to the top electrode 140 beside the first cavity 150, and the top electrode 140 supports the structure of the first cavity 150. In other embodiments of the present invention, the structure of the top electrode 140 and the forming manner of the first cavity 150 are not limited to the structure shown in fig. 2, and may be changed as needed by a person skilled in the art, which is not described herein.

The material of the top electrode 140 is typically polysilicon. In a preferred embodiment, the thickness of the bottom electrode 130 is 0.1 μm to 4 μm. The material of the bottom electrode 130 is selected from one of the metals of aluminum, titanium, zinc, silver, gold, copper, tungsten, cobalt, nickel, tantalum, platinum, or any combination thereof; or, the conductive nonmetal is selected from polysilicon, amorphous silicon, polycrystalline silicon germanium, amorphous silicon germanium or any combination thereof; or, a combination of one of the metal, the conductive nonmetal and any combination thereof and an insulating layer; but are not limited to these materials and may be other materials known to those skilled in the art.

The bottom electrode 130 can be prepared by the following steps: a bottom electrode film is first formed on the interlayer dielectric layer 120, and then the bottom electrode film is selectively etched to form the bottom electrode 130. When the material of the bottom electrode 130 and the material of the interconnect layer M2 on top of the third interconnect structure 103 are the same, the bottom electrode 130 and the interconnect layer M2 on top of the third interconnect structure 103 may be formed simultaneously.

Then, step S12 is performed, as shown in fig. 3, the passivation layer 200 is selectively etched, and a first opening 201' and a second opening 202 are formed in the passivation layer 200 for being used as a sensing window of the MEMS pressure sensor. The second opening 202 is located in the first opening 201 ', the first opening 201' is located at least on a portion of the first cavity 150, and the second opening 202 exposes a portion of the top electrode 140 on the first cavity 150. Wherein, the first opening 201' may be formed first, and then the second opening 202 may be formed; or forming the second opening 202 first and then forming the first opening 201'; or an integrated process (all in one) is adopted, and the first opening 201' and the second opening 202 are formed at the same time.

Next, in step S13, as shown in fig. 3, a passivation layer via 203 is formed in the passivation layer 200 on the package region 100b, and the passivation layer via 203 exposes the top of the first interconnect structure 101. In a preferred embodiment, the steps S12 and S13 can be performed simultaneously.

Then, step S14 is performed, as shown in fig. 4, a substrate 300 is bonded on the passivation layer 200, the substrate 300 covers the first opening 201 ', and the first opening 201' forms the second cavity 201. Preferably, the substrate 300 is a wafer, and the wafer has better mechanical and electrical properties, and in other embodiments, the substrate 300 may also be a glass substrate or the like.

In this embodiment, a substrate 300 is bonded on the passivation layer 200 by fusion bonding. For example, when the substrate 300 and the passivation layer 200 are heated, the Si-H bond and the H-O bond on the surfaces of the substrate 300 and the passivation layer 200 are broken, and then the surfaces of the substrate 300 and the passivation layer 200 are bonded together, the Si-O bond on the surface of the substrate 300 and the surface-O bond of the passivation layer 200 form a Si-O bond, so that the van der waals force on the surfaces of the substrate 300 and the passivation layer 200 is changed into a covalent bond, thereby bonding the substrate 300 and the passivation layer 200, and further, the temperature of the melting process is 200 ℃ to 450 ℃, for example, 300 ℃, which is low and does not damage the semiconductor wafer 100.

In other embodiments, the substrate 300 and the passivation layer 200 may be bonded by an adhesive layer or the like, which is not described herein. If necessary, the side of the substrate 300 facing away from the passivation layer 200 may also be thinned.

Then, step S15 is performed, as shown in fig. 5, a substrate via hole 301 is formed in the substrate 300 on the package region 100b, and the substrate via hole 301 and the passivation layer via hole 203 are conducted. Specifically, the substrate through hole 301 may be prepared by a deep silicon etching process or the like.

Next, step S16 is performed, as shown in fig. 6, a conductive material is filled in the substrate via 301 and the passivation layer via 203 to form a via structure 400, wherein the conductive material is one or more of copper, tungsten, and molybdenum, and the via structure 400 electrically leads the control circuit 110 out of the substrate 300.

Thereafter, step S17 is performed, as shown in fig. 7, a gasket 500 is formed on the substrate 300, and the gasket 500 is used to connect the through hole structure 400 for bonding a bonding portion. Specifically, the spacer 500 may be formed by first forming a conductive film on the substrate 300 and then selectively etching the conductive film.

Preferably, as shown in fig. 8, a protection layer 600 is formed on the substrate 300, the protection layer 600 exposes the pad 500, and the protection layer 600 exposes at least a portion of the substrate 300 on the sensing region 100 a. Specifically, the protective layer 600 may be formed by first forming a protective layer film on the substrate 300 and then selectively etching the protective layer film.

Subsequently, as shown in fig. 9, a vent hole 302 is formed on the substrate 300 on the sensing region 100a, and the vent hole 302 is communicated with the second cavity 201. Specifically, the vent holes 302 may be prepared by a deep silicon etching process or the like.

Further, the chip wafer level packaging method further includes:

the gasket 500 is bonded to a circuit board by a bonding portion. Specifically, the soldering portion is a micro bump, and it is conceivable to prepare the soldering portion on the pad 500 by a micro bump process, and then solder the soldering portion to the circuit board.

And cutting the semiconductor wafer 100, the passivation layer 200, the substrate 300 and the circuit board to form a single-grain pressure sensor wafer-level packaging structure.

The preferred embodiment of the present invention is described above, but the present invention is not limited to the above disclosure, and for example, it is within the scope of the present invention to bond a substrate 300 on the passivation layer 200, and then simultaneously etch the substrate 200 and the passivation layer 200, and simultaneously form the substrate via 301 and the passivation layer via 203.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A method of packaging a pressure sensor, comprising:

providing a semiconductor wafer, wherein the semiconductor wafer comprises a plurality of chips, each chip comprises an induction area and a packaging area, a control circuit and an interlayer dielectric layer positioned on the control circuit are arranged in each chip, a first interconnection structure is formed in each interlayer dielectric layer, the top of each first interconnection structure is exposed out of the interlayer dielectric layer in each packaging area, each first interconnection structure is electrically connected with the control circuit, a passivation layer is formed on each chip, a first cavity is formed between each passivation layer and the corresponding interlayer dielectric layer in each induction area, a top electrode is formed on the top wall of each first cavity, and a bottom electrode is formed on the bottom wall of each first cavity;

2. The method of packaging a pressure sensor of claim 1, wherein a vent hole is formed in the substrate above the sensing area, the vent hole communicating with the second cavity.

3. The method of packaging a pressure sensor of claim 1, wherein prior to the step of forming a substrate via in the substrate on the package region, further comprising:

and thinning one surface of the substrate deviating from the passivation layer.

4. The method of packaging a pressure sensor according to any one of claims 1 to 3, further comprising, after the step of forming a spacer on the substrate:

5. The method of packaging a pressure sensor of claim 1, further comprising:

bonding the gasket with a circuit board through a welding part;

6. The method of packaging a pressure sensor of claim 1, wherein the substrate is a wafer.

7. The method of packaging a pressure sensor of claim 1, wherein a substrate is bonded to the passivation layer by fusion bonding.

8. The method of packaging a pressure sensor of claim 7, wherein the temperature of the fusion bonding is 200 ℃ to 450 ℃.

9. The method of packaging a pressure sensor of claim 1, wherein the interlevel dielectric layer further comprises a second interconnect structure and a third interconnect structure, the second interconnect structure and the third interconnect structure being electrically connected to the control circuit, respectively, the second interconnect structure being electrically connected to the bottom electrode, and the third interconnect structure being electrically connected to the top electrode.

10. The method for packaging a pressure sensor according to claim 1, wherein the conductive material is one or more of copper, tungsten, and molybdenum.