CN107731784A - A kind of semiconductor devices anti-fuse structures and preparation method thereof - Google Patents
A kind of semiconductor devices anti-fuse structures and preparation method thereof Download PDFInfo
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- CN107731784A CN107731784A CN201711046556.4A CN201711046556A CN107731784A CN 107731784 A CN107731784 A CN 107731784A CN 201711046556 A CN201711046556 A CN 201711046556A CN 107731784 A CN107731784 A CN 107731784A
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- layer
- contact hole
- area
- semiconductor substrate
- antifuse
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 121
- 238000002360 preparation method Methods 0.000 title claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 88
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 26
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims description 43
- 230000004888 barrier function Effects 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 22
- 238000004519 manufacturing process Methods 0.000 claims description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 10
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 7
- 229910021332 silicide Inorganic materials 0.000 claims description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 239000004411 aluminium Substances 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 5
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 229910052697 platinum Inorganic materials 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical group O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims 2
- 238000009413 insulation Methods 0.000 claims 1
- 239000004408 titanium dioxide Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 239000000377 silicon dioxide Substances 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 8
- 239000003989 dielectric material Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 239000002648 laminated material Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000000116 mitigating effect Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
Abstract
The present invention, which provides a kind of semiconductor devices anti-fuse structures and preparation method, preparation, to be included：Semi-conductive substrate is provided, there is active area and isolated area；In defining an antifuse configuring area in Semiconductor substrate, a groove structure for surrounding antifuse configuring area is formed, antifuse configuring area includes the Part I in active area and the Part II extended in isolated area；Dielectric layer and conductive layer are formed in the bottom of groove structure and partial sidewalls；Conductive layer and the first contact hole are electrically connected in being formed in isolated area, second contact hole with side of the groove structure away from the first contact hole in formation in active area with the second spacing.Pass through such scheme, the present invention passes through one jiao of setting protuberance in flush type metal wire, tie point when can be turned on control circuit, first contact hole is arranged in isolated area, stability during ensureing break-over of device, its preparation can be completed in the preparation flow of the flush type character line of memory, without increasing extra processing step.
Description
Technical field
The invention belongs to ic manufacturing technology field, more particularly to a kind of semiconductor devices anti-fuse structures and its
Preparation method.
Background technology
It is well known that nonvolatile memory can still preserve its data content after power is turned off.In general, when non-
Volatile memory manufacture is completed and after dispatching from the factory, and user can program (program) nonvolatile memory, and then by number
According to record in the nonvolatile memory.And according to the number of programming, nonvolatile memory can further discriminate between for：Repeatedly compile
Memory (multi-time programmable memory, abbreviation MTP memory), the memory of one-time programming of journey
(Mask ROM are stored for (onetime programmable memory, abbreviation otp memory) or mask read-only storage
Device).
Otp memory part can be classified as fuse-type otp memory part or anti-fuse type otp memory part.Including
Each memory cell in fuse-type otp memory part can provide short circuit before it is programmed, and can be in its quilt
Open circuit is provided after programming.On the contrary, each memory cell being included in anti-fuse type otp memory part can be compiled at it
Open circuit is provided before journey, and short circuit can be provided after it is programmed.In view of the feature of MOS transistor, CMOS technology
Go for the manufacture of anti-fuse type otp memory part.
And as DRAM spare memory cells control, anti-fuse structures are most important, and in the prior art, there is antifuse knot
Not the problems such as when structure turns on, firing point position is not known, and conducting circuit is single, and device is unstable after conducting, in addition, existing skill
The preparation of antifuse device structure in art mostly independently of the preparation technology flow of other devices outside, complex process, production
Cycle is grown, and cost is higher.
Therefore, how a kind of anti-fuse structures and preparation method thereof are provided, it is real to solve above mentioned problem of the prior art
Category is necessary.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide a kind of semiconductor devices antifuse knot
Structure and preparation method thereof, for solving, anti-fuse structures connectivity points in the prior art are not known and device is unstable after line conduction
And the problems such as anti-fuse structures preparation technology complexity.
In order to achieve the above objects and other related objects, the present invention provides a kind of preparation of semiconductor devices anti-fuse structures
Method, comprise the following steps：
1) semi-conductive substrate is provided, the Semiconductor substrate has active area and the isolation positioned at active area periphery
Area；
2) in defining an antifuse configuring area in the Semiconductor substrate, and one is formed around the antifuse configuring area
Groove structure, wherein, the antifuse configuring area includes Part I in the active area and with being connected described the
One end of a part and the Part II extended in the isolated area；
3) continuous dielectric layer is formed in the bottom of the groove structure and partial sidewalls, and is filled in the dielectric layer
Conductive layer, the top of the conductive layer are less than the upper surface of the Semiconductor substrate；And
4) it is electrically connected to the conductive layer and has the of the first spacing with the active area in being formed in the isolated area
One contact hole, and in forming the second contact hole in the active area, second contact hole is with the groove structure away from institute
The side for stating the first contact hole has the second spacing.
As a preferred embodiment of the present invention, in step 2), the step of forming the groove structure：
2-1) in being correspondingly formed the first mask layer on the antifuse configuring area, and formed in the semiconductor substrate surface
Cover the top of first mask layer and the second mask layer of side wall；
Second mask layer and first mask layer at the top of first mask layer 2-2) are removed, to retain
The second mask layer is stated to be formed in the part of the side of first mask layer；
2-3) in step 2-2) surface one layer of the 3rd mask layer of deposition of structure is obtained, separately make the upper of the 3rd mask layer
Surface is not higher than the upper surface of remaining second mask layer；
Remaining second mask layer 2-4) is removed, to obtain groove opening；And
2-5) continue to etch the Semiconductor substrate by the groove opening, with the Semiconductor substrate formed with
The corresponding groove structure of the groove opening.
As a preferred embodiment of the present invention, step 2-3) in, formed three mask layer the step of include：Prior to
Step 2-2) threeth mask layer of surface one layer height of formation higher than remaining second mask layer of structure is obtained, then
Part the 3rd mask layer is removed using flatening process until exposing the top of remaining second mask layer,
To obtain the 3rd mask layer.
As a preferred embodiment of the present invention, in step 2), the groove structure of formation includes ring part and convex
Go out portion, wherein, the ring part surround the lateral wall of the antifuse configuring area, and the protruding parts is close in the ring part
There is the 3rd spacing on the lateral wall of the side of second contact hole and between the protuberance and second contact hole.
As a preferred embodiment of the present invention, in step 1), also it is included in the semiconductor substrate surface and forms one layer
The step of etching barrier layer.
As a preferred embodiment of the present invention, in step 3), in addition to before the filling conductive layer, in the medium
Layer surface forms the step of one layer of cementing layer.
As a preferred embodiment of the present invention, the top of the dielectric layer is less than the upper surface of the Semiconductor substrate；
Also it is included in the step of step 3) obtains surface one layer of filling perforation insulating barrier of formation of structure, the filling perforation insulating barrier is filled in described
The top of groove structure and the upper surface for extending to the Semiconductor substrate.
As a preferred embodiment of the present invention, in step 4), first spacing is 0.3~30 nanometer；Described second
Spacing is 0.3~30 nanometer.
As a preferred embodiment of the present invention, the depth of the isolated area for the semiconductive substrate thickness 50%~
90%；The length in the isolated area of the Part II of the antifuse configuring area is the Part II total length
10%~50%；The width of the groove structure is the 10%~50% of the width of the antifuse configuring area；The groove knot
The depth of structure is the 30%~70% of the semiconductive substrate thickness；The top of the dielectric layer and the conductive layer and described half
The distance between conductor substrate surface is the 20%~60% of the groove structure depth；The thickness of the dielectric layer is the ditch
The 0.1%~10% of slot structure width.
As a preferred embodiment of the present invention, the making of the process implementing of step 1)~step 4) in flush type character line
In.
The present invention also provides a kind of semiconductor device structure, and the semiconductor device structure includes：
Semiconductor substrate, there is active area and the isolated area positioned at active area periphery；Antifuse configuring area, is defined in
In the Semiconductor substrate, the antifuse configuring area include Part I in the active area and be connected described in
One end of Part I and the Part II extended in the isolated area；Groove structure, in the Semiconductor substrate, and
Around the outer rim for being arranged at the antifuse configuring area；
Dielectric layer and conductive layer, the dielectric layer are incorporated into bottom and the partial sidewalls of the groove structure, the conduction
Layer is filled in the dielectric layer, and the surface of the Semiconductor substrate is below at the top of the dielectric layer and the conductive layer；
And
First contact hole and the second contact hole, first contact hole are electrically connected to described in the isolated area and led
There is the first spacing in electric layer and with the active area, second contact hole be located in the active area and with the groove knot
Side of the structure away from first contact hole has the second spacing.
As a preferred embodiment of the present invention, the groove structure includes ring part and protuberance, wherein, the ring
Shape portion is around the lateral wall of the antifuse configuring area, and the protruding parts is in the ring part close to second contact hole
There is the 3rd spacing on the lateral wall of side and between the protuberance and second contact hole.
As a preferred embodiment of the present invention, the top of the dielectric layer is less than the upper surface of the Semiconductor substrate；
The semiconductor devices anti-fuse structures also include filling perforation insulating barrier, are filled in the top of the groove structure and extend to described
The upper surface of Semiconductor substrate, wherein, first contact hole electrically connects through the filling perforation insulating barrier with the conductive layer, institute
The second contact hole is stated through the filling perforation insulating barrier and is extended in the active area.
As a preferred embodiment of the present invention, one layer of gluing is also formed between the dielectric layer and the conductive layer
Layer.
As a preferred embodiment of the present invention, the material of the cementing layer includes titanium nitride.
As a preferred embodiment of the present invention, the material of the conductive layer be selected from tungsten, titanium, nickel, aluminium, platinum, silicon titanium nitride,
At least one of group that metal nitride, metal silicide and DOPOS doped polycrystalline silicon are formed；The resistance of the conductive layer
Rate is 2 × 10-8Ω m~1 × 102Ωm；；In the group that the material of the dielectric layer is formed selected from silica, hafnium oxide
It is at least one.
As a preferred embodiment of the present invention, first contact hole is identical with the structure of second contact hole, bag
Include conductive pole and lateral wall and the bonding layer of bottom positioned at the conductive pole.
As a preferred embodiment of the present invention, first spacing is 0.3~30 nanometer；Second spacing is 0.3
~30 nanometers.
As described above, semiconductor structure of the present invention and preparation method thereof, has the advantages that：
The present invention semiconductor device structure, can be used as DRAM spare memory cells control anti-fuse structures, by
One jiao of its flush type metal wire is arranged to projective structure, tie point when being turned on so as to control circuit, and by by
One contact hole is arranged in the isolated area for having the first spacing with active area, stability during ensureing break-over of device, meanwhile, lead to
The setting of two flush type metal wires is crossed, circuit selects most short one after can making line conduction；In addition, the present invention's partly leads
The preparation of body device architecture can be completed in the preparation flow of the flush type character line of memory, without increasing extra technique
Step, so as to simplify preparation technology, the production cycle is shortened, reduces production cost.
Brief description of the drawings
Fig. 1 is shown as flow chart prepared by the semiconductor device structure of the present invention.
Fig. 2 is shown as providing the structural representation of Semiconductor substrate in the semiconductor device structure preparation of the present invention.
Fig. 3 is shown as the schematic diagram of the antifuse configuring area defined in the semiconductor device structure preparation of the present invention.
Fig. 4 is shown as the top view of the groove structure formed in the semiconductor device structure preparation of the present invention.
Fig. 5 is shown as being formed the structural representation of the first mask layer in the semiconductor device structure preparation of the present invention.
Fig. 6 is shown as the sectional view in A-A ' directions in structure shown in Fig. 5.
Fig. 7 is shown as the sectional view in B-B ' directions in structure shown in Fig. 5.
Fig. 8 is shown as being formed the structural representation of the second mask layer in the semiconductor device structure preparation of the present invention.
Fig. 9 is shown as the sectional view in A-A ' directions in structure shown in Fig. 8.
Figure 10 is shown as the sectional view in B-B ' directions in structure shown in Fig. 8.
Figure 11 is shown as being formed the structure of remaining second mask layer in the sectional view in A-A ' directions in structure shown in Fig. 8
Figure.
Figure 12 is shown as being formed the structure of remaining second mask layer in the sectional view in B-B ' directions in structure shown in Fig. 8
Figure.
Figure 13 is shown as being formed the structure chart of the first mask layer in the sectional view in A-A ' directions in structure shown in Fig. 8.
Figure 14 is shown as being formed the structure chart of the first mask layer in the sectional view in B-B ' directions in structure shown in Fig. 8.
Figure 15 is shown as being formed the structure chart of the first mask layer in the sectional view in A-A ' directions in structure shown in Fig. 8.
Figure 16 is shown as being formed the structure chart of the first mask layer in the sectional view in B-B ' directions in structure shown in Fig. 8.
Figure 17 is shown as being formed the structure chart of groove opening in the sectional view in A-A ' directions in structure shown in Fig. 8.
Figure 18 is shown as being formed the structure chart of groove opening in the sectional view in B-B ' directions in structure shown in Fig. 8.
Figure 19 is shown as being formed the structure chart of groove structure in the sectional view in A-A ' directions in structure shown in Fig. 8.
Figure 20 is shown as being formed the structure chart of groove structure in the sectional view in B-B ' directions in structure shown in Fig. 8.
Figure 21 is shown as being formed the structure chart of dielectric layer in the sectional view in A-A ' directions in structure shown in Fig. 8.
Figure 22 is shown as being formed the structure chart of dielectric layer in the sectional view in B-B ' directions in structure shown in Fig. 8.
Figure 23 is shown as being formed the structure chart of cementing layer in the sectional view in A-A ' directions in structure shown in Fig. 8.
Figure 24 is shown as being formed the structure chart of cementing layer in the sectional view in B-B ' directions in structure shown in Fig. 8.
Figure 25 is shown as being formed the structure chart of conductive layer in the sectional view in A-A ' directions in structure shown in Fig. 8.
Figure 26 is shown as being formed the structure chart of conductive layer in the sectional view in B-B ' directions in structure shown in Fig. 8.
Figure 27 is shown as being formed the vertical view of first, second contact hole in prepared by semiconductor device structure provided by the invention
Figure.
Figure 28 is shown as the sectional view in A-A ' directions in structure shown in Figure 27.
Figure 29 is shown as the sectional view in B-B ' directions in structure shown in Figure 27.
Component label instructions
1 Semiconductor substrate
11 active areas
12 isolated areas
13 antifuse configuring areas
131 Part II
132 Part I
21 first mask layers
The Part I of 211 first mask layers
The Part II of 212 first mask layers
31 etching barrier layers
41 second mask layers
42 remaining second mask layers
51 the 3rd mask layers
52 the 3rd mask layers
61 groove openings
71 groove structures
711 ring parts
712 protuberances
81 dielectric layers
82 cementing layers
83 conductive layers
91 first contact holes
92 second contact holes
S1~S4 steps 1)~step 4)
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Fig. 1 is referred to Figure 29.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, though only showing the component relevant with the present invention in diagram rather than according to package count during actual implement
Mesh, shape and size are drawn, and form, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout form may also be increasingly complex.
As shown in figure 1, the present invention provides a kind of preparation method of semiconductor devices anti-fuse structures, comprise the following steps：
1) semi-conductive substrate is provided, the Semiconductor substrate has active area and the isolation positioned at active area periphery
Area；
2) in defining an antifuse configuring area in the Semiconductor substrate, and one is formed around the antifuse configuring area
Groove structure, wherein, the antifuse configuring area includes Part I in the active area and with being connected described the
One end of a part and the Part II extended in the isolated area；
3) continuous dielectric layer is formed in the bottom of the groove structure and partial sidewalls, and is filled in the dielectric layer
Conductive layer, the top of the conductive layer are less than the upper surface of the Semiconductor substrate；And
4) it is electrically connected to the conductive layer and has the of the first spacing with the active area in being formed in the isolated area
One contact hole, and in forming the second contact hole in the active area, second contact hole is with the groove structure away from institute
The side for stating the first contact hole has the second spacing.
Describe semiconductor device structure of the present invention and preparation method thereof in detail below in conjunction with accompanying drawing.
As shown in S1 and Fig. 2 in Fig. 1, step 1) is carried out, there is provided semi-conductive substrate 1, the Semiconductor substrate 1 have
Active area 11 and the isolated area 12 positioned at the periphery of active area 11；
Specifically, the material of the Semiconductor substrate 1 of the present invention includes but is not limited to monocrystalline or polycrystalline semiconductor material, separately
Outside, the substrate 1 can also be intrinsic monocrystalline substrate either light dope silicon substrate, can also be silicon-on-insulator,
The backing material well known within the skill of those ordinarily skilled such as germanium silicon, the active area 11 include the material with element doping, this
In embodiment, the material of the Semiconductor substrate 1 is single crystal silicon material.In addition, the channel separating zone 12 can be shallow trench
Isolation structure, including shallow trench and the dielectric material that is filled in the shallow trench, the K values of the dielectric material are typically less than
3, it act as isolating shallow trench electric leakage and mitigating being electrically coupled (coupling), and the dielectric material can be silica material
Deng.In addition, periphery here refers to the abducent region of active region sidewalls, the active area and the isolated area side connect
Touch.
As an example, the depth of the isolated area 12 is the 50%~90% of the thickness of Semiconductor substrate 1.
Specifically, the depth of the isolated area 12 is preferably the 60%~80% of the thickness of Semiconductor substrate 1, so as to control
Degree of isolation between transistor processed, it is ensured that part of the invention such as the first contact hole realizes its function, is selected in this example
The depth for selecting the isolated area 12 is the 70% of the thickness of Semiconductor substrate 1.
As an example, in step 1), also it is included in the step that the surface of Semiconductor substrate 1 forms one layer of etching barrier layer 31
Suddenly.
Specifically, the step of whole surface for being additionally included in Semiconductor substrate 1 deposits one layer of etching barrier layer 31, its material
Including but not limited to silicon nitride, the etching barrier layer 31 are used to protect Semiconductor substrate in the techniques such as follow-up etching are carried out
It is injury-free, so as to the stability of further retainer member performance.
As shown in the S2 in Fig. 1 and Fig. 3~20, step 2) is carried out, is matched somebody with somebody in defining an antifuse in the Semiconductor substrate 1
Area 13 is put, and forms a groove structure 71 for surrounding the antifuse configuring area 13, wherein, the antifuse configuring area 13 includes
Part I 132 in the active area 11 and it is connected with one end of the Part I 132 and extends to described
Part II 131 in isolated area 12；
Specifically, the purpose of the step is the semiconductor device structure for the application, such as anti-fuse structures, there is provided forms two
The groove of bar flush type metal wire, wherein, the antifuse configuring area 13 is used to define the groove structure 71 being subsequently formed
Shape and position, so as to finally determine the positions of two flush type metal wires.In addition, the Part I and described
Part II is preferably orthogonal, the shape of the antifuse configuring area 13 can be L-type, with the shape such as L-type minute surface is symmetrical
Shape, certainly, the Part II can also have certain non-perpendicular angle in other embodiments with the Part I,
It is preferably the antifuse configuring area 13 of the two vertical L-type in this example.
As an example, in step 2), the step of forming groove structure 71, specifically includes：
2-1) in being correspondingly formed the first mask layer 21 on the antifuse configuring area 13, and in the table of Semiconductor substrate 1
Face forms the second mask layer 41 of the top for covering first mask layer 21 and side wall, wherein, second mask layer 41 is right
The region of Semiconductor substrate 1 described in Ying Yu is used to be subsequently formed the groove structure 71, as shown in Fig. 5~10；
Second mask layer 41 at the top of the first mask layer 21 and first mask layer 21 2-2) are removed, with
Retain second mask layer 41 to be formed in the part of the side of first mask layer 21, as shown in Figure 11~12；
2-3) in step 2-2) surface one layer of the 3rd mask layer 52 of deposition of structure is obtained, separately make the 3rd mask layer 52
Upper surface be not higher than remaining second mask layer 41 upper surface, as shown in Figure 13~16；
Remaining second mask layer 41 2-4) is removed, to obtain groove opening 61, as shown in Figure 17~18；And
2-5) continue to etch the Semiconductor substrate 1 by the groove opening 61, with shape in the Semiconductor substrate 1
Into the groove structure 71 corresponding with the groove opening 61, as shown in Figure 19~20.
Specifically, this example provides a kind of preparation method of groove structure, one layer of first mask layer 21 is deposited first, its
In, first mask layer 21 includes but is not limited to photoresist, and one layer of second mask layer is then covered on the first mask layer 21
41, second mask layer 41 includes but is not limited to SADP (self-aligned double patterning) hard mask, institute
The depositional mode for stating the first mask layer 21 and second mask layer 41 is well known within the skill of those ordinarily skilled any heavy
Product mode.
In addition, in this example, first mask layer 21 also just has due to being correspondingly formed with the antifuse configuring area 13
Corresponding Part I 211 and Part II 212, wherein, the Part I 211 is entirely located in the active area 11, institute
The one end of Part II 212 to be stated with the Part I 211 to be connected, the other end is extended in the isolated area 12, accordingly, by
Cover first mask layer 21 in second mask layer 41, then its it is inevitable also some be located in the active area, one
Part is located in the isolated area, wherein, the part of active area is located at for the first mask layer 21, it is corresponding to be covered in its week side of boss
Second mask layer 41 is also entirely located on the active area, and the part of isolated area, corresponding covering are located at for the first mask layer 21
Also it is entirely located in the isolated area in the second mask layer 41 of its week side of boss, as shown in Figure 8.
Specifically, the step of also including removing first mask layer 21 and the second mask layer of part 41, by these
After the removal of material, the patterning of double exposure is formd, obtained remaining second mask layer 41 is first to cover
Twice of the quantity of film layer 21, so as to the flush type metal wire of the anti-fuse structures needed.Wherein, the first mask is removed
Can use flatening process during second mask layer 41 at the top of layer 21, remove the first mask layer 21 can using ion etching or
The technique of person's wet etching, is not particularly limited herein.It should be noted that this technique and the litho pattern in device array area
Unanimously, the two can be completed in same technique, so as to simplify the complexity of technique, shortened production manufacturing cycle, gone forward side by side
One step reduces device cost, and so that size preferably matches between device, device performance is stable.
As an example, step 2-3) in, formed the 3rd mask layer 52 the step of include：Prior to step 2-2) tied
The surface of structure forms the 3rd mask layer 51 that a layer height is higher than remaining second mask layer 41, then using planarization
Technique removes part the 3rd mask layer 51 until the top of remaining second mask layer 41 is exposed, to obtain
3rd mask layer 52.
Specifically, first in step 2-2) after structure on cover one layer of the 3rd mask layer 51, its material is included but not
It is limited to silica, then exposes the top of the second mask layer 41 by flatening process, ensures that subsequent technique is smoothed out.
As an example, for the antifuse configuring area 13, described vertical 131 length in the isolated area 12
For the 10%~50% of the total length of Part II 131；The width of the groove structure 71 is the antifuse configuring area 13
Width 10%~50%；The depth of the groove structure 71 is the 30%~70% of the thickness of Semiconductor substrate 1.
Specifically, have to i.e. corresponding first mask layer 21 in the antifuse configuring area 13 in isolated area
The limitation of length is to rationally design the position of the first follow-up contact hole, and the anti-fuse structures so as to be stablized are led
Logical stability, described vertical 131 length in the isolated area 12 is preferably the total length of Part II 131
20%~40%, it is 30% in this example；The width of the groove structure 71 is preferably the width of the antifuse configuring area 13
20%~40%, be 30% in this example；The depth of the groove structure 71 is preferably the thickness of Semiconductor substrate 1
40%~60%, it is 50% in this example.The setting of the parameter can match each other, and can obtain the device of stable performance
Structure.
As an example, the groove structure 71 formed includes ring part 711 and on the ring part lateral wall
Protuberance 712, the ring part 711 is surrounded on the lateral wall of the antifuse configuring area 13, and the protuberance 712 is located at institute
Ring part is stated on the lateral wall of the side of second contact hole 92 and the protuberance 712 and second contact hole 92
Between there is the 3rd spacing Z3.
Specifically, in this example, there is provided the groove structure 71 of another shape, at it close to the second contact hole 92
One jiao of setting, one protuberance 712, so as to ensure that the flush type metal wire being subsequently formed has a protuberance 712, due to this
The position of protuberance 712 and second contact hole is closer to, and thereby may be ensured that the connectivity points of anti-fuse structures occur herein
Place, so as to control the communicating position of antifuse device, improve the stability and certainty of antifuse device structure.
As shown in the S3 in Fig. 1 and Figure 22~26, step 3) is carried out, in the bottom of the groove structure 71 and partial sidewalls
Continuous dielectric layer 81 is formed, and in filling conductive layer 83 in the dielectric layer 81, the top of the conductive layer 83 is less than described
The upper surface of Semiconductor substrate 1；
As an example, the top of the dielectric layer 81 is less than the upper surface of the Semiconductor substrate 1, it is preferable that is given an account of
The upper surface flush of matter layer 81 and the conductive layer 83, it is below the upper surface of the Semiconductor substrate 1.
As an example, in step 3), in addition to formed after the dielectric layer 81 and the filling conductive layer 83 before, in described
The surface of dielectric layer 81 forms the step of one layer of cementing layer 82.
Specifically, the purpose of the step is the filling groove structure 71, to obtain the metal wire of flush type, wherein, can
Pass through low pressure gas phase deposition (Low Presure Chemical Vapor Deposition) or plasma gas-phase deposit
(Atomic Layer are made in (Plasma Enhancement Chemical Vapor Deposition) or atomic deposition
) etc. Deposition technique is formed, and the material of the conductive layer 83 is selected from tungsten, titanium, nickel, aluminium, platinum, silicon titanium nitride, nitride metal
In the group that thing, metal silicide (titanium silicide, nickle silicide) and DOPOS doped polycrystalline silicon (N-type polycrystalline silicon, p-type polysilicon) are formed
At least one, certainly, its can be above-mentioned material in two kinds or the laminated material bed of material formed above；The conductive layer 83
Resistivity is 2 × 10-8Ω m~1 × 102Ωm；The group that the material of the dielectric layer 81 is selected from silica, hafnium oxide is formed
At least one of group, or the laminated material bed of material that two kinds of materials are formed.In addition, be additionally included in dielectric layer and conductive layer it
Between form one layer of cementing layer, such as the step of titanium nitride, to improve contact turn-on effect therebetween.
As an example, between the dielectric layer 81 and the top and the surface of the Semiconductor substrate 1 of the conductive layer 83
Distance is the 20%~60% of the depth of groove structure 71；The thickness of the dielectric layer 81 is the width of groove structure 71
0.1%~10%.
Specifically, between the dielectric layer 81 and the top and the surface of the Semiconductor substrate 1 of the conductive layer 83 away from
It is 40% from the 30%~50% of the preferably described depth of groove structure 71, in this example；The thickness of the dielectric layer 81 is preferred
For the 1%~8% of the width of groove structure 71, selection is 5% in this example.
As an example, also it is included in the step of body structure surface that step 3) obtains forms one layer of filling perforation insulating barrier 93, it is described
Filling perforation insulating barrier 93 is filled in the top of the groove structure 71 and extends to the upper surface of the Semiconductor substrate 1.
Specifically, formation filling perforation is exhausted before of the invention being additionally included in prepares the first contact hole 91 and the second contact hole 92
The step of edge layer 93, its material include but is not limited to silica.Wherein, first contact hole 91 insulate through the filling perforation
Layer electrically connects with the conductive layer, and second contact hole 92 is through the filling perforation insulating barrier and extends in the active area.
As shown in the S4 in Fig. 1 and Figure 27~29, step 4) is carried out, is electrically connected in formation in the isolated area 12 described
Conductive layer 83 and first contact hole 91 with the active area 11 with the first spacing Z1, and in formation in the active area 11
Second contact hole 92, second contact hole 92 and side of the groove structure 71 away from first contact hole 91 have the
Two spacing Z2, wherein, for the position relationship between each device architecture of clearer display, other not phases for being omitted in Figure 27
The structure of pass.
As an example, in step 4), first spacing is 0.3~30 nanometer；Second spacing is received for 0.3~30
Rice.
As an example, first contact hole 91 is identical with the structure of second contact hole 92, including conductive pole and
Positioned at the lateral wall of the conductive pole and the bonding layer of bottom.Wherein, the conductive layer material of conductive pole and the flush type metal wire
Material etc. is identical, and the bonding layer is identical with the cementing layer in the flush type metal wire, selects as titanium nitride.
Specifically, this step completes the making of contact hole, so as to complete the semiconductor device structure of the present invention, such as antifuse
The preparation of structure.Wherein, the first spacing and the second spacing rationally are provided with, wherein, the first spacing is preferably 5~20 nanometers,
Second spacing is preferably 5~20 nanometers, and in the present embodiment, first spacing and second spacing are disposed as 10nm, its
In, first spacing refers to first contact hole and connect close to one side of the active area with the active area close to described first
The distance between one side of window is touched, the first contact hole is arranged in the isolated area and keeps the first spacing with active area, is
Because when anti-fuse structures turn on, there is very big electrical potential difference, and the insulating materials of isolated area can alleviate this potential
Influence caused by difference, and the application rationally sets the size of the first spacing, so as to ensure that size of devices, cost and stably
Property.In addition, second spacing refers to that second contact hole leans on close to one side of the isolation structure and the isolation structure
The distance between one side of nearly first contact hole, it is preferably identical with first spacing, so as to ensure that device junction
The matching of component.
As an example, the process implementing of step 1)~step 4) is in the making of flush type character line.
It should be noted that the flush type metal wire of the present invention can have identical knot with existing flush type character line
Structure, using with device array area identical litho pattern and technique, character line can prepared so as to the process step of the invention
While complete, can need not increase other steps, simplify the complexity of existing process, reduce manufacturing cycle, reduce
Cost.
As shown in Fig. 2~29, the present invention also provides a kind of semiconductor device structure, wherein, the semiconductor structure can be with
For the structure being prepared using the method for the present invention, or prepared by other method, the structure being prepared with the present invention
Exemplified by illustrate, the semiconductor device structure includes：
Semiconductor substrate 1, there is active area 11 and the isolated area 12 positioned at active area periphery；Antifuse configuring area
13, it is defined in the Semiconductor substrate 1, the antifuse configuring area 13 includes the Part I in the active area 11
132 and the Part II 131 with being connected one end of the Part I 132 and extending in the isolated area 12, referring to Fig. 3
It is shown；Groove structure 71, set in the Semiconductor substrate 1, and around the antifuse configuring area 13, referring in Fig. 4
Structure shown in；
Dielectric layer 81 and conductive layer 83, the dielectric layer 81 are incorporated into bottom and the partial sidewalls of the groove structure 71,
The conductive layer 83 is filled in the dielectric layer 81, and the top of the conductive layer 83 is less than the upper table of the Semiconductor substrate 1
Face, participate in Figure 24 and Figure 25 sectional view described in；And
First contact hole 91 and the second contact hole 92, first contact hole 91 are electrically connected in the isolated area 12
There is the first spacing on the conductive layer 83 and with the active area 11, second contact hole 92 is located in the active area 11
And there is the second spacing with side of the groove structure 71 away from first contact hole 91, referring to shown in Figure 26~29.
Specifically, semiconductor device structure provided by the invention may be used as anti-fuse structures, it has two flush types
Metal wire, and the first spacing and the second spacing set, wherein, the setting of the first spacing, anti-fuse structures can be prevented
During conducting, the unstable phenomenon of device architecture is caused to occur due to high-tension presence, first contact hole 91 is arranged on
In isolated area, there is scattered alleviation, so as to improving the stability of break-over of device.
Specifically, the material of the Semiconductor substrate 1 of the present invention includes but is not limited to monocrystalline or polycrystalline semiconductor material, separately
Outside, the substrate 1 can also be intrinsic monocrystalline substrate either light dope silicon substrate, can also be silicon-on-insulator,
The backing material well known within the skill of those ordinarily skilled such as germanium silicon, the active area 11 include the material with element doping, this
In embodiment, the material of the Semiconductor substrate 1 is single crystal silicon material.In addition, the channel separating zone 12 can be shallow trench
Isolation structure, including shallow trench and the dielectric material that is filled in the shallow trench, the K values of the dielectric material are typically less than
3, it act as isolating shallow trench electric leakage and mitigating being electrically coupled (coupling), and the dielectric material can be silica material
Deng.In addition, periphery here refers to the abducent region of active region sidewalls, the active area and the isolated area side connect
Touch.
As an example, the groove structure 71 includes ring part 711 and protuberance 712, wherein, the ring part 711
Lateral wall around the antifuse configuring area, the protuberance 712 are located at the ring part close to second contact hole 92
Side lateral wall on and there is between the protuberance 712 and second contact hole 92 the 3rd spacing Z3.
Specifically, in this example, there is provided the groove structure 71 of another shape, at it close to the second contact hole 92
One jiao of setting, one protuberance, so as to ensure that the flush type metal wire being subsequently formed has a protuberance, due to the protuberance
Be closer to the position of second contact hole, thereby may be ensured that anti-fuse structures connectivity points occur here, so as to
To control the communicating position of antifuse device, the stability and certainty of antifuse device structure are improved.
As an example, the top of the dielectric layer 81 is less than the upper surface of the Semiconductor substrate 1, it is preferable that is given an account of
The upper surface flush of matter layer 81 and the conductive layer 83, it is below the upper surface of the Semiconductor substrate 1.
As an example, also include filling perforation insulating barrier 93, it is filled in the top of the groove structure 71 and extends to described half
The upper surface of conductor substrate 1, wherein, first contact hole 91 is electrically connected through the filling perforation insulating barrier 93 with the conductive layer 83
Connect, second contact hole 92 is through the filling perforation insulating barrier 93 and extends in the active area 11.
Specifically, formation filling perforation is exhausted before of the invention being additionally included in prepares the first contact hole 91 and the second contact hole 92
The step of edge layer 93, its material include but is not limited to silica.Wherein, first contact hole 91 insulate through the filling perforation
Layer electrically connects with the conductive layer, and second contact hole 92 is through the filling perforation insulating barrier and extends in the active area.
As an example, one layer of cementing layer 82 is also formed between the dielectric layer 81 and the conductive layer 83.Specifically, institute
Stating the material of cementing layer 82 includes titanium nitride, to improve contact turn-on effect therebetween.
As an example, the material of the conductive layer 83 is selected from tungsten, titanium, nickel, aluminium, platinum, silicon titanium nitride, metal nitride, gold
At least one of group that category silicide and DOPOS doped polycrystalline silicon are formed；The resistivity of the conductive layer 83 is 2 × 10-8Ω
M~1 × 102Ωm；The material of the dielectric layer 81 is selected from least one of silica, the group that hafnium oxide is formed.
Specifically, the material of the conductive layer 83 is selected from tungsten, titanium, nickel, aluminium, platinum, silicon titanium nitride, metal nitride, metal
In the group that silicide (titanium silicide, nickle silicide) and DOPOS doped polycrystalline silicon (N-type polycrystalline silicon, p-type polysilicon) are formed at least
One kind, certainly, it can be two kinds or the laminated material bed of material formed above in above-mentioned material；The resistivity of the conductive layer 83
For 2 × 10-8Ω m~1 × 102Ωm；In the group that the material of the dielectric layer 81 is formed selected from silica, hafnium oxide
It is at least one, or the laminated material bed of material that two kinds of materials are formed.
As an example, first contact hole 91 is identical with the structure of second contact hole 92, including conductive pole and
Positioned at the lateral wall of the conductive pole and the bonding layer of bottom.Wherein, the conductive layer material of conductive pole and the flush type metal wire
Material etc. is identical, and the bonding layer is identical with the cementing layer in the flush type metal wire, selects as titanium nitride.
As an example, first spacing is 0.3~30 nanometer；Second spacing is 0.3~30 nanometer.
Specifically, this step completes the making of contact hole, so as to complete the semiconductor device structure of the present invention, such as antifuse
The preparation of structure.Wherein, the first spacing and the second spacing rationally are provided with, wherein, the first spacing is preferably 5~20 nanometers,
Second spacing is preferably 5~20 nanometers, and in the present embodiment, first spacing and second spacing are disposed as 10nm, its
In, first spacing refers to first contact hole and connect close to one side of the active area with the active area close to described first
The distance between one side of window is touched, the first contact hole is arranged in the isolated area and keeps the first spacing with active area, is
Because when anti-fuse structures turn on, there is very big electrical potential difference, and the insulating materials of isolated area can alleviate this potential
Influence caused by difference, and the application rationally sets the size of the first spacing, so as to ensure that size of devices, cost and stably
Property.In addition, second spacing refers to that second contact hole leans on close to one side of the isolation structure and the isolation structure
The distance between one side of nearly first contact hole, it is preferably identical with first spacing, so as to ensure that device junction
The matching of component.
In summary, the present invention provides a kind of semiconductor devices anti-fuse structures and preparation method thereof, prepares including as follows
Step：1) semi-conductive substrate is provided, the Semiconductor substrate has active area and the isolated area positioned at active area periphery；
2) in defining an antifuse configuring area in the Semiconductor substrate, and formed one around the antifuse configuring area groove knot
Structure, wherein, the antifuse configuring area includes the Part I being located in the active area and one with the Part I
Hold the Part II for being connected and extending in the isolated area；3) formed and connected in the bottom of the groove structure and partial sidewalls
Continuous dielectric layer, and in filling conductive layer in the dielectric layer, the top of the conductive layer is less than the table of the Semiconductor substrate
Face；And 4) in the isolated area formed be electrically connected to the conductive layer and with the active area have the first spacing first
Contact hole, and in forming the second contact hole in the active area, second contact hole is with the groove structure away from described
The side of first contact hole has the second spacing.By such scheme, semiconductor devices anti-fuse structures of the invention, Ke Yizuo
Anti-fuse structures are controlled for DRAM spare memory cells, by being arranged to projective structure in one jiao of its flush type metal wire, from
And tie point when can be turned on control circuit, and by by the first contact hole be arranged on active area have the first spacing every
From in area, stability during ensureing break-over of device, meanwhile, by the setting of two flush type metal wires, circuit can be led
Circuit selects most short one after logical；In addition, the preparation of the semiconductor device structure of the present invention can be in the flush type of memory
Completed in the preparation flow of character line, without increasing extra processing step, so as to simplify preparation technology, shorten production week
Phase, reduce production cost.So the present invention effectively overcomes various shortcoming of the prior art and has high industrial exploitation value
Value.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (18)
1. a kind of preparation method of semiconductor devices anti-fuse structures, it is characterised in that comprise the following steps：
1) semi-conductive substrate (1) is provided, the Semiconductor substrate has active area (11) and positioned at active area periphery
Isolated area (12)；
2) in defining an antifuse configuring area (13) in the Semiconductor substrate, and one is formed around the antifuse configuring area
Groove structure (71), wherein, the antifuse configuring area includes Part I (132) and connection in the active area
One end of the first part and the Part II (131) extended in the isolated area；
3) continuous dielectric layer (81) is formed in the bottom of the groove structure and partial sidewalls, and is filled in the dielectric layer
Conductive layer (83), the top of the conductive layer are less than the upper surface of the Semiconductor substrate；And
4) it is electrically connected to the conductive layer and has the of the first spacing (Z1) with the active area in being formed in the isolated area
One contact hole (91), and in forming the second contact hole (92) in the active area, second contact hole and the groove knot
Side of the structure away from first contact hole has the second spacing (Z2).
2. the preparation method of semiconductor devices anti-fuse structures according to claim 1, it is characterised in that in step 2),
The step of forming the groove structure specifically includes：
2-1) in being correspondingly formed the first mask layer (21) on the antifuse configuring area, and formed in the semiconductor substrate surface
Cover the top of first mask layer and the second mask layer (41) of side wall；
Second mask layer and first mask layer at the top of first mask layer 2-2) are removed, to retain described the
Two mask layers are formed in the part of the side of first mask layer；
2-3) in step 2-2) surface one layer of the 3rd mask layer (52) of deposition of structure is obtained, separately make the upper of the 3rd mask layer
Surface is not higher than the upper surface of remaining second mask layer；
Remaining second mask layer 2-4) is removed, to obtain groove opening (61)；And
2-5) continue to etch the Semiconductor substrate by the groove opening, with the Semiconductor substrate formed with it is described
The corresponding groove structure of groove opening.
3. the preparation method of semiconductor devices anti-fuse structures according to claim 2, it is characterised in that step 2-3)
In, formed three mask layer the step of include：
Prior to step 2-2) obtain threeth mask of surface one layer height of formation higher than remaining second mask layer of structure
Material layer (51), then part the 3rd mask layer is removed until exposing remaining described second using flatening process
The top of mask layer, to obtain the 3rd mask layer.
4. the preparation method of semiconductor devices anti-fuse structures according to claim 1, it is characterised in that in step 2),
The groove structure (71) formed includes ring part (711) and protuberance (712), wherein, the ring part is around described
The lateral wall of antifuse configuring area, lateral wall of the protruding parts in the ring part close to the side of second contact hole
There is above and between the protuberance and second contact hole the 3rd spacing (Z3).
5. the preparation method of semiconductor devices anti-fuse structures according to claim 1, it is characterised in that in step 1),
Also it is included in the step of semiconductor substrate surface forms one layer of etching barrier layer (31).
6. the preparation method of semiconductor devices anti-fuse structures according to claim 1, it is characterised in that step 3) is filled
Before the conductive layer, also it is included in the step of dielectric layer surface forms one layer of cementing layer (82).
7. the preparation method of semiconductor devices anti-fuse structures according to claim 1, it is characterised in that the dielectric layer
Top be less than the Semiconductor substrate upper surface；Also it is included in step 3) and obtains one layer of filling perforation insulation of surface formation of structure
The step of layer (93), the filling perforation insulating barrier is filled in the top of the groove structure and extends to the upper of the Semiconductor substrate
Surface.
8. the preparation method of semiconductor devices anti-fuse structures according to claim 1, it is characterised in that in step 4),
First spacing is 0.3~30 nanometer；Second spacing is 0.3~30 nanometer.
9. the preparation method of semiconductor devices anti-fuse structures according to claim 1, it is characterised in that the isolated area
Depth be the semiconductive substrate thickness 50%~90%；The Part II of the antifuse configuring area is located at the isolation
Length in area is the 10%~50% of the Part II total length；The width of the groove structure configures for the antifuse
The 10%~50% of the width in area；The depth of the groove structure is the 30%~70% of the semiconductive substrate thickness；It is described
The distance between the top of conductive layer and the semiconductor substrate surface are the 20%~60% of the groove structure depth；It is described
The thickness of dielectric layer is the 0.1%~10% of the groove structure width.
10. according to the preparation method of semiconductor devices anti-fuse structures according to any one of claims 1 to 9, its feature exists
In the process implementing of step 1)~step 4) is in the manufacturing process of flush type character line.
A kind of 11. semiconductor devices anti-fuse structures, it is characterised in that including：
Semiconductor substrate (1), there is active area (11) and the isolated area (12) positioned at active area periphery, antifuse configuring area
(13) it is defined in the Semiconductor substrate, the antifuse configuring area includes the Part I in the active area
(132) and one end of the connection Part I and the Part II (132) that extends in the isolated area, groove structure
(71) in the Semiconductor substrate, and set around the antifuse configuring area；
Dielectric layer (81) and conductive layer (83), the dielectric layer is incorporated into bottom and the partial sidewalls of the groove structure, described
Conductive layer is filled in the dielectric layer, and the top of the conductive layer is less than the upper surface of the Semiconductor substrate；And
First contact hole (91) and the second contact hole (92), first contact hole are electrically connected to the institute in the isolated area
State on conductive layer and there is the first spacing (Z1) with the active area, second contact hole be located in the active area and with institute
Stating side of the groove structure away from first contact hole has the second spacing (Z2).
12. semiconductor devices anti-fuse structures according to claim 11, it is characterised in that the groove structure includes ring
Shape portion (711) and protuberance (712), wherein, the ring part is around the lateral wall of the antifuse configuring area, the protrusion
Portion is located at the ring part on the lateral wall of the side of second contact hole and the protuberance contacts with described second
There is the 3rd spacing (Z3) between window.
13. semiconductor devices anti-fuse structures according to claim 11, it is characterised in that the top of the dielectric layer is low
In the upper surface of the Semiconductor substrate；The semiconductor devices anti-fuse structures also include filling perforation insulating barrier (93), are filled in
The top of the groove structure and the upper surface for extending to the Semiconductor substrate, wherein, first contact hole is described in
Filling perforation insulating barrier electrically connects with the conductive layer, and second contact hole is through the filling perforation insulating barrier and extends to described active
In area.
14. semiconductor devices anti-fuse structures according to claim 11, it is characterised in that the dielectric layer is led with described
One layer of cementing layer (82) is also formed between electric layer.
15. semiconductor devices anti-fuse structures according to claim 14, it is characterised in that the material bag of the cementing layer
Include titanium nitride.
16. semiconductor devices anti-fuse structures according to claim 11, it is characterised in that the material choosing of the conductive layer
In the group formed from tungsten, titanium, nickel, aluminium, platinum, silicon titanium nitride, metal nitride, metal silicide and DOPOS doped polycrystalline silicon
It is at least one；The resistivity of the conductive layer is 2 × 10-8Ω m~1 × 102Ωm；The material of the dielectric layer is selected from titanium dioxide
At least one of group that silicon, hafnium oxide are formed.
17. semiconductor devices anti-fuse structures according to claim 11, it is characterised in that first contact hole and institute
State that the structure of the second contact hole is identical, including conductive pole and lateral wall and the bonding layer of bottom positioned at the conductive pole.
18. the semiconductor devices anti-fuse structures according to any one of claim 11~17, it is characterised in that described
One spacing is 0.3~30 nanometer；Second spacing is 0.3~30 nanometer.
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