CN107728517B - Universal intermediate frequency signal processing method based on embedded ARM - Google Patents

Abstract

The invention provides a general intermediate frequency signal processing method based on an embedded ARM, which comprises the following steps: firstly, connecting an FPGA and an ARM external interface module, namely EIM; writing an EIM time sequence conversion module; thirdly, packaging an EIM control interface; developing an ARM remote control method for a user to monitor the EIM in real time; through the steps, the embedded ARM-based universal intermediate frequency signal processing method is based on the software calculation and control capacity provided by the embedded ARM, can realize various different signal processing capacities through software development and configuration, and can monitor the running state of the platform in real time, so that the embedded ARM-based universal intermediate frequency signal processing method has strong universality, achieves the effect of reducing development difficulty and cost, and is suitable for experimental occasions of general technical verification.

Description

Universal intermediate frequency signal processing method based on embedded ARM

[ technical field ] A method for producing a semiconductor device

The invention provides a general intermediate frequency signal processing method based on an embedded advanced reduced instruction set machine (ARM), which is a method capable of controlling intermediate frequency signal processing in real time through software and belongs to the field of communication and control.

[ background of the invention ]

A common intermediate frequency signal processing platform is based on an industrial personal computer framework, and a server main board and a signal processing board card are connected through buses such as Compact Peripheral Component Interconnect (CPCI). The signal processing board card takes a Field Programmable Gate Array (FPGA) as a core to complete the signal processing functions of the intermediate frequency signal, including analog-to-digital conversion, modulation, demodulation and the like; the server mainboard is provided with an operating system to complete all the operation and processing functions similar to those of a personal computer, and software development can be carried out on the operating system to realize the functions of controlling and communicating the signal processing board card and the like. The industrial personal computer-based architecture has the disadvantages of poor flexibility in development and use, relatively high cost, large occupied space and inapplicability in many occasions for technical verification.

[ summary of the invention ]

Objects of the invention

The invention aims to provide a method for processing a universal intermediate frequency signal based on an embedded ARM, which is used for controlling the intermediate frequency signal processing based on the embedded ARM.

(II) technical scheme

In order to achieve the purpose, the invention discloses a general intermediate frequency signal processing method based on an embedded ARM, which comprises the following implementation steps:

step one, connecting an FPGA and an External Interface Module (EIM) of an ARM;

step two, compiling an EIM time sequence conversion module;

step three, packaging an EIM control interface;

step four, developing an ARM remote control method for a user to monitor the EIM in real time;

in step one, "connect the FPGA and the external interface module (i.e., EIM)" of the ARM, the method is as follows:

in the design stage of a schematic diagram of a hardware board card, signals related to EIMs, including chip selection signals, enable signals, address effective signals, read-write enable signals and data/address multiplexing signals, are connected to pins of an FPGA one by one, so that the hardware connection foundation is ensured to be effective and reliable;

wherein, the writing EIM time sequence conversion module in the step two comprises the following steps:

analyzing the accessed EIM related signals in the FPGA according to a set time sequence relation, converting the signals into self-defined local bus signals in the FPGA, wherein the self-defined local bus signals comprise local chip selection signals, local read-write enabling pulse signals, local address signals, local data signals and local data read-back signals, and connecting the local bus signals with each submodule in the FPGA to realize the control of the EIM on each module of the FPGA.

Wherein, the "encapsulate EIM control interface" in step three is implemented as follows:

and packaging read-write control of the EIM by the ARM into a top library function based on the corresponding relation between the address and the register defined in the EIM time sequence conversion module in the second step, and calling the function to perform read-write control on the parameters of the signal processing algorithm in the FPGA by the ARM.

Wherein, in the step four, the method for developing the ARM remote control method for the user to monitor the EIM in real time is as follows:

on the basis that the ARM provides an external network interface, a remote control mode of the ARM is set, then a remote control command of the EIM is set, and a personal computer of a user is connected with the ARM through a network to realize real-time monitoring of the EIM.

Through the steps, the embedded ARM-based universal intermediate frequency signal processing method is based on the software calculation and control capacity provided by the embedded ARM, can realize various different signal processing capacities through software development and configuration, and can monitor the running state of the platform in real time, so that the embedded ARM-based universal intermediate frequency signal processing method has strong universality, achieves the effect of reducing development difficulty and cost, and is suitable for experimental occasions of general technical verification.

(III) advantages and effects

According to the design of the invention, the embedded ARM is used for replacing the traditional industrial personal computer framework, software development is carried out on the ARM to complete the required operation and control functions, a remote control method for the ARM is provided, the flexibility of development, use and control is improved, and the cost and the occupied space are reduced.

According to the design of the invention, the invention can realize various intermediate frequency signal processing functions through multiple development and configuration of software, and has strong universality.

[ description of the drawings ]

The foregoing and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings. In the drawings:

fig. 1 is a block diagram of an embodiment according to the present invention.

Fig. 2 is a schematic diagram of bus communication between an embedded ARM and an FPGA according to an embodiment of the present invention.

Figure 3 is a schematic diagram of a user interface of an embedded ARM according to an embodiment of the present invention.

FIG. 4 is a flow chart of the method of the present invention.

The numbers, symbols and codes in the figures are explained as follows:

FPGA represents Field Programmable Gate Array;

ARM stands for Advanced RISC Machine, Advanced reduced instruction set Machine;

EIM stands for External Interface Module, External Interface Module;

EIM _ CS represents a chip select signal; EIM _ OE represents an enable signal; EIM _ LBA represents an address valid signal; EIM _ RW denotes read/write enable signal; EIM _ DA denotes a data/address multiplexing signal; lcs _1 denotes the local chip select signal for module 1; lcs _ n denotes the local chip select signal for the nth module; lwr denotes a local read-write enable pulse; la represents a local address signal; ldin represents the local data signal; ldout _1 represents the 1 st local data read-back signal; ldout _ n represents the local data read back signal for the nth module.

[ detailed description ] embodiments

So that the manner in which the features, objects, and functions of the invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings.

The embodiment of the invention provides a general intermediate frequency signal processing method based on an embedded ARM, which replaces an industrial personal computer framework and simultaneously reserves sufficient software operation capacity and control capacity by a software development mode on a Linux operating system carried by the embedded ARM. The signal processing algorithm runs on the FPGA and can be repeatedly configured through software, so that the software, the algorithm and the hardware module can be continuously updated and updated, and various application scenes can be met.

First, a hardware platform according to an embodiment of the present invention is introduced, and as shown in fig. 1, a hardware module according to an embodiment of the present invention includes an FPGA, an embedded ARM, an analog-to-digital conversion module, a clock module, and a power module. The FPGA and the ARM are core modules, and the main functions of the invention are completed by the FPGA and the ARM. The FPGA is responsible for running a digital signal processing algorithm and finishing a bus interface with the embedded ARM and a data exchange interface with other peripheral hardware. The ARM is used for carrying a software operating system and is responsible for completing all software operation functions and communication and control functions related to other modules, and the communication and control functions comprise bus communication with the FPGA and a user-oriented software control interface. The analog-to-digital conversion module, the clock module and the power module are used as peripheral circuits to meet other necessary hardware requirements, including the steps of converting intermediate-frequency analog signals into digital signals for FPGA (field programmable gate array) to perform digital signal processing, and providing clocks with different frequencies and different voltages for all chips.

The FPGA is connected with the ARM through the EIM provided by the ARM, the EIM is analyzed and converted in the FPGA and then connected to the signal processing algorithm module running in the FPGA, and the ARM can perform software control on the FPGA through the EIM, monitor parameters in the FPGA in real time and repeatedly configure the FPGA to realize different signal processing effects. The software calculation required by the operation in the ARM can automatically monitor the operation condition of the FPGA, and can also receive an instruction from a user computer through a network interface to monitor the operation condition of the FPGA. The foregoing illustrates a basic principle of the if signal processing platform according to the embodiment of the present invention, and the following describes in detail the steps of controlling if signal processing based on the embedded ARM.

The invention discloses a general intermediate frequency signal processing method based on an embedded ARM (advanced RISC machines), which is shown in figure 4 and comprises the following implementation steps:

the first step is as follows: connecting the FPGA with the EIM of the ARM;

as shown in fig. 2, signals related to an EIM of ARM include:

chip select signal-EIM _ CS

Enable Signal-EIM _ OE

Address valid Signal-EIM _ LBA

Read-write enable signal-EIM _ RW

Data/address multiplex signal-EIM _ DA

In the stage of designing a hardware board schematic diagram, signals related to the EIM are connected to the FPGA one by one, the ARM is used as an active side to control the signals according to a certain time sequence, and the FPGA is used as a receiving side to process the signals.

The second step is that: compiling an EIM time sequence conversion module;

when the FPGA is developed, the EIM is converted into a local bus through a time sequence conversion module. The step is the key point of the implementation of the invention, and in order to facilitate the control of the internal register of the FPGA, the accessed EIM needs to be analyzed and then converted into an independently defined local bus inside the FPGA to be connected with each submodule in the FPGA. As shown in fig. 2, the timing conversion module programmed in the FPGA analyzes all signals of the EIM described in the first step according to a predetermined timing relationship, and converts the signals into self-defined local bus signals, which respectively include:

local chip select signal-lcs _ n

Local read write enable pulse-lwr

Local address signal-la

Local data Signal-ldin

Local data read-back signal-ldout _ n

For different sub-modules running inside the FPGA, a local chip selection signal and a local data read-back signal correspond to the sub-modules, and other local bus signals are the same among the different sub-modules. After the time sequence conversion control is carried out, the register and the EIM can be conveniently connected when the FPGA is developed.

The third step: packaging an EIM control interface;

all parameters of the signal processing algorithm running in the FPGA can be abstracted into registers, and the control of the signal processing algorithm can be completed by controlling the registers in the FPGA through EIM. Therefore, the read-write control of the ARM on the EIM is packaged into a top library function for users to use, and when the users develop the ARM software, the read-write control can be performed on the parameters of the signal processing algorithm in the FPGA by calling the library function.

Fourthly, developing an ARM remote control method for a user to monitor the EIM in real time;

as shown in fig. 3, the embodiment of the present invention integrates a network cable interface to connect a personal computer with an ARM, and sets a remote control mode of the ARM on the basis, and then sets a remote control command for an EIM, so that software computation of the ARM can be controlled in real time by performing a remote login operation on the ARM, and meanwhile, the operation of the FPGA can be controlled in real time by the EIM, thereby completing a method for controlling intermediate frequency signal processing by an embedded ARM.

As can be seen from the above steps, in the embodiment of the present invention, the embedded ARM mainly completes three operations: 1) data communication with the FPGA; 2) running software for calculation; 3) network communication with a user computer. The main functions of the original industrial personal computer are completed while the structure of the industrial personal computer is replaced. The embedded ARM provides software calculation and control capability as a basis, various different signal processing capabilities are realized through software development and configuration, and the running condition of the platform can be monitored in real time, so that the embedded ARM-based universal intermediate frequency signal processing method has stronger universality, and has the advantages of flexibility, cost reduction, volume reduction and the like compared with an industrial personal computer architecture.

Although the present invention has been described with reference to the above embodiments, the embodiments are merely exemplary, and not restrictive, and it should be understood that various changes and substitutions may be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (1)

1. A method for processing a universal intermediate frequency signal based on an embedded ARM is characterized in that: the implementation steps are as follows:

step one, connecting an FPGA and an External Interface Module (EIM) of an ARM;

step two, compiling an EIM time sequence conversion module;

step three, packaging an EIM control interface;

step four, developing an ARM remote control method for a user to monitor the EIM in real time;

in the step one, the external interface module, i.e. EIM, for connecting the FPGA and the ARM is as follows:

in the design stage of a schematic diagram of a hardware board card, signals related to EIM, including a chip selection signal, an enable signal, an address effective signal, a read-write enable signal and a data/address multiplexing signal, are connected to pins of the FPGA one by one;

the writing EIM timing conversion module described in step two is implemented as follows:

analyzing the accessed EIM related signals in the FPGA according to a set time sequence relation, converting the signals into self-defined local bus signals in the FPGA, wherein the self-defined local bus signals comprise local chip selection signals, local read-write enabling pulse signals, local address signals, local data signals and local data read-back signals, and connecting the local bus signals with each submodule in the FPGA to realize the control of the EIM on each module of the FPGA;

encapsulating the EIM control interface as described in step three, does so as follows: based on the corresponding relation between the address and the register defined in the EIM time sequence conversion module in the step two, packaging read-write control of the ARM on the EIM into a top library function, and calling the function to perform read-write control on parameters of a signal processing algorithm in the FPGA through the ARM;

the method for developing ARM remote control for real-time monitoring of EIM by the user, which is described in step four, is as follows:

on the basis that the ARM provides an external network interface, a remote control mode of the ARM is set, then a remote control command of the EIM is set, and a personal computer of a user is connected with the ARM through a network to realize real-time monitoring of the EIM.

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