CN107710004A - The improved power supply transient performance of integrated circuit testing environment middle probe card component（Power Integrity） - Google Patents
The improved power supply transient performance of integrated circuit testing environment middle probe card component（Power Integrity） Download PDFInfo
- Publication number
- CN107710004A CN107710004A CN201680031122.4A CN201680031122A CN107710004A CN 107710004 A CN107710004 A CN 107710004A CN 201680031122 A CN201680031122 A CN 201680031122A CN 107710004 A CN107710004 A CN 107710004A
- Authority
- CN
- China
- Prior art keywords
- nude film
- spacing
- conversion baseplate
- structure according
- spacing conversion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31901—Analysis of tester Performance; Tester characterization
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
- G01R31/2889—Interfaces, e.g. between probe and tester
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07364—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch
- G01R1/07378—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch using an intermediate adapter, e.g. space transformers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31905—Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
Abstract
The present invention describes the three different embodiments conveyed for Low ESR (overclocking) power realized to nude film substantially.This low impedance at high frequency enables nude film with package level speed operation, so as to reduce the yield loss of package level.Each embodiment solves the slightly different aspect of whole wafer probe application.However, in each example, the key improvements of the disclosure are relative to position of the prior art for the passive element for filtering/decoupling of powering.Three all embodiments are required for a kind of method to embed passive components near spacing conversion baseplate or physically in spacing conversion baseplate.
Description
Background technology
1. technical field
The present invention is a kind of for solving and being monolithic (singulated) or non-monolithic (unsingulated) nude film
(die) automatic test of the very high speed integrated circuit device of (wafer (wafer)) form related Power Integrity problem
Structure.Especially, present invention offer one kind is used for improved spacing conversion baseplate (pitch translation substrate)
And for positioning or being embedded in the structure closer to the passive element of spacing conversion baseplate.
2.Definition
Disclosure for a better understanding of the present invention, some terms are defined below.
Probe card：Multilayer board, usually 3 millimeters to 8 millimeters thicks.It is used as from (automatic) test system to
The electric signal routing interface of spacing conversion baseplate.Probe card changes spacing in itself, but size is bigger.Probe card is also changed for spacing
Substrate and probe case provide mechanical support.For the sake of clarity, it is described in the drawings and shows probe card.
Spacing conversion baseplate：Spacing conversion baseplate (PTS) provides the interface between probe card and probe case component.Standard
Printed circuit board material does not allow sufficiently small spacing to support the electrical connection pattern on integrated circuit die.It is special that PTS is used
Material, and it is more much smaller than probe card, it is allowed to electrical signals are by being present between nude film and probe card.Most of PTS devices lead to
Normally due to for manufacture they material and it is well known.These materials include but is not limited to " MLC " (multi-layer ceramics),
" MLO " (multilayer organic matter), " Si Sub " (silicon substrate), " Glass sub " (glass substrate).The principal focal point of the disclosure is
PTS, because improved Power Integrity needs to be changed this structure.
Probe case component：Probe case component includes the actual electric probe between integrated circuit die and PTS.In order to clear
Chu Qijian, described in figure and show probe case.
Nude film：For nude film with reference to the actual circuit that is electrically integrated, whole probe assembly is designed to test for the actual electricity collection
Into circuit.Usual nude film manufactures by the gross on Silicon Wafer；This form is referred to as the form of " non-monolithic " by this document.The shape of non-monolithic
Formula is that nude film tests most common form.Nude film can individually be tested in the form of " monolithic ", wherein each nude film and wafer thing
Separated in reason.Nude film can also be tested in the form of " reconstruct " wafer, and wherein the placement spacing of nude film and original wafer be not
Together.Probe assembly includes probe card, spacing conversion baseplate and probe case, and any of it, which is used in the form of these three, is carried out
Nude film is tested.The main purpose for solving Power Integrity/impedance problems in the disclosure is to realize before encapsulation to nude film
Test as close possible to its mission mode (end user's application).
Wafer：Brilliant diameter of a circle is usually 200mm, 300mm or 450mm, is the basis of each individually nude film of manufacture.One
Wafer may include 30-40 to the independent nude film that thousands of are non-monolithic form.For the sake of clarity, wafer is shown in figure.
As illustrated, reader is considered as testing the single nude film that probe is connected on wafer.
Chuck：Chuck is a big pressing plate, is typically constructed of metal, and wafer/chip is supported and clamped in test process.
Chuck is also travel mechanism, from a nude film to another nude film, so as to test each chip.In order to clearly rise
See, chuck is shown in the drawings.
Power Integrity：The probe assembly for describing to be arranged at when device works on power supply and grounding pin is in much degree
On disclosure satisfy that the requirement of transient current.Crucial indicatrix is " current supply circuit impedance " and frequency for Power Integrity
Rate.
Current supply circuit impedance：This is when tested integrated circuit (nude film) applies sinusoidal or transient current demand to power pins
When power supply by probe assembly and grounding pin (power pins) by measurement (voltage drop/electricity in frequency domain F of the voltage of decline
Stream).Electric power loop impedance is lower, and voltage drop is smaller.Impedance loop represents that power supply and grounding pin have all been included.
In excessively simplified term, impedance loop is frequently described as " self-induction " in the industry, wherein self-induction (LS) etc.
In loop inductance (LL) 1/2, and | j2 π FLL| the impedance loop related equal to simple inductance." impedance loop " is more just
True and general term, because it explains the situation of the non-ideal inductor in power supply to the path on ground, such as resonance point.
Data eye：Because current supply circuit impedance may not be converted into the improvement of performance, data eye is used also as can
Depending on indicatrix.The data eye service life time-division by the data flow from tested nude film numerical data be superimposed, generally with operation
Clock or embedded clock are associated.The one centre data ocular opened shows good operating range, when eye closed center just
It is likely to occur mistake.
(Compliant Electrical Interconnect) is electrically interconnected in flexibility：A kind of electrical interconnection arrangement is, it is necessary to certain
The compression of degree, to realize the electrical contact between the desired pad (pad) on two different surfaces.Flexible interconnection allows two
The coplanar difference of higher degree, motion (i.e. thermal expansion discharges) between individual surface, and be generally easy to exchange.Example includes but unlimited
In spring contact probe, electrically conductive elastic piece and electrically conductive elastic pin.
Permanent electrical interconnection：A kind of electrical interconnection arrangement, realize permanent between the desired pad on two different surfaces
Connection and electrical contact.Permanent interconnection is characterised by relatively low contact resistance, the higher rigidity of structure and takes off two surfaces
The effect of viscous larger heat and power.Example include but is not limited to solder and thermoacoustic ripple (thermal-sonically) bonding
Copper post.
Redistribution layer (RDL)：One electric routing layer, is present in spacing conversion baseplate, and is used for from the very small of nude film
Point-to-point connection of the spacing to the very big spacing of probe card.In many cases, intermediate steps and multiple interconnection be might have
Redistribution layer.
3.Correlation technique
Figure 11 shows the sectional view of the prior art of correlation, and only for reference.In the prior art, wafer probe or naked
Piece probe unit includes probe card [80], bindiny mechanism [82] and spacing conversion baseplate [81], probe and probe [83] and crystalline substance
Circle probe chuck (only chuck) [85].At work, chuck [85] is moved to nude film from nude film in the x-y directions.When next
When nude film to be measured has arrived at, chuck [85] rises to wafer/nude film [84] in probe [83].Probe [83] and wafer [84]
On nude film formed Mechanical Contact, so as to provide conductive path, it is allowed to which nude film [84] is tested.
In the prior art, passive electrical element 86 (being usually capacitor) is next during its work and in electrical testing
Electric charge storage is provided from the transient current demand (charging/time) of nude film [84].Normal practice of the prior art is between use
Connected up away from the region directly over the nude film [84] in conversion baseplate [81] and detecting card [80].
The physical distance between nude film to be tested on passive electrical element [86] and wafer [84] directly affects passive electrical
The electric charge of storage can be sent to any degree to meet the transient current demand of nude film [84] in gas element [86].If distance
It is longer, because more delays will occur in the length of distance.Because decoupling capacitor plays the effect of RF short circuits, therefore this prolongs
Generally there is up to~1GHz inductive effect late, and shaken as frequency increases between higher impedance and lower impedance
Swing (referring to Figure 12 B).This is a kind of impedance influences of common distribution.Due to probe card thickness in response to it is different and different,
The accurate location of resonance point can also change.Net impacts are shown in Figure 13 B, 14B, 15B and 16B.According to Figure 13 B and 14B
Data eye, nude film is rightly stopped between 667MB/s and 1000MB/s.Figure 16 B show 1GHz clocks.In this feelings
Under condition, ring is intended to align, but edge transition serious distortion.
For the term of slight over simplification, problem can be by being reduced to loop inductance L by effective impedance loopLCome
Explain.Voltage drop is multiplied by derivative of the transient current demand relative to the time, Δ V=L equal to loop inductanceL×dI/dt.Work as nude film
On transistor it is in an interim state when, transient current can be produced, and briefly, the parasitic capacitance that must be driven with transistor
CpIt is current related with part ON/OFF.With LLIncrease, transistor output response with delay, decay sinusoidal ring
Or the edge of the reduction of delay.Herein simplify in the case of, two kinds it is possible response all with LLAnd CPMain second-order response have
Close --- usually it is modeled as second order differential equation.Ring is most apparent in Figure 14 B.
4.
Passive element is connected in probe card by the prior art of standard using solder reflow process.This connection method is made
Good fortune domain knowledge and embodiment more than 30 year.Therefore cost is cheap and reliable --- and all it is to sacrifice performance as cost.There is provided
The one or more structures for overcoming the above mentioned problem related to above-mentioned prior art will be desirable.
The content of the invention
The present invention, which provides, a kind of is used for improved spacing conversion baseplate and for positioning or embedded changing base closer to spacing
The structure of the passive element of plate.Present invention fundamentally provides the different embodiment of the three of this structure, for realizing to naked
Low ESR (overclocking) power conveying of piece.This low impedance at high frequency enables nude film with package level speed operation, so as to reduce envelope
Fill the yield loss of level.Each embodiment solves the slightly different aspect of whole wafer probe application.However, each
In embodiment, the key improvements of the disclosure are relative to position of the prior art for the passive element for filtering/decoupling of powering.Institute
Three embodiments having are required for a kind of method to embed passive components near spacing conversion baseplate or physically in spacing
In conversion baseplate.
Decoupling element and plane are embedded into an insert configuration by the first embodiment of the present invention (referring to Fig. 1-4), institute
State insert configuration and also serve as bindiny mechanism between spacing conversion baseplate and probe card.The embodiment has the excellent of interchangeability
Point, because spacing conversion baseplate can be the consume element in high power capacity test.Although more preferable than prior art, relative to
There are some hydraulic performance declines in other embodiments.First embodiment can be used together with any type of spacing conversion baseplate.
But the short electrical length of glass and silicon substrate is most favourable.
Decoupling element is connected directly to upper table interplanar distance conversion baseplate by second embodiment (referring to Fig. 5-7).Substrate is installed
On protectiveness mechanical cover, the electrical connection with probe card is also provided.The embodiment have bigger power integrity and
The advantages of interchangeability.However, it is more more expensive than first embodiment to replace mechanism.Second embodiment needs the short of glass and silicon substrate
Electrical length realize its advantage.
Decoupling element is directly completely embedded into immediately below thin electric signal redistribution layer by 3rd embodiment (referring to Fig. 8-10)
Spacing conversion baseplate.The embodiment has maximum power integrity performance to sacrifice interchangeability as cost.Must after consume
Whole component must be changed.3rd embodiment can be built with any applicable material.
Brief description of the drawings
Fig. 1-4 describes the first embodiment of the present invention substantially, shows decoupling element and plane being embedded into an insertion
Structure in part structure, the insert configuration also serve as the bindiny mechanism between spacing conversion baseplate and probe card, wherein：
Fig. 1 is the decomposed sectional view of the first embodiment of the present invention, is by decoupling element which show the present invention
It is embedded into the structure in an insert configuration with plane, the insert configuration is also served as between spacing conversion baseplate and probe card
Bindiny mechanism；
Fig. 2 is the sectional view after the complete assembling of first embodiment of the invention as shown in Figure 1；
Fig. 3 is similar embodiment of the invention as illustrated in fig. 1 and 2, is soldered to is used for away from conversion baseplate among it
The insert configuration of decoupling element and plane；
Fig. 4 is similar embodiment of the invention as shown in Figure 3, except spacing conversion baseplate is soldered to probe card；
Fig. 5-7 generally show the second embodiment of the present invention, and wherein decoupling element is provided with supreme for being directly connected to
The structure of surface spacing conversion baseplate, wherein：
Fig. 5 is the exploded partial cutaway view of the second embodiment of the present invention, and wherein the present invention is shown as being used to decouple member
One structure of part, to be directly connected to the top of upper table interplanar distance conversion baseplate；
Fig. 6 is the view after the complete assembling of the second embodiment shown in Fig. 5；
Fig. 7 is similar embodiment of the invention as illustrated in Figures 5 and 6, except spacing conversion baseplate is soldered to probe
Card；
Fig. 8-10 generally show the third embodiment of the present invention, and wherein decoupling element is directly completely embedded into thin electric signal
In spacing conversion baseplate below redistribution layer, wherein：
Fig. 8 is the decomposed sectional view of the third embodiment of the present invention, and the wherein present invention is shown as a structure, wherein
Decoupling element is completely embedded into the spacing conversion baseplate immediately below thin electric signal redistribution layer,
Fig. 9 is the sectional view after the 3rd embodiment assembling completely shown in Fig. 8,
Figure 10 is similar embodiment of the invention as shown in FIG. 8 and 9, except spacing conversion baseplate is soldered to probe
Card；
Figure 11 is the sectional view of prior art construction；
Figure 12 is to show first embodiment (Fig. 1-4) and 3rd embodiment compared with the structure of Figure 11 prior art
The curve map of current supply circuit impedance in the frequency domain of (Fig. 8-10)；
Figure 13 be and prior art (Figure 11；B) compare, for 3rd embodiment (Fig. 8-10；A simple pattern data)
Eye@667Mb/s diagram
Figure 14 is the simple pattern data eye@of 3rd embodiment (A) (Fig. 8-10) compared with prior art (B) (Figure 11)
1Gb/s diagram
Figure 15 is the simple pattern data eye@of the 3rd embodiment (A) (Fig. 8-10) compared with prior art (B) (Figure 11)
2GB/s diagram
Figure 16：Show compared with prior art (B) (Figure 11), the voltage and time domain of 3rd embodiment (A) (Fig. 8-10)
Clock patterns
Figure 17：For show all embodiments of the invention be used for relative to the capacitor locations in spacing conversion baseplate and/
Or the top view of the wiring of the signal of embedded element insert；
Figure 18 is the enlarged drawing of Fig. 1 spacing conversion baseplate；
Figure 19 is the enlarged drawing of Fig. 5 spacing conversion baseplate；And
Figure 20 is the enlarged drawing of Fig. 8 spacing conversion baseplate；
Embodiment
The element number of each embodiment in accompanying drawing 1-20 is as follows：
Fig. 1：The view sub-anatomy of first embodiment with flexible interconnection
1. probe card printed circuit board (PCB) (PCB)
2. the wafer to be detected with single nude film
3. supporting probe chuck
4. probe case
5. probe mechanism
6.PCB to ECI flexible interconnection
7. the compression for #6 stops shell
8. the element of insertion, passive type
Embedded element insert 9. (ECI) substrate
10.ECI to PTS flexible interconnection
11. the compression for #10 stops shell
12. the spacing conversion baseplate (PTS) of " glass " or " silicon " through hole with insertion
13. embedded element insert component, is made up of #6-#11
14.ECI/PTS components, substitute prior art (for example, MLO, MLC)
15. probe assembly
Fig. 2：First embodiment (Fig. 1), it show after assembling and detects nude film
16. probe card printed circuit board (PCB) (PCB) (identical with Fig. 1 .1)
17. the wafer to be detected (identical with Fig. 1 .2) with single nude film
18. supporting probe chuck (identical with Fig. 1 .3)
19.ECI/PTS components, substitute prior art (for example, MLO, MLC) (identical with Fig. 1 .14)
20. probe assembly (identical with Fig. 1 .15)
Fig. 3：With the little deviation 1 of first embodiment：PTS is to using permanent electrical interconnection between ECI
21. probe card printed circuit board (PCB) (PCB) (identical with Fig. 1 .1)
22. the wafer to be detected (identical with Fig. 1 .2) with single nude film
23. supporting probe chuck (identical with Fig. 1 .3)
24.ECI/PTS components, substitute prior art (for example, MLO, MLC) (, simply element 10,11 similar with Fig. 1 .14
Change permanent interconnection into)
25. probe assembly (identical with Fig. 1 .15)
Permanent conductive interconnection mechanism (solder, copper post) between 26.ECI and PTS
Fig. 4：With the little deviation 2 of first embodiment：Permanent electrical interconnection is used between PTS ECI components and probe card
27. probe card printed circuit board (PCB) (PCB) (identical with Fig. 1 .1)
28. the wafer to be detected (identical with Fig. 1 .2) with single nude film
29. supporting probe chuck (identical with Fig. 1 .3)
30.ECI/PTS components, substitute prior art (for example, MLO, MLC) (, simply element 6,7 ands similar with Fig. 1 .14
10th, 11 permanent interconnection is changed into)
31. probe assembly (identical with Fig. 1 .15)
Permanent conductive interconnection mechanism (solder, copper post) between 32.ECI and PTS
Permanent conductive interconnection mechanism (solder, copper post) between 33.ECI/PTS components and probe card
The accompanying drawing of second embodiment
Fig. 5-7 describes the section view for being used for signal loading and the improved method of power supply conveying using the second main embodiment
Two little deviations of figure：Based on " TSV ", " TGV " or similar techniques, the spacing conversion baseplate (PTS) based on glass or silicon, its
Middle passive element is directly installed on spacing converter.These elements can be the form of nude film or encapsulation.With conductive path
Fastening element be permanently attached to spacing converter substrate as needed, for mechanical enhancer, more preferable durability and it is big between
Away from conversion (coarse pitch translation).Fig. 5 describes discrete component.Fig. 6 is shown to be assembled with " mission mode "
Fig. 5.Fig. 7 describes little deviation, and wherein flexible interconnection is via any type of more permanently connected replacement, typically solder
And copper post.
In Figure 5,34-38,46 are marked to describe associated with the disclosure but specifically include necessity in the disclosure
Functional element.It is because they are representation function and are necessary relative to the improvement of prior art to show these elements.
Fig. 5：Embodiment #2 sectional exploded view：The embedding of PTS is connected to support reinforcement and using flexibility
Enter formula decoupling element
34. probe card printed circuit board (PCB) (PCB)
35. the wafer to be detected with single nude film
36. supporting probe chuck
37. probe case
38. probe mechanism
39.PCB to PTS flexible interconnection
40. the compression for #39 stops shell
41. embedded element, passive type, and cavity
Forever mechanism is conductively connected between 42.PTS and reinforcing element
43. it is used for the reinforcing element of big spacing conversion with conductive path
44. with insertion " glass " or the spacing conversion baseplate (PTS) of " silicon " through hole or similar techniques
45. embedded element spacing converter assembly, is made up of #39-#44
46. probe assembly
Fig. 6：Second embodiment (Fig. 5), it show after assembling and detects nude film
47. probe card printed circuit board (PCB) (PCB) (identical with Fig. 5 .34)
48. the wafer to be detected (identical with Fig. 5 .35) with single nude film
49. supporting probe chuck (identical with Fig. 5 .36)
50.ECI/PTS components, substitute prior art (for example, MLO, MLC) (identical with Fig. 5 .45)
51. probe assembly (identical with Fig. 5 .46)
Fig. 7：The little deviation of second embodiment：Use between adjacent reinforcer and probe card and forever electrically connect
52. probe card printed circuit board (PCB) (PCB) (identical with Fig. 5 .34)
53. the wafer to be detected (identical with Fig. 5 .35) with single nude film
54. supporting probe chuck (identical with Fig. 5 .36)
55.ECI/PTS components, and replacement prior art (for example, MLO, MLC) (it is similar with Fig. 5 .45, except flexible member #
39 and #40 has been substituted for permanent attachment mechanism)
56. probe assembly (identical with Fig. 5 .46)
57. embedded element/permanent attachment mechanism between spacing convertor base plate component and probe card
The accompanying drawing of 3rd embodiment
Figure #8-#10 is described using the 3rd main embodiment using sectional view to be changed for what signal loading and power supply conveyed
Two little deviations of the method entered：Spacing with the passive electrical element being embedded in directly over test nude film interested turns
Change substrate.Figure #8 describes each element.Figure #9 shows the figure #8 after being assembled with " mission mode ".It is micro- that figure #10 describes one
Little deviation, wherein flexible interconnection are substituted by any type of more permanent connection, but typically solder and copper post.
In #8 is schemed, mark 58-62,68 describe associated with the disclosure but specifically include necessity in the disclosure
Functional element.It is because they are representation function and are necessary relative to the improvement of prior art to show these elements.
Fig. 8：The sectional exploded view of 3rd embodiment：Spacing is directly embedded passive components into using flexibility electrical interconnection to change
In substrate
58. probe card printed circuit board (PCB) (PCB)
59. the wafer to be detected with single nude film
60. supporting probe chuck
61. probe case
62. probe mechanism
63.PCB to ECI flexible interconnection
64. the compression for #63 stops shell
65. the element of insertion, passive type
66. the spacing conversion baseplate (PTS) with integrated embedded element
67.PTS components
68. probe assembly
Fig. 9：It show the 3rd embodiment (Fig. 8) of assembling and detects nude film
69. probe card printed circuit board (PCB) (PCB) (identical with Fig. 8 .58)
70. the wafer to be detected (identical with Fig. 8 .59) with single nude film
71. supporting probe chuck (identical with Fig. 8 .60)
72. spacing conversion baseplate (identical with Fig. 8 .67)
73. probe case (identical with Fig. 8 .68)
Figure 10：With the little deviation of 3rd embodiment：Permanent electrical interconnection is used between PTS and probe card
74. probe card printed circuit board (PCB) (PCB) (identical with Fig. 8 .58)
75. the wafer to be detected (identical with Fig. 8 .59) with single nude film
76. supporting probe chuck (identical with Fig. 8 .60)
77. spacing conversion baseplate (is similar to Fig. 8 .67, but is revised as permanently connected)
78. probe case (identical with Fig. 8 .68)
79. permanent attachment mechanism
Figure 11：Description of the prior art
80. probe card printed circuit board (PCB) (PCB)
81. spacing conversion baseplate
82. permanent attachment mechanism
83. probe case and probe
84. the wafer to be detected with single nude film
85. supporting probe chuck
86. the passive element of welded and installed
Figure 12-16 shows the performance comparison between prior art and the disclosed embodiments.In Figure 12-16, " A " side
Show the improved performance of the disclosure；" B " side shows the performance of prior art.
Figure 12：Compared with prior art (B), the current supply circuit of first embodiment (A) and 3rd embodiment (A) in a frequency domain
Impedance.
Figure 13：Simple pattern data eye@667Mb/s；3rd embodiment (A) is compared with prior art (B)
Figure 14：Simple pattern data eye@1Gb/s；3rd embodiment (A) is compared with prior art (B)
Figure 15：Simple pattern data eye@2GB/s；3rd embodiment (A) is compared with prior art (B)
Figure 16：Compared with prior art (B), voltage-domain clock pattern of 3rd embodiment (A).
Figure 17：Show signal relative to the capacitor locations in spacing conversion baseplate and/or embedded element insert
The top view of route
87. the position of the nude film under spacing conversion baseplate (PTS)
The position of passive element (such as decoupling capacitor) directly over nude film in 88.ECI (embodiment #1) or PTS
89. small spacing through hole ring：50um to 100um spacing through hole, be usually known " insertion silicon hole " (TSV) or
" insertion glass through hole " (TGV)
90. the route of signal from nude film to the redistribution layer near nude film [87] on small spacing through hole ring [89]
91. interface pad [92] of the route of signal from small spacing through hole ring [89] to the redistribution layer relative with nude film
92. interface pad is connected to by probe card by permanent or flexible interconnection
93. spacing conversion baseplate
Figure 18：The sectional view of embodiment #1 improved spacing conversion baseplate
94. the upper redistribution layer (relative with nude film) of the interface pad for being fanned out to ECI and probe card from TSV/TGV
95. the throughhole portions of spacing conversion baseplate
96. the lower redistribution layer being fanned out to from die pad to TSV/TGV (near nude film)
97. the die pad for linking probe
98. " hinder into " region of signal route.It is special as much as possible in the region in reallocation region and TSV/TGV regions
For powering and being grounded route.
99. embedded element insert (referring to figure #1), as illustrated, for exchanging between embedded element is not integrated into
Away from conversion baseplate
100. signal Routing Area.These regions are located at outside die area, connect up and carry directly over nude film for passive element
For space.
Figure 19：The sectional view of embodiment #2 improved spacing conversion baseplate
101. the upper redistribution layer (relative with nude film) of the interface pad for being fanned out to ECI and probe card from TSV/TGV
102. the throughhole portions of spacing conversion baseplate
103. the lower redistribution layer being fanned out to from die pad to TSV/TGV (near nude film)
104. the die pad for linking probe
105. " hinder into " region of signal route.It is special as much as possible in the region in reallocation region and TSV/TGV regions
Door is used to powering and being grounded route.
106. the embedded element in spacing conversion baseplate (referring to figure #5).
107. signal Routing Area.These regions are located at outside die area, connect up and carry directly over nude film for passive element
For space.
Figure 20：The sectional view of embodiment #3 improved spacing conversion baseplate
108. the throughhole portions of spacing conversion baseplate
109. the lower redistribution layer being fanned out to from die pad to TSV/TGV (near nude film)
110. the die pad for linking probe
111. " hinder into " region of signal route.It is special as much as possible in the region in reallocation region and TSV/TGV regions
Door is used to powering and being grounded route.
112. the embedded element in spacing conversion baseplate (referring to figure #5).
113. signal Routing Area.These regions are located at outside die area, connect up and carry directly over nude film for passive element
For space.
The present invention is provided for improved spacing conversion baseplate and changed for positioning or being embedded in closer to spacing substantially
Three with some variations or modifications embodiment of the passive element of substrate.Each embodiment solves whole wafer probe should
Slightly different aspect.However, for each embodiment, the key improvements of the disclosure are used relative to prior art
In the position of the passive element of supply filtering/decoupling.Three all basic embodiments of the present invention are required for passive element is embedding
Enter near spacing conversion baseplate or physically in spacing conversion baseplate.By this way, the invention provides one kind to tie
Structure, wherein passive electronic components (such as discrete capacitor) can pass through embedded and thereby shortening passive element and tested nude film
Between physical distance and be significantly placed near tested nude film.The invention provides for realizing this embedded junction
The various embodiments of structure and method.
Fig. 1-2 0 referring to the drawings, Fig. 1-4 basically describe the first embodiment of the present invention, wherein decoupling element peace
Face is embedded in an insert configuration, and the insert configuration also serves as the connection machine between spacing conversion baseplate and probe card
Structure.The first embodiment has the advantages of interchangeability, because spacing conversion baseplate can be the consume member in high power capacity test
Part.Although more preferable than prior art, there are some hydraulic performance declines relative to other embodiments.The first embodiment can be with
It is used together with any type of spacing conversion baseplate.But the short electrical length of glass and silicon substrate is most favourable.
Fig. 1-4 described using the first main embodiment using sectional view conveyed for signal loading and power supply it is improved
The first embodiment of the present invention with three little deviations of method：With the company based on " TSV ", " TGV " or similar techniques
It is connected to the discrete insert of glass or the embedded element (passive) of silicon substrate spacing conversion baseplate.(TSV=penetrates silicon hole, TGV
=insertion glass through hole).Fig. 1 describes each element.Fig. 2 shows Fig. 1 after being assembled with " mission mode ".The descriptions of Fig. 3 and 4
One little deviation, wherein flexible interconnection are substituted by any type of more permanent connection, but typically solder and copper post.
In the embodiment in figure 1, compared with Figure 11 prior art, there are two basic distinctions.First, instead of Figure 11 traditional spacing
Conversion baseplate, Fig. 1 embodiment have the much smaller new spacing conversion baseplate 12 of the substrate width of the prior art than Figure 11.Figure
Compared with the thickness of the substrate of prior art of the new relatively thin substrate 12 with Figure 11 is 1 to 2 millimeter in 1, its thickness is 50 to 100
Micron
Secondly, in the embodiment in figure 1, electric capacity 8 or passive element 8 are located in insert 9.Therefore, because relatively thin base
The position of plate 12 and electric capacity or passive element 8 on insert 9, electric capacity 8 is more closer than the structure of prior art in Figure 11 to be visited
Pin card, the distance with probe card are 200-300 microns, and the distance of the structure of Figure 11 prior art is 44 millimeters or 4.5 millis
Rice is to 9 millimeters.Therefore, the structural improvement of first embodiment power filter and decoupling so that tested nude film can be with faster
Speed operation, include the speed of package level.This structure has very thin spacing conversion baseplate, is connected to passive decoupling member
Part, and reduce electrical length/delay in power source path.In this configuration, the route that is fanned out to of signal extends to spacing conversion
The periphery of substrate, to distinguish order of priority to power supply and ground connection route directly over nude film.In addition, in the structure shown here, power supply
Impedance loop reduces so that nude film can be with the faster speed operation including encapsulating step velocity.The structure allows the survey to nude film
Examination has the performance standard consistent with " Known good nude film ", and therefore allows performance level to test and encapsulated close to more nude films
Middle nude film and the performance level of nude film interconnection are tested.
Another advantage of the new structure of Fig. 1 embodiment is that substrate 12 is consume element and is interchangeable, and
The substrate of prior art is not interchangeable in Figure 11.Fig. 2 is the identical embodiment of the complete assembling forms of Fig. 1.
Fig. 3 is similar to Fig. 1 and 2 embodiment, except spacing conversion baseplate 12 is welded to passive element insert 9.
Whole circuit is welded together.Fig. 3 embodiment is more economical, because any interconnection for making us complaint need not be added.
Fig. 4 is the embodiment similar with Fig. 3, except circuit structure can be removed and change from probe card in figure 3.
In Fig. 4 embodiment, whole circuit structure is soldered to probe card 21.This make it that the embodiment is more reliable.
Second basic embodiment of the present invention is shown in fig. 5-7.Use adding for signal for the second main embodiment
Carry two little deviations with the sectional view of the improved method of power supply conveying：Based on " TSV ", " TGV " or similar technology, glass
Or the spacing conversion baseplate (PTS) of silicon substrate, wherein passive element are arranged on directly over spacing converter.These elements can be naked
Piece or the form of encapsulation.Fastening element with conductive path is permanently attached to spacing converter substrate as needed, is used for
Mechanical enhancer, more preferable durability and the conversion of big spacing.Fig. 5 describes each element.Fig. 6 is shown to be assembled with " mission mode "
Fig. 5.Fig. 7 describes a little deviation, and wherein flexible interconnection is typically welded by any type of more permanently connected replacement
Material and copper post.
In Figure 5,34-38,46 are marked to describe associated with the disclosure but specifically include necessity in the disclosure
Functional element.It is because they are representation function and are necessary relative to the improvement of prior art to show these elements.
Fig. 5 shows that the present invention is used for the portion for decoupling the second embodiment of the structure of passive element 41 (such as capacitor 41)
Divide view sub-anatomy, be connected directly to the top of upper table interplanar distance conversion baseplate 44.This eliminates the reality of Fig. 1-4 to the present invention
Apply the needs of the insert used in example.Passive element can be connected into spacing by the one of which in two methods to change
The top of substrate 44.First method is that element is welded to the top of substrate.Second is hot sonic bonds, and this is this area
Known technology.And heating capacitor, it is spoted weld the top of substrate.The dimensional thickness of substrate is for the embodiment and this hair
First embodiment in bright Fig. 1-4 is identical.
Fig. 6 is embodiment same as shown in Figure 5, be except it second embodiment of the invention complete assembling after regard
Figure.
Fig. 7 is similar with the embodiment of Fig. 5 and 6, is encapsulated except structure all welds together as one to provide more preferably
Reliability.
Fig. 8-10 basically describes the third embodiment of the present invention, and wherein passive element [65] is directly embedded into spacing and turned
Change in substrate [66].This requires that spacing conversion baseplate [65] is compatible with element insertion, and in element and spacing conversion baseplate
[65] under/basal surface between form thin redistribution layer.Passive embedded components [65] are created to crystalline substance using thin layer (being less than 5um)
The nearest possible position of circle/nude film [59].Different from the first and second embodiments of the present invention, the 3rd embodiment is without using thin
Spacing conversion baseplate --- using only thin lamination, as shown in figure 20.3rd embodiment also requires the wiring side shown in Figure 17
Method, the core away from conversion baseplate (surface of nude film) is prior to power supply and ground connection wiring among it.3rd embodiment has
Have all apart from gain of second embodiment, plus average 125um, for effective thickness of the central bay away from conversion baseplate.
As illustrated in fig. 12, the 3rd embodiment realizes the alap current supply circuit resistance from nude film to passive element
It is anti---- the first and second embodiments and all prior arts better than the present invention.Figure 13 A, 14A and 15A are by 3rd embodiment
Data eye and random data stream of the prior art respectively compared with, respectively 667MBs, 1000MBs and 2000MBs.Figure
16A is by the clock data of 3rd embodiment compared with prior art.
All embodiments are all embedded in a manner of passive decoupling and filter element are positioned closer into nude film in itself.The
One and second embodiment pass through it is embedded and using thin spacing conversion baseplate realize this point.Between 3rd embodiment is by being embedded in
Away from realizing this point in conversion baseplate, while use thin, very intensive redistribution layer.In all cases, these realities
Applying example significantly reduces current supply circuit impedance --- minimum 5 times (first embodiments) and up to 20 times (3rd embodiment) (referring to
Figure 12).
Fig. 8 shows the sectional exploded view of 3rd embodiment, wherein, a structure, which has, is completely embedded into what is formed by thin lamination
The passive component 65 of spacing conversion baseplate 66, as shown in figure 20, in the underface of thin electric signal redistribution layer, spacing conversion baseplate
Less preferably there are the identical width dimensions described in the spacing conversion baseplate of Fig. 1 of present invention first embodiment again.
The third embodiment of the present invention shown in Fig. 8 provides highest performance, because the passive element 65 of such as capacitor 65 is straight
Connect and be embedded into spacing conversion baseplate 66.Fig. 9 shows the embodiment that Fig. 8 is the view assembled completely.Figure 10 and Fig. 8 implementation
Example is similar, is all welded together as a unit.Figure 11 is previously discussed prior art construction.
Although in order to the disclosure and method and step setting in terms of permitted diverse purpose have been described currently preferably
Embodiment, but those skilled in the art can be with manufacture device part.Such change is included in be limited by appended claims
In fixed spirit of the invention.
Claims (24)
1. improved power supply transient performance (Power Integrity) structure of integrated circuit testing environment middle probe card component, including：
Thin spacing convertor base plate；Passive element is located in insert, and the insert also serves as spacing conversion baseplate and probe
Bindiny mechanism between card, passive element is set low impedance at high frequency is allowed nude film with package level close to the spacing conversion baseplate
Speed operation, so as to reduce the yield loss of package level.
2. structure according to claim 1, wherein the passive element is capacitor.
3. structure according to claim 1, wherein the spacing conversion baseplate is based on " TSV ", " TGV " or similar techniques
Glass or silicon substrate spacing convertor base plate.
4. structure according to claim 1, wherein the thickness of the thin substrate 1 is 50 to 100 microns.
5. structure according to claim 1, wherein the passive element on the insert close to the probe card simultaneously
And apart from the distance of the probe card about 200-300 microns.
6. structure according to claim 1, wherein the spacing conversion baseplate is replaceable.
7. structure according to claim 1, wherein, the spacing conversion baseplate is welded to the passive element insert.
8. structure according to claim 1, wherein, the total is welded to the probe card, described so as to strengthen
Reliability of structure.
9. structure according to claim 1, wherein, the passive electronic components, such as discrete capacitor, insertion can be passed through
And thereby shorten the method for the physical distance between passive element and tested nude film and be significantly placed on tested nude film
Near.
10. structure according to claim 1, wherein, the structural improvement power filter and decoupling so that tested nude film
It can at faster speed run, include the speed of package level.
11. structure according to claim 1, wherein, the substrate is very thin spacing conversion baseplate, is connected to described
Passive decoupling elements, and reduce electrical length/delay in supply path.
12. structure according to claim 1, wherein, the periphery for being fanned out to route and extending to spacing conversion baseplate of signal, with
Just order of priority is distinguished to power supply and ground connection route directly over nude film.
13. structure according to claim 12, wherein, current supply circuit impedance reduces so that nude film can be with including encapsulation
The faster speed operation of step velocity.
14. structure according to claim 1, wherein, the structure allow the test to nude film have with it is " Known good
The consistent performance standard of nude film ", and therefore allow performance level to test what is interconnected close to nude film in the encapsulation of more nude films with nude film
Performance level is tested.
15. structure according to claim 1, wherein, the element in probe test environment can be quick with the cost of minimum
Exchange, and embedded element will not be impacted.
16. improved power supply transient performance (Power Integrity) structure of integrated circuit testing environment middle probe card component, including
Thin spacing convertor base plate；Passive element is located in insert, the insert also serve as spacing conversion baseplate and probe card it
Between bindiny mechanism, make passive element close to the spacing conversion baseplate, low impedance at high frequency is allowed nude film with the speed of package level
Degree operation, so as to reduce the yield loss of package level.
17. structure according to claim 16, wherein, the passive element is described passive by using solder and copper post welding
Element is connected to the top of the spacing conversion baseplate to the top of the substrate.
18. structure according to claim 16, wherein the passive element is adheringly coupled to the spacing by thermoacoustic ripple
The top of conversion baseplate.
19. structure according to claim 1, wherein, the total is welded to the probe card, described so as to strengthen
Reliability of structure.
20. improved power supply transient performance (Power Integrity) structure of integrated circuit testing environment middle probe card component, including
The thin spacing convertor base plate that thin lamination is formed；Passive element is directly embedded into spacing conversion baseplate, the substrate with it is described
Element insertion is compatible, and further comprises between the lower surface or basal surface of the passive element and the spacing conversion baseplate
The thin redistribution layer formed, the thin layer provide the immediate possible position of the passive embedded element and wafer/nude film,
So that the passive element is close to the spacing conversion baseplate so that low impedance at high frequency allows nude film to be transported with the speed of package level
OK, so as to reducing the yield loss of package level.
21. structure according to claim 21, wherein, spacing conversion baseplate is compatible with element insertion, and in element and
Under spacing conversion baseplate/basal surface between form thin redistribution layer.
22. structure according to claim 21, wherein, the core of spacing conversion baseplate, the surface of nude film is shown
Wiring method prior to power supply and ground connection connect up.
23. the side of power supply transient performance (Power Integrity) structure for improving integrated circuit testing environment middle probe card component
Method, including：
Thin spacing convertor base plate is provided；And
Passive element is positioned in insert, the insert also serves as the connection machine between spacing conversion baseplate and probe card
Structure, make passive element close to the spacing conversion baseplate, make low impedance at high frequency allow nude film to be run with the speed of package level, so as to
Reduce the yield loss of package level.
24. the side of power supply transient performance (Power Integrity) structure for improving integrated circuit testing environment middle probe card component
Method, comprise the following steps：
A structure including passive element is directly completely embedded into the spacing conversion baseplate that thin lamination formed, make passive element close to
The spacing conversion baseplate, low impedance at high frequency is set to allow nude film to be run with the speed of package level, so as to reduce the finished product of package level
Rate is lost.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201562168107P | 2015-05-29 | 2015-05-29 | |
| US62/168,107 | 2015-05-29 | ||
| PCT/US2016/019865 WO2016195766A1 (en) | 2015-05-29 | 2016-02-26 | Improved power supply transient performance (power integrity) for a probe card assembly in an integrated circuit test environment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107710004A true CN107710004A (en) | 2018-02-16 |
Family
ID=57441201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201680031122.4A Pending CN107710004A (en) | 2015-05-29 | 2016-02-26 | The improved power supply transient performance of integrated circuit testing environment middle probe card component（Power Integrity） |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP3304110A4 (en) |
| JP (1) | JP2018523135A (en) |
| KR (1) | KR20180014781A (en) |
| CN (1) | CN107710004A (en) |
| TW (1) | TW201702613A (en) |
| WO (1) | WO2016195766A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107305217A (en) * | 2016-04-22 | 2017-10-31 | 新特系统股份有限公司 | Probe card |
| CN110824207A (en) * | 2018-08-08 | 2020-02-21 | 中华精测科技股份有限公司 | Radio frequency probe card device and interval conversion plate thereof |
| CN114860054A (en) * | 2022-07-05 | 2022-08-05 | 之江实验室 | Power supply device for wafer-level processor |
| TWI798125B (en) * | 2022-07-05 | 2023-04-01 | 中華精測科技股份有限公司 | Detachable testing device, holder thereof, and space transformer module thereof |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7170494B2 (en) * | 2018-10-15 | 2022-11-14 | 東京エレクトロン株式会社 | Intermediate connection member and inspection device |
| TWI684772B (en) * | 2019-03-11 | 2020-02-11 | 創意電子股份有限公司 | Inspecting device and its socket |
| US11143690B2 (en) * | 2019-10-02 | 2021-10-12 | Nanya Technology Corporation | Testing structure and testing method |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6336269B1 (en) * | 1993-11-16 | 2002-01-08 | Benjamin N. Eldridge | Method of fabricating an interconnection element |
| JP2003178847A (en) * | 2001-12-12 | 2003-06-27 | Yamaichi Electronics Co Ltd | Ic socket |
| TW557526B (en) * | 2001-03-16 | 2003-10-11 | Formfactor Inc | Wafer level interposer |
| CN1477691A (en) * | 2002-07-23 | 2004-02-25 | 富士通株式会社 | Method for testing probe board and semiconductor chip, capacitor and mfg. method thereof |
| CN1495870A (en) * | 1994-11-15 | 2004-05-12 | ��ķ�����عɷ�����˾ | Composite intermediate connection element of microelectronic component and its making method |
| US20070145989A1 (en) * | 2005-12-27 | 2007-06-28 | Hua Zhu | Probe card with improved transient power delivery |
| CN101308820A (en) * | 2004-04-09 | 2008-11-19 | 株式会社瑞萨科技 | Manufacturing method of semiconductor integrated circuit device and probe card |
| WO2009025427A1 (en) * | 2007-08-23 | 2009-02-26 | Gigalane Co.Ltd | Probe card |
| CN104345187A (en) * | 2013-07-26 | 2015-02-11 | 三星电机株式会社 | A plate used for a probe card, a manufacturing method thereof and the probe card |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4862077A (en) * | 1987-04-29 | 1989-08-29 | International Business Machines Corporation | Probe card apparatus and method of providing same with reconfigurable probe card circuitry |
| US6060891A (en) * | 1997-02-11 | 2000-05-09 | Micron Technology, Inc. | Probe card for semiconductor wafers and method and system for testing wafers |
| JP2004500699A (en) * | 1999-05-27 | 2004-01-08 | ナノネクサス インコーポレイテッド | Structure and manufacturing method of integrated circuit wafer probe card assembly |
| US6917525B2 (en) * | 2001-11-27 | 2005-07-12 | Nanonexus, Inc. | Construction structures and manufacturing processes for probe card assemblies and packages having wafer level springs |
| US8901950B2 (en) * | 2009-02-19 | 2014-12-02 | Advantest America, Inc | Probe head for a microelectronic contactor assembly, and methods of making same |
| US9263370B2 (en) * | 2013-09-27 | 2016-02-16 | Qualcomm Mems Technologies, Inc. | Semiconductor device with via bar |
-
2016
- 2016-02-26 KR KR1020177037840A patent/KR20180014781A/en not_active Application Discontinuation
- 2016-02-26 EP EP16803876.8A patent/EP3304110A4/en not_active Withdrawn
- 2016-02-26 JP JP2018514774A patent/JP2018523135A/en active Pending
- 2016-02-26 WO PCT/US2016/019865 patent/WO2016195766A1/en active Application Filing
- 2016-02-26 CN CN201680031122.4A patent/CN107710004A/en active Pending
- 2016-04-19 TW TW105112114A patent/TW201702613A/en unknown
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6336269B1 (en) * | 1993-11-16 | 2002-01-08 | Benjamin N. Eldridge | Method of fabricating an interconnection element |
| CN1495870A (en) * | 1994-11-15 | 2004-05-12 | ��ķ�����عɷ�����˾ | Composite intermediate connection element of microelectronic component and its making method |
| TW557526B (en) * | 2001-03-16 | 2003-10-11 | Formfactor Inc | Wafer level interposer |
| JP2003178847A (en) * | 2001-12-12 | 2003-06-27 | Yamaichi Electronics Co Ltd | Ic socket |
| CN1477691A (en) * | 2002-07-23 | 2004-02-25 | 富士通株式会社 | Method for testing probe board and semiconductor chip, capacitor and mfg. method thereof |
| CN101308820A (en) * | 2004-04-09 | 2008-11-19 | 株式会社瑞萨科技 | Manufacturing method of semiconductor integrated circuit device and probe card |
| US20070145989A1 (en) * | 2005-12-27 | 2007-06-28 | Hua Zhu | Probe card with improved transient power delivery |
| WO2009025427A1 (en) * | 2007-08-23 | 2009-02-26 | Gigalane Co.Ltd | Probe card |
| CN104345187A (en) * | 2013-07-26 | 2015-02-11 | 三星电机株式会社 | A plate used for a probe card, a manufacturing method thereof and the probe card |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107305217A (en) * | 2016-04-22 | 2017-10-31 | 新特系统股份有限公司 | Probe card |
| CN110824207A (en) * | 2018-08-08 | 2020-02-21 | 中华精测科技股份有限公司 | Radio frequency probe card device and interval conversion plate thereof |
| CN114860054A (en) * | 2022-07-05 | 2022-08-05 | 之江实验室 | Power supply device for wafer-level processor |
| TWI798125B (en) * | 2022-07-05 | 2023-04-01 | 中華精測科技股份有限公司 | Detachable testing device, holder thereof, and space transformer module thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2016195766A1 (en) | 2016-12-08 |
| EP3304110A4 (en) | 2019-01-23 |
| KR20180014781A (en) | 2018-02-09 |
| JP2018523135A (en) | 2018-08-16 |
| TW201702613A (en) | 2017-01-16 |
| EP3304110A1 (en) | 2018-04-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107710004A (en) | The improved power supply transient performance of integrated circuit testing environment middle probe card component（Power Integrity） | |
| KR101339493B1 (en) | Space Transformer for Probe Card and Manufacturing Method Thereof | |
| US7102367B2 (en) | Probe card and testing method of semiconductor chip, capacitor and manufacturing method thereof | |
| US7692436B2 (en) | Probe card substrate with bonded via | |
| KR100814177B1 (en) | Semiconductor device and process for fabricating the same | |
| JP4017186B2 (en) | Method and apparatus for non-conductively interconnecting integrated circuits | |
| US7088118B2 (en) | Modularized probe card for high frequency probing | |
| KR100690922B1 (en) | Semiconductor device package | |
| TWI522622B (en) | Probe head for a microelectronic contactor assembly, and the method of forming the same | |
| JP5567818B2 (en) | Semiconductor interposer and manufacturing method thereof (silicon interposer test for 3D chip stack) | |
| US6861858B2 (en) | Vertical probe card and method for using the same | |
| CN101459156B (en) | Semiconductor device | |
| KR20000052705A (en) | A system and method for packaging integrated circuits | |
| RU2715170C1 (en) | Integrated circuit modules and smart card including thereof | |
| CN108476585A (en) | PCB mixes redistribution layer | |
| KR20070103073A (en) | Probe card assembly and method of attaching probes to the probe card assembly | |
| US9793226B2 (en) | Power supply transient performance (power integrity) for a probe card assembly in an integrated circuit test environment | |
| US11129314B2 (en) | Stepped component assembly accommodated within a stepped cavity in component carrier | |
| Jin et al. | Introduction to microsystem packaging technology | |
| TW201626532A (en) | Wiring board with interposer and dual wiring structures integrated together and method of making the same | |
| US20040012405A1 (en) | Probe card with full wafer contact configuration | |
| US20060022688A1 (en) | Probe card | |
| CN105655321A (en) | Electronic packages and methods of making and using same | |
| US20030234660A1 (en) | Direct landing technology for wafer probe | |
| TW379394B (en) | A system and method for packaging integrated circuits |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20180216 |
|
| WD01 | Invention patent application deemed withdrawn after publication |