CN107707323B - A kind of method and clock calibrator (-ter) unit of clock alignment - Google Patents
A kind of method and clock calibrator (-ter) unit of clock alignment Download PDFInfo
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- CN107707323B CN107707323B CN201710557436.4A CN201710557436A CN107707323B CN 107707323 B CN107707323 B CN 107707323B CN 201710557436 A CN201710557436 A CN 201710557436A CN 107707323 B CN107707323 B CN 107707323B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
- H04W56/001—Synchronization between nodes
- H04W56/0015—Synchronization between nodes one node acting as a reference for the others
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
- H04W56/0035—Synchronisation arrangements detecting errors in frequency or phase
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Abstract
The present invention is suitable for field of communication technology, provides the method and clock calibrator (-ter) unit of a kind of clock alignment, which comprises receives the standard signal sequence sent by standard signal source；The standard signal sequence and clock signal to be calibrated are subjected to Frequency mixing processing, obtain mixed frequency signal；Calculate frequency deviation of the mixed frequency signal relative to the standard signal sequence；The clock signal is compensated using the frequency deviation, calibrates the clock signal.The deviation of clock signal is calibrated by way of calculating frequency deviation, implementation is simple, and calibration accuracy is high, and can carry out clock alignment to multiple equipment simultaneously by a standard signal source, is not influenced by equipment clock individual error, improves calibration efficiency.
Description
Technical field
The invention belongs to the methods and clock calibrator (-ter) unit of field of communication technology more particularly to a kind of clock alignment.
Background technique
Currently, be usually that present clock is input to a detection unit, by calculate present clock and calibration clock it
Between time difference, to realize the calibration to present clock.Situation higher for clock frequency, for example, bluetooth mixing clock be
2.4GHz directlys adopt reference clock to calibrate, and needs a precise clock source than 2.4GHz high, often makes calibration program
Complexity, calibration accuracy be difficult to ensure, and since there are individual errors for different equipment clocks, it is therefore desirable to mixing clock by
A calibration, it is complicated for operation, cause calibration efficiency low.
Summary of the invention
In view of this, the embodiment of the invention provides a kind of method of clock alignment and clock calibrator (-ter) unit, it is existing to solve
There is clock alignment precision in technology not high, the low problem of calibration efficiency.
The first aspect of the embodiment of the present invention provides a kind of method of clock alignment, comprising:
Receive the standard signal sequence sent by standard signal source；
The standard signal sequence and clock signal to be calibrated are subjected to Frequency mixing processing, obtain mixed frequency signal；
Calculate frequency deviation of the mixed frequency signal relative to the standard signal sequence；
The clock signal is compensated using the frequency deviation, calibrates the clock signal.
The second aspect of the embodiment of the present invention provides a kind of device of clock alignment, comprising:
Receiving module, for receiving the standard signal sequence sent by standard signal source；
Frequency mixing module is mixed for the standard signal sequence and clock signal to be calibrated to be carried out Frequency mixing processing
Frequency signal；
Computing module, for calculating frequency deviation of the mixed frequency signal relative to the standard signal sequence；
Compensating module calibrates the clock signal for compensating using the frequency deviation to the clock signal.
The third aspect of the embodiment of the present invention provides a kind of clock alignment equipment, including memory, processor and storage
On the memory and the computer program that can run on the processor, the processor execute the computer program
Shi Shixian following steps:
Receive the standard signal sequence sent by standard signal source；
The standard signal sequence and clock signal to be calibrated are subjected to Frequency mixing processing, obtain mixed frequency signal；
Calculate frequency deviation of the mixed frequency signal relative to the standard signal sequence；
The clock signal is compensated using the frequency deviation, calibrates the clock signal.
The fourth aspect of the embodiment of the present invention provides a kind of computer readable storage medium, the computer-readable storage
Media storage has computer program, and the computer program realizes following steps when being executed by processor:
Receive the standard signal sequence sent by standard signal source；
The standard signal sequence and clock signal to be calibrated are subjected to Frequency mixing processing, obtain mixed frequency signal；
Calculate frequency deviation of the mixed frequency signal relative to the standard signal sequence；
The clock signal is compensated using the frequency deviation, calibrates the clock signal.
Existing beneficial effect is the embodiment of the present invention compared with prior art: the standard signal that standard signal source is sent
Sequence and clock signal to be calibrated carry out Frequency mixing processing, after obtaining mixed frequency signal, calculate mixed frequency signal relative to standard signal
The frequency deviation of sequence compensates clock signal according to frequency deviation, calibrates clock signal, calibrates clock by way of calculating frequency deviation
The deviation of signal, implementation is simple, and calibration accuracy is high, and by a standard signal source can simultaneously to multiple equipment into
Row clock calibration, is not influenced by equipment clock individual error, improves calibration efficiency.
Detailed description of the invention
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to embodiment or description of the prior art
Needed in attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description is only of the invention some
Embodiment for those of ordinary skill in the art without any creative labor, can also be according to these
Attached drawing obtains other attached drawings.
Fig. 1 is a kind of implementation process schematic diagram of the method for clock alignment that the embodiment of the present invention one provides；
Fig. 2 is a kind of implementation process schematic diagram of the method for clock alignment provided by Embodiment 2 of the present invention；
Fig. 3 is to carry out clock school to multiple equipment simultaneously in a kind of method of clock alignment provided by Embodiment 2 of the present invention
Quasi- schematic diagram；
Fig. 4 is a kind of topology example figure of the device for clock alignment that the embodiment of the present invention three provides；
Fig. 5 is a kind of topology example figure of the device for clock alignment that the embodiment of the present invention four provides；
Fig. 6 is a kind of structural schematic diagram for clock alignment equipment that the embodiment of the present invention five provides.
Specific embodiment
In being described below, for illustration and not for limitation, the tool of such as particular system structure, technology etc is proposed
Body details, to understand thoroughly the embodiment of the present invention.However, it will be clear to one skilled in the art that there is no these specific
The present invention also may be implemented in the other embodiments of details.In other situations, it omits to well-known system, device, electricity
The detailed description of road and method, in case unnecessary details interferes description of the invention.
In order to illustrate technical solutions according to the invention, the following is a description of specific embodiments.
Embodiment one:
Fig. 1 is a kind of flow chart of the method for clock alignment that the embodiment of the present invention one provides, and the embodiment of the present invention is held
Row main body is clock alignment equipment, specifically can be the hardware device etc. comprising clock calibrating device, when Fig. 1 is exemplary a kind of
The method of clock calibration can specifically include step S101 to step S104, and details are as follows:
S101: the standard signal sequence sent by standard signal source is received.
Specifically, standard signal source issues the standard signal sequence of predetermined format, and clock alignment equipment is received by antenna
The standard signal sequence.
The standard signal sequence can be continuous 10101010 sequence, and the length of the sequence can be according to the needs of application
It is configured, it should be noted that the more long result finally calibrated of the length of the sequence is more accurate.
S102: standard signal sequence and clock signal to be calibrated are subjected to Frequency mixing processing, obtain mixed frequency signal.
Specifically, using low-noise amplifier (Low Noise Amplifier, LNA) to the standard signal sequence received
After column amplify processing, standard signal sequence is mixed with clock signal to be calibrated by frequency mixer, is mixed
Signal.
Further, clock signal to be calibrated is bluetooth 2.4GHz clock signal.
S103: frequency deviation of the mixed frequency signal relative to standard signal sequence is calculated.
When standard signal sequence to be mixed with clock signal, frequency deviation can be introduced.Frequency deviation is peculiar in frequency-modulated wave
Phenomenon refers to offset of the fixed FM wave frequency to two sides, indicates that frequency deviation, such as 1ppm indicate million usually using ppm
/ mono-.Frequency deviation is, since the number of clock multiplier is larger, to can generally achieve 150 times as caused by clock multiplier, therefore,
For the clock jitter of 1ppm, the deviation of 150ppm can be introduced after frequency multiplication.
Specifically, frequency deviation can be calculated by data aided algorithm or blind estimate algorithm etc., other frequency deviations can also be used
Estimating algorithm calculates frequency deviation, herein with no restrictions.
S104: clock signal to be calibrated is compensated using frequency deviation, calibrates the clock signal.
Specifically, the frequency deviation obtained according to step S103 compensates clock signal to be calibrated, to realize to this
The calibration of clock signal.
It should be noted that the computational accuracy of frequency deviation can be as accurate as the error range of 2KHz, therefore to 2.4GHz clock
The calibration accuracy of signal is approximately equal to 1ppm up to 2K/2.4G, and calibration error is small, and calibration accuracy is high, and calibration result can satisfy
The requirement of practical application.If direct calibration source clock, calibration accuracy is about 150ppm, relative to the calibration accuracy of 1ppm,
Its calibration error is very big, is extremely difficult to the requirement of practical application.If directly calibrating 2.4GHz clock frequency, need to compare
The higher precise clock source of 2.4GHz clock frequency realizes that difficulty is very big, and calibration efficiency is low.
Meanwhile using the clock correcting method of the embodiment of the present invention, it can only pass through a standard signal source broadcast standard
Signal sequence, while realizing and clock alignment is carried out simultaneously to multiple equipment, mode of operation is simple, effectively improves calibration efficiency.
In the present embodiment, carry out the standard signal sequence that standard signal source is sent to be mixed place with clock signal to be calibrated
Reason, after obtaining mixed frequency signal, calculates frequency deviation of the mixed frequency signal relative to standard signal sequence, is carried out according to frequency deviation to clock signal
Compensation calibrates clock signal, the deviation of clock signal is calibrated by way of calculating frequency deviation, implementation is simple, calibration accuracy
Height, and clock alignment can be carried out to multiple equipment simultaneously by a standard signal source, not by equipment clock individual error
Influence, improve calibration efficiency.
Embodiment two:
Fig. 2 is a kind of flow chart of the method for clock alignment provided by Embodiment 2 of the present invention, and the embodiment of the present invention is held
Row main body is clock alignment equipment, specifically can be the hardware device etc. comprising clock calibrating device, when Fig. 2 is exemplary a kind of
The method of clock calibration can specifically include step S201 to step S205, and details are as follows:
S201: the standard signal sequence sent by standard signal source is received.
Specifically, standard signal source issues the standard signal sequence of predetermined format, and clock alignment equipment is received by antenna
The standard signal sequence.
Standard signal sequence may include the protocol Data Unit of leader sequence, access address and preset length.Preferably,
The data format of standard signal sequence is specifically as follows:
| Preamble(8bit) | Access Address(32bit) | PDU (16bit~2056bit) | CRC(246bit) |
Preamble is leader sequence, and what will be sent for alerting signal receiving end is useful signal, pays attention to receiving, with
Exempt to lose useful signal.
Access Address is access address, can be set to arbitrary value.
PDU is protocol Data Unit (Protocol Data Unit), is used for transmission specific valid data, can be set
It, specifically can be according to practical application for the maximum length that continuous 10101010 sequence, the length of the sequence can allow for PDU
Needs be configured, it should be noted that the more long result finally calibrated of the length of the sequence is more accurate.
CRC is cyclic redundancy check (Cyclic Redundancy Check), for verifying to the data of transmission.
S202: standard signal sequence and clock signal to be calibrated are subjected to Frequency mixing processing, obtain mixed frequency signal.
Specifically, after amplifying processing to the standard signal sequence received using LNA, standard is believed by frequency mixer
Number sequence is mixed with clock signal to be calibrated, obtains mixed frequency signal.
Further, clock signal to be calibrated is bluetooth 2.4GHz clock signal.
After obtaining mixed frequency signal, frequency deviation of the mixed frequency signal relative to standard signal sequence is calculated.Preferably, can pass through
Following steps S203 to step S204 realizes the calculating to frequency deviation, and details are as follows:
S203: pre-processing mixed frequency signal, obtains protocol Data Unit corresponding data-signal in mixed frequency signal
Sequence.
Specifically, the obtained mixed frequency signal of step S202 is pre-processed, by pretreated process from mixed frequency signal
The corresponding data signal sequence of protocol Data Unit in middle extraction standard signal sequence.
Further, preprocessing process can realize that detailed description are as follows with S2031 as follows to step S2033:
S2031: analog-to-digital conversion is carried out to mixed frequency signal.
Specifically, analog-to-digital conversion is carried out to the mixed frequency signal that step S202 is obtained using analog-digital converter ADC, simulation is believed
Number be converted to digital signal.
S2032: automatic growth control and filtering processing are carried out to the mixed frequency signal after analog-to-digital conversion, obtain letter to be matched
Number；
Specifically, digital signal step S2031 being converted to passes through automatic growth control (automatic gain
Control, AGC) and filtering processing, removal is interfered and the influence of noise signal, obtains signal to be matched.
S2033: signal to be matched is matched according to leader sequence and access address, extracts data signal sequence.
Specifically, leader sequence is matched from signal to be matched and access address obtains if successful match according to matching
Register sequence and access address, extract data signal sequence after access address.
S204: frequency deviation is calculated according to data signal sequence.
Specifically, calculating frequency deviation according to data signal sequence can be completed by step S2041 to step S2042, in detail
It is described as follows:
S2041: the corresponding frequency values of each signal position in data signal sequence are obtained.
Specifically, the data signal sequence extracted according to step S2033, obtains each signal position in the data signal sequence
Corresponding frequency values.
S2042: according to preset length, the average value of each frequency values is calculated, frequency deviation is obtained.
Specifically, according to the preset length of PDU in standard signal sequence, each signal position pair in data signal sequence is calculated
The average value for the frequency values answered, the average value are frequency deviation.
For example, the part PDU in standard signal sequence is 10101010 sequences of standard, after by step S2033
The digital signal sequences extracted are 10101010 sequences with frequency deviation, the corresponding frequency of each signal position in the data signal sequence
Rate value is respectively x1,x2,...,xk, wherein the value of k is the preset length of signal position corresponding signal sampling point number and PDU
Product, usual number of sampling points be 8, k can with value be 32,64,128,256 etc., the knot of its bigger clock alignment of the value of k
Fruit is more accurate, then specifically can calculate frequency deviation freq_offset according to following formula.
S205: clock signal to be calibrated is compensated using frequency deviation, calibrates the clock signal.
Specifically, the frequency deviation obtained according to step S204 compensates clock signal to be calibrated, to realize to this
The calibration of clock signal.
It should be noted that the computational accuracy of frequency deviation can be as accurate as the error range of 2KHz, therefore to 2.4GHz clock
The calibration accuracy of signal is approximately equal to 1ppm up to 2K/2.4G, and calibration error is small, and calibration accuracy is high, and calibration result can satisfy
The requirement of practical application.If direct calibration source clock, calibration accuracy is about 150ppm, relative to the calibration accuracy of 1ppm,
Its calibration error is very big, is extremely difficult to the requirement of practical application.If directly calibrating 2.4GHz clock frequency, need to compare
The higher precise clock source of 2.4GHz clock frequency realizes that difficulty is very big, and calibration efficiency is low.
Meanwhile using the clock correcting method of the embodiment of the present invention, it can only pass through a standard signal source broadcast standard
Signal sequence, while realizing and clock alignment is carried out simultaneously to multiple equipment, mode of operation is simple, effectively improves calibration efficiency.
As shown in figure 3, Fig. 3 shows the method using the embodiment of the present invention simultaneously to multiple equipment (equipment 1, equipment
The schematic diagram of 2 ..., equipment n) progress clock alignment.Wherein, standard signal source broadcast standards signals sequence, each equipment will connect
The standard signal sequence received carries out after LAN amplifies processing in frequency mixer Mixer and 2.4GHz clock signal
Mixing carries out analog-to-digital conversion by analog-digital converter ADC to obtained mixed frequency signal, and the number obtained after analog-to-digital conversion is believed
Number input synchronous detection module, matches Preamble and Access Address, successful match be confirmed as it is synchronous at
The digital signal input frequency offset correction module of the obtained part PDU is calculated frequency deviation according to matching result, then by frequency deviation school by function
The frequency deviation f of quasi-mode block output inputs Mixer as offset, realizes the calibration to 2.4GHz clock signal.
Preamble and Access Address is matched by synchronous detection module, and the basis after successful match
The digital signal for the part PDU extracted carries out the calculating of frequency deviation, can guarantee the validity of frequency offset calculation starting point data, energy
Enough improve calibration accuracy.
In the present embodiment, carry out the standard signal sequence that standard signal source is sent to be mixed place with clock signal to be calibrated
Reason after obtaining mixed frequency signal, carries out analog-to-digital conversion to mixed frequency signal, obtains letter to be matched after automatic growth control and filtering processing
Number, which is matched according to leader sequence and access address, therefrom extracts data signal sequence, is believed further according to the data
Number sequence calculates frequency deviation, is finally compensated according to the frequency deviation to clock signal, calibrates clock signal, passes through the side for calculating frequency deviation
Formula calibrates the deviation of clock signal, and implementation is simple, and calibration accuracy is high, and can be right simultaneously by a standard signal source
Multiple equipment carry out clock alignment, do not influenced by equipment clock individual error, improve calibration efficiency, while by pair
Preamble and Access Address is matched, and according to the digital signal for the part PDU extracted after successful match
The calculating for carrying out frequency deviation can guarantee the validity of frequency offset calculation starting point data, improve calibration accuracy.
It should be understood that the size of the serial number of each step is not meant that the order of the execution order in above-described embodiment, each process
Execution sequence should be determined by its function and internal logic, the implementation process without coping with the embodiment of the present invention constitutes any limit
It is fixed.
A kind of method of clock alignment is essentially described above, is below retouched the device to a kind of clock alignment in detail
It states.
Embodiment three:
Fig. 4 is a kind of structural schematic diagram of the device for clock alignment that the embodiment of the present invention three provides, for ease of description,
Only parts related to embodiments of the present invention are shown.A kind of exemplary device of clock alignment of Fig. 4 can be previous embodiment
The executing subject of the method for one clock alignment provided.A kind of exemplary device of clock alignment of Fig. 4 include: receiving module 31,
Frequency mixing module 32, computing module 33 and compensating module 34, detailed description are as follows for each functional module:
Receiving module 31, for receiving the standard signal sequence sent by standard signal source；
Frequency mixing module 32 is obtained for the standard signal sequence and clock signal to be calibrated to be carried out Frequency mixing processing
Mixed frequency signal；
Computing module 33, for calculating frequency deviation of the mixed frequency signal relative to the standard signal sequence；
Compensating module 34 calibrates the clock signal for compensating using the frequency deviation to the clock signal.
Each module realizes the process of respective function in a kind of device of clock alignment provided in this embodiment, specifically refers to
The description of aforementioned embodiment illustrated in fig. 1, details are not described herein again.
From a kind of exemplary device of clock alignment of above-mentioned Fig. 4 it is found that in the present embodiment, by the mark of standard signal source transmission
Calibration signal sequence and clock signal to be calibrated carry out Frequency mixing processing, after obtaining mixed frequency signal, calculate mixed frequency signal relative to mark
The frequency deviation of calibration signal sequence compensates clock signal according to frequency deviation, calibrates clock signal, the school by way of calculating frequency deviation
The deviation of clock signal, implementation is simple, and calibration accuracy is high, and can be simultaneously to multiple by a standard signal source
Equipment carries out clock alignment, is not influenced by equipment clock individual error, and calibration efficiency is improved.
Example IV:
Fig. 5 is a kind of structural schematic diagram of the device for clock alignment that the embodiment of the present invention four provides, for ease of description,
Only parts related to embodiments of the present invention are shown.A kind of exemplary device of clock alignment of Fig. 5 can be previous embodiment
The executing subject of the method for two clock alignments provided.A kind of exemplary device of clock alignment of Fig. 5 include: receiving module 41,
Frequency mixing module 42, computing module 43 and compensating module 44, detailed description are as follows for each functional module:
Receiving module 41, for receiving the standard signal sequence sent by standard signal source；
Frequency mixing module 42 is obtained for the standard signal sequence and clock signal to be calibrated to be carried out Frequency mixing processing
Mixed frequency signal；
Computing module 43, for calculating frequency deviation of the mixed frequency signal relative to the standard signal sequence；
Compensating module 44 calibrates the clock signal for compensating using the frequency deviation to the clock signal.
Further, the standard signal sequence includes the protocol data list of leader sequence, access address and preset length
Member, the computing module 43 include:
It pre-processes submodule 431 and obtains the protocol Data Unit in institute for pre-processing to the mixed frequency signal
State corresponding data signal sequence in mixed frequency signal；
Frequency deviation submodule 432, for calculating the frequency deviation according to the data signal sequence.
Further, frequency deviation submodule 432 is also used to:
Obtain the corresponding frequency values of each signal position in the data signal sequence；
According to the preset length, the average value of each frequency values is calculated, the frequency deviation is obtained.
Further, pretreatment submodule 431 is also used to:
Analog-to-digital conversion is carried out to the mixed frequency signal；
Automatic growth control and filtering processing are carried out to the mixed frequency signal after analog-to-digital conversion, obtain signal to be matched；
The signal to be matched is matched according to the leader sequence and the access address, extracts the data-signal sequence
Column.
Further, the clock signal to be calibrated is bluetooth 2.4GHz clock signal.
Each module realizes the process of respective function in a kind of device of clock alignment provided in this embodiment, specifically refers to
The description of aforementioned embodiment illustrated in fig. 2, details are not described herein again.
From a kind of exemplary device of clock alignment of above-mentioned Fig. 5 it is found that in the present embodiment, by the mark of standard signal source transmission
Calibration signal sequence and clock signal to be calibrated carry out Frequency mixing processing, after obtaining mixed frequency signal, carry out modulus to mixed frequency signal and turn
It changes, obtains signal to be matched after automatic growth control and filtering processing, it is to be matched to match this according to leader sequence and access address
Signal therefrom extracts data signal sequence, calculates frequency deviation further according to the data signal sequence, is finally believed according to the frequency deviation clock
It number compensates, calibrates clock signal, the deviation of clock signal is calibrated by way of calculating frequency deviation, implementation is simple, school
Quasi- precision is high, and can carry out clock alignment to multiple equipment simultaneously by a standard signal source, not by equipment clock
The influence of body error improves calibration efficiency, while by matching to Preamble and Access Address, and is matching
The calculating for carrying out frequency deviation after success according to the digital signal for the part PDU extracted, can guarantee frequency offset calculation starting point data
Validity, improve calibration accuracy.
Embodiment five:
Fig. 6 is the schematic diagram for the clock alignment equipment that the embodiment of the present invention five provides.As shown in fig. 6, the embodiment when
Clock calibrator (-ter) unit 5 includes: processor 50, memory 51 and is stored in the memory 51 and can be on the processor 50
The computer program 52 of operation, such as clock alignment program.The processor 50 is realized when executing the computer program 52
State the step in the embodiment of the method for each clock alignment, such as step S101 to S104 shown in FIG. 1.Alternatively, the processing
Device 50 realizes the function of each module/submodule in above-mentioned each Installation practice, such as Fig. 4 institute when executing the computer program 52
Show the function of module 31 to 34.
Illustratively, the computer program 52 can be divided into one or more module/units, it is one or
Multiple module/units are stored in the memory 51, and are executed by the processor 50, to complete the present invention.Described one
A or multiple module/units can be the series of computation machine program instruction section that can complete specific function, which is used for
Implementation procedure of the computer program 52 in the clock alignment equipment 5 is described.For example, the computer program 52 can be with
It is divided into receiving module, frequency mixing module, computing module and compensating module, each module concrete function is as follows:
Receiving module, for receiving the standard signal sequence sent by standard signal source；
Frequency mixing module is mixed for the standard signal sequence and clock signal to be calibrated to be carried out Frequency mixing processing
Frequency signal；
Computing module, for calculating frequency deviation of the mixed frequency signal relative to the standard signal sequence；
Compensating module calibrates the clock signal for compensating using the frequency deviation to the clock signal.
Further, the standard signal sequence includes the protocol data list of leader sequence, access address and preset length
Member, the computing module include:
It pre-processes submodule and obtains the protocol Data Unit described for pre-processing to the mixed frequency signal
Corresponding data signal sequence in mixed frequency signal；
Frequency deviation submodule, for calculating the frequency deviation according to the data signal sequence.
Further, the frequency deviation submodule is also used to:
Obtain the corresponding frequency values of each signal position in the data signal sequence；
According to the preset length, the average value of each frequency values is calculated, the frequency deviation is obtained.
Further, the pretreatment submodule is also used to:
Analog-to-digital conversion is carried out to the mixed frequency signal；
Automatic growth control and filtering processing are carried out to the mixed frequency signal after analog-to-digital conversion, obtain signal to be matched；
The signal to be matched is matched according to the leader sequence and the access address, extracts the data-signal sequence
Column.
Further, the clock signal to be calibrated is bluetooth 2.4GHz clock signal.
The clock alignment equipment 5 can be the needs such as desktop PC, notebook, palm PC and cloud server
The equipment for carrying out clock alignment, specifically can be bluetooth equipment.The clock alignment equipment may include, but be not limited only to, place
Manage device 50, memory 51.It will be understood by those skilled in the art that Fig. 6 is only the example of clock alignment equipment 5, do not constitute
Restriction to clock calibrator (-ter) unit 5 may include perhaps combining certain components or not than illustrating more or fewer components
Same component, such as the clock alignment equipment can also include input-output equipment, network access equipment, bus etc..
Alleged processor 50 can be central processing unit (Central Processing Unit, CPU), can also be
Other general processors, digital signal processor (Digital Signal Processor, DSP), specific integrated circuit
(Application Specific Integrated Circuit, ASIC), ready-made programmable gate array (Field-
Programmable Gate Array, FPGA) either other programmable logic device, discrete gate or transistor logic,
Discrete hardware components etc..General processor can be microprocessor or the processor is also possible to any conventional processor
Deng.
The memory 51 can be the internal storage unit of the clock alignment equipment 5, such as clock alignment equipment 5
Hard disk or memory.The memory 51 is also possible to the External memory equipment of the clock alignment equipment 5, such as the clock school
The plug-in type hard disk being equipped in quasi- equipment 5, intelligent memory card (Smart Media Card, SMC), secure digital (Secure
Digital, SD) card, flash card (Flash Card) etc..Further, the memory 51 can also both include the clock
The internal storage unit of calibrator (-ter) unit 5 also includes External memory equipment.The memory 51 is for storing the computer program
And other programs and data needed for the clock alignment equipment.The memory 51 can be also used for temporarily storing
Output or the data that will be exported.
It is apparent to those skilled in the art that for convenience of description and succinctly, only with above-mentioned each function
Can unit, module division progress for example, in practical application, can according to need and by above-mentioned function distribution by different
Functional unit, module are completed, i.e., the internal structure of described device is divided into different functional unit or module, more than completing
The all or part of function of description.Each functional unit in embodiment, module can integrate in one processing unit, can also
To be that each unit physically exists alone, can also be integrated in one unit with two or more units, it is above-mentioned integrated
Unit both can take the form of hardware realization, can also realize in the form of software functional units.In addition, each function list
Member, the specific name of module are also only for convenience of distinguishing each other, the protection scope being not intended to limit this application.Above system
The specific work process of middle unit, module, can refer to corresponding processes in the foregoing method embodiment, and details are not described herein.
In the above-described embodiments, it all emphasizes particularly on different fields to the description of each embodiment, is not described in detail or remembers in some embodiment
The part of load may refer to the associated description of other embodiments.
Those of ordinary skill in the art may be aware that list described in conjunction with the examples disclosed in the embodiments of the present disclosure
Member and algorithm steps can be realized with the combination of electronic hardware or computer software and electronic hardware.These functions are actually
It is implemented in hardware or software, the specific application and design constraint depending on technical solution.Professional technician
Each specific application can be used different methods to achieve the described function, but this realization is it is not considered that exceed
The scope of the present invention.
In embodiment provided by the present invention, it should be understood that disclosed device/terminal device and method, it can be with
It realizes by another way.For example, device described above/terminal device embodiment is only schematical, for example, institute
The division of module or unit is stated, only a kind of logical function partition, there may be another division manner in actual implementation, such as
Multiple units or components can be combined or can be integrated into another system, or some features can be ignored or not executed.Separately
A bit, shown or discussed mutual coupling or direct-coupling or communication connection can be through some interfaces, device
Or the INDIRECT COUPLING or communication connection of unit, it can be electrical property, mechanical or other forms.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple
In network unit.It can select some or all of unit therein according to the actual needs to realize the mesh of this embodiment scheme
's.
It, can also be in addition, the functional units in various embodiments of the present invention may be integrated into one processing unit
It is that each unit physically exists alone, can also be integrated in one unit with two or more units.Above-mentioned integrated list
Member both can take the form of hardware realization, can also realize in the form of software functional units.
If the integrated module/unit be realized in the form of SFU software functional unit and as independent product sale or
In use, can store in a computer readable storage medium.Based on this understanding, the present invention realizes above-mentioned implementation
All or part of the process in example method, can also instruct relevant hardware to complete, the meter by computer program
Calculation machine program can be stored in a computer readable storage medium, the computer program when being executed by processor, it can be achieved that on
The step of stating each embodiment of the method.Wherein, the computer program includes computer program code, the computer program
Code can be source code form, object identification code form, executable file or certain intermediate forms etc..Computer-readable Jie
Matter may include: can carry the computer program code any entity or device, recording medium, USB flash disk, mobile hard disk,
Magnetic disk, CD, computer storage, read-only memory (ROM, Read-Only Memory), random access memory (RAM,
Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium etc..It should be noted that described
The content that computer-readable medium includes can carry out increasing appropriate according to the requirement made laws in jurisdiction with patent practice
Subtract, such as does not include electric carrier signal and electricity according to legislation and patent practice, computer-readable medium in certain jurisdictions
Believe signal.
Embodiment described above is merely illustrative of the technical solution of the present invention, rather than its limitations；Although referring to aforementioned reality
Applying example, invention is explained in detail, those skilled in the art should understand that: it still can be to aforementioned each
Technical solution documented by embodiment is modified or equivalent replacement of some of the technical features；And these are modified
Or replacement, the spirit and scope for technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution should all
It is included within protection scope of the present invention.
Claims (10)
1. a kind of method of clock alignment, which is characterized in that the described method includes:
Receive the standard signal sequence sent by standard signal source；The continuous sequence that the standard signal sequence is made of 1 and 0
Column, the length of the sequence is configured according to the needs of application and the more long final calibration result of length is more accurate；
The standard signal sequence and clock signal to be calibrated are subjected to Frequency mixing processing, obtain mixed frequency signal；
Calculate frequency deviation of the mixed frequency signal relative to the standard signal sequence；
The clock signal is compensated using the frequency deviation, calibrates the clock signal.
2. the method as described in claim 1, which is characterized in that the standard signal sequence includes leader sequence, access address
With the protocol Data Unit of preset length, the frequency deviation packet for calculating the mixed frequency signal relative to the standard signal sequence
It includes:
The mixed frequency signal is pre-processed, the protocol Data Unit corresponding data letter in the mixed frequency signal is obtained
Number sequence；
The frequency deviation is calculated according to the data signal sequence.
3. method according to claim 2, which is characterized in that described to calculate the frequency deviation packet according to the data signal sequence
It includes:
Obtain the corresponding frequency values of each signal position in the data signal sequence；
According to the preset length, the average value of each frequency values is calculated, the frequency deviation is obtained.
4. method according to claim 2, which is characterized in that it is described that the mixed frequency signal is pre-processed, it obtains described
Protocol Data Unit corresponding data signal sequence in the mixed frequency signal includes:
Analog-to-digital conversion is carried out to the mixed frequency signal；
Automatic growth control and filtering processing are carried out to the mixed frequency signal after analog-to-digital conversion, obtain signal to be matched；
The signal to be matched is matched according to the leader sequence and the access address, extracts the data signal sequence.
5. such as the described in any item methods of Claims 1-4, which is characterized in that the clock signal to be calibrated is bluetooth
2.4GHz clock signal.
6. a kind of device of clock alignment, which is characterized in that described device includes:
Receiving module, for receiving the standard signal sequence sent by standard signal source；The standard signal sequence is by 1 and 0
The length of the continuous sequence of composition, the sequence is configured according to the needs of application and the more long final calibration result of length is more smart
Really；
Frequency mixing module obtains mixing letter for the standard signal sequence and clock signal to be calibrated to be carried out Frequency mixing processing
Number；
Computing module, for calculating frequency deviation of the mixed frequency signal relative to the standard signal sequence；
Compensating module calibrates the clock signal for compensating using the frequency deviation to the clock signal.
7. device as claimed in claim 6, which is characterized in that the standard signal sequence includes leader sequence, access address
With the protocol Data Unit of preset length, the computing module includes:
It pre-processes submodule and obtains the protocol Data Unit in the mixing for pre-processing to the mixed frequency signal
Corresponding data signal sequence in signal；
Frequency deviation submodule, for calculating the frequency deviation according to the data signal sequence.
8. device as claimed in claim 7, which is characterized in that the frequency deviation submodule is also used to:
Obtain the corresponding frequency values of each signal position in the data signal sequence；
According to the preset length, the average value of each frequency values is calculated, the frequency deviation is obtained.
9. a kind of clock alignment equipment, including memory, processor and storage are in the memory and can be in the processing
The computer program run on device, which is characterized in that the processor realizes such as claim 1 when executing the computer program
The step of to any one of 5 the method.
10. a kind of computer readable storage medium, the computer-readable recording medium storage has computer program, and feature exists
In when the computer program is executed by processor the step of any one of such as claim 1 to 5 of realization the method.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1309483A (en) * | 2000-02-16 | 2001-08-22 | 汤姆森特许公司 | Local oscillator frequency correction in quadrature frequency-division multiplex system |
| WO2005043852A1 (en) * | 2003-11-03 | 2005-05-12 | Koninklijke Philips Electronics N.V. | Apparatus for determining a frequency offset error and receiver based thereon |
| CN102196468A (en) * | 2010-03-10 | 2011-09-21 | 美国博通公司 | Communication method and communication system |
| CN102664859A (en) * | 2012-05-22 | 2012-09-12 | 天津工业大学 | Synchronization and channel estimation scheme for multi-band orthogonal frequency division multiplexing (OFDM) ultra wideband receiver |
-
2017
- 2017-07-10 CN CN201710557436.4A patent/CN107707323B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1309483A (en) * | 2000-02-16 | 2001-08-22 | 汤姆森特许公司 | Local oscillator frequency correction in quadrature frequency-division multiplex system |
| WO2005043852A1 (en) * | 2003-11-03 | 2005-05-12 | Koninklijke Philips Electronics N.V. | Apparatus for determining a frequency offset error and receiver based thereon |
| CN102196468A (en) * | 2010-03-10 | 2011-09-21 | 美国博通公司 | Communication method and communication system |
| CN102664859A (en) * | 2012-05-22 | 2012-09-12 | 天津工业大学 | Synchronization and channel estimation scheme for multi-band orthogonal frequency division multiplexing (OFDM) ultra wideband receiver |
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