CN107707217A - The broadband of high dB gains becomes six active phase shifters of mutual conductance - Google Patents
The broadband of high dB gains becomes six active phase shifters of mutual conductance Download PDFInfo
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Abstract
The invention discloses a kind of broadband of high dB gains to become six active phase shifters of mutual conductance, mainly solves the problems, such as that image current error is larger in existing phase shifter.It includes single-turn double balun, orthogonal signal generator, analog adder, buffer and control circuits.After radiofrequency signal enters active balun circuit, single-ended radio frequency signal is changed into opposite in phase and amplitude identical differential signal, improves the entire gain of circuit.Differential signal is after three limit orthogonal signal generators, produce input of four amplitude identical orthogonal signalling as analog adder, in the presence of controller, the signal of the phase shifts such as cluster is synthesized by way of orthogonal vector synthesis, buffered device acts on obtaining the output signal of phase shifter.The present invention not only increases on phase accuracy, and makes passive module gain reduction smaller, while avoids using D/A converting circuit the power consumption for apply bias current, reducing circuit, available in RF IC.
Description
The invention belongs to technical field of electronic devices, and in particular to a kind of 3 to six active shiftings in 8GHZ frequency ranges
Phase device, in the RF IC available for the needs high accuracy phase shifter such as frequency microwave phased-array receiver.
Background technology
The phased-array technique of early stage utilizes the theory developmental research of Mixed Design, mainly including transistor, unit phase shifter
Deng.With the development of solid-state semiconductor integrated circuit technique, a part of control electronics use III-V half
The integrated form on a single chip of conductor, such as GaAs, GaN or InP.And typical analog component is exactly to pass through iii-v
Technology is realized, while silicon substrate DSP can fit together with printed circuit board (PCB), similar to business PC mainboard structures.
Although III-V technologies provide high Q passive devices and low-loss, the switch of high-isolation, this be with sacrifice into
This and chip area are cost.In addition, the important breakthrough in silicon technology upper part field, reduces phased array skill to a certain extent
The cost of art, particularly silicon germanium material it is verified for low power electronic device up in the range of millimeter-wave frequency have with
The comparable property of III-V material.Therefore, with current technological level, the main reality that interlock circuit is carried out using silicon germanium material
It is existing.
Based on SiGe process condition, in phased array transceiver, the species of phase shifter mainly has loading wire type phase shifter, anti-
Penetrate formula phase shifter, switch-line phase shifter, high pass low pass phase shifter and Vector Modulation phase shifter etc..Wherein, passed using switch
Defeated line, 90 degree of hybrid coupled lines, the passive phase shifter of cyclic loading line composition have grown up.But runed in business IC
In their physical size prevent they from poly array integrate.In order to solve this problem, arrived using distributed network
The synthesis topological structure of lamped element parameter transformation, the physical size of phase shifter can be reduced.However, in being run in broadband, by
In the speed that the size of lumped passive network increases quickly, the requirement of chip size can not be met, this is primarily due to respectively
The use of kind on-chip inductor.Therefore, the integrated phased array system being not particularly suited on chip.It is active compared with passive design
Phase shifter is controlled by good digit phase in the presence of driving load, can obtain higher integrated level.
As shown in figure 1, active phase shifter is typically mirrored to analog addition using reference current by D/A converting circuit DAC
Electric current in the metal-oxide-semiconductor of device as path, and then by opening the relation of radical sign in circuit between electric current and gain, derive correspondingly
Phase size.The shortcomings that this active phase shifter is that change in size is larger between each transistor, it is impossible to is completely secured correspondingly
Transistor is operated in appropriate region, while the error between image current can also produce certain influence to phase.
The content of the invention
It is an object of the invention to the deficiency for above-mentioned existing active phase shifter, proposes that a kind of broadband of high dB gains becomes
Six active phase shifters of mutual conductance, to fix the size of transistor in active phase shifter, reduce image current error, improve phase essence
Degree.
To achieve the above object, the broadband of high dB gains of the invention becomes six active phase shifters of mutual conductance, including：Single-turn is double
Balun, orthogonal signal generator, analog adder, buffer and controller, single-turn double balun, orthogonal signal generator, simulations
Adder, buffer are sequentially connected, and controller is connected with analog adder, it is characterised in that：
The analog adder, using cascode amplifier, by changing grid voltage so that the quantitative change such as gain of circuit
Change, the signal that output amplitude is continuous and phase is flat；
The controller, the crystal directly acted on using bias voltage caused by variable resistance circuit in analog adder
Tube grid, from the radiofrequency signal of the phase shifts such as the output port generation of analog adder.
Preferably, the cascode amplifier includes：Active inductance, four groups of nmos pass transistors, four path analoging switch, should
The both ends of active inductance connect one end and the supply voltage VDD of four path analoging switch, the other end point of four path analoging switch respectively
The output port of four groups of nmos pass transistors is not connected, and the other end of four groups of nmos pass transistors is connected to the ground GND；
Preferably, the double baluns of the single-turn include：Active inductance, PMOS current mirrors, difference block, biasing resistor, filter
Ripple electric capacity and shunt capacitance, the both ends of the active inductance connect the output port and supply voltage VDD of difference block respectively, should
The both ends of PMOS current mirrors connect the output port and supply voltage VDD of difference block, the both ends difference of the biasing resistor respectively
The control port and bias voltage of difference block are connected, the both ends of the filter capacitor connect difference block input port and penetrated respectively
Frequency input signal, the both ends of the shunt capacitance connect one end and the ground GND of biasing resistor respectively；
Preferably, the buffer includes：Amplification module, load resistance, biasing resistor, shunt capacitance, filter capacitor
With NPN triode current mirror, one end of the output port connection load resistance of the amplification module, the other end connection of load resistance
Supply voltage VDD, the both ends of the biasing resistor connect the control port and bias voltage of amplification module respectively, the shunt capacitance
Both ends connect one end and the supply voltage VDD of biasing resistor respectively, and the both ends of the filter capacitor connect the defeated of amplification module respectively
Exit port and radio frequency output signal, the both ends of the NPN triode current mirror connect respectively amplification module current mirror port and
Ground GND；
Preferably, the variable resistance circuit includes：Two resistances hinder 1 to the low resistance resistance between 5K and two
It is worth the high resistance measurement in more than 5K；
Preferably, the orthogonal signal generator includes：Two-stage quadrature module, and the both ends of first order quadrature module point
Not Lian Jie second level quadrature module input port and radio-frequency input signals, second level quadrature module the other end connection simulation plus
The input port of musical instruments used in a Buddhist or Taoist mass.
The invention has the advantages that：
1) present invention is due to using cascode amplifier, by directly changing grid voltage so that the gain equivalent of circuit
Change, the signal that output amplitude is continuous and phase is flat, avoids current mirror error present in traditional analog adder, carries
High output phase precision.
2) present invention is due to using variable resistance circuit, caused bias voltage being directly acted on brilliant in analog adder
The grid of body pipe, and then the radiofrequency signal of the phase shift such as output port generation from analog adder, are avoided using tradition phase-shifting
The larger D/A converting circuit of transistor size in device, reduces the power consumption of integrated circuit, while ensures phase accuracy.
Brief description of the drawings
Fig. 1 is the analog adder circuit in conventional active phase shifter；
Fig. 2 is the overall structure block diagram of the present invention；
Fig. 3 is three limit orthogonal signal generator circuit diagrams in the present invention；
Fig. 4 is the analog adder circuit diagram in the present invention；
Fig. 5 is the double active balun circuit figures of single-turn in the present invention；
Fig. 6 is the differential configuration buffer circuits figure in the present invention；
Fig. 7 is the simulation curve figure that 16 phase states between 0 to 90 degree are produced with the present invention.
Embodiment
Exemplified by this example becomes six active phase shifters of mutual conductance by the broadband of high dB gains in the range of one 3 to 8GHZ.
Reference picture 2, the active phase shifter of this example include double baluns of single-turn, orthogonal signal generator, analog adder, slow
Device and controller are rushed, single-turn double balun, orthogonal signal generator, analog adder and buffers are sequentially connected, controller and mould
Intend adder connection；After radiofrequency signal enters the double baluns of single-turn, the radiofrequency signal of single ended input is changed into opposite in phase and width
Spend size a pair of differential signals of identical；It is identical to produce four amplitude sizes after orthogonal signal generator for the differential signal
And orthogonal signalling of the phasetophase away from 90 degree, input of the orthogonal signalling as next stage analog adder；In analog adder,
The signal of the phase shifts such as cluster is generated by way of Vector modulation；Finally, the output letter of phase shifter is obtained after buffered device effect
Number.
Reference picture 3, the orthogonal signal generator in this example include two-stage quadrature module；First order quadrature module is used to produce
Two limits in raw frequency band, it includes four electric capacity C1, C2, C3, C4 and four resistance R1, R2, R3, R4, and the second level is orthogonal
Module is used to produce a limit in frequency band, and it includes four electric capacity C5, C6, C7, C8 and four resistance R5, R6, R7, R8,
Its annexation is as follows：
First resistor R1 both ends connect the first electric capacity C1 output end and the second electric capacity C2 input, the second electricity respectively
Resistance R2 both ends connect the second electric capacity C2 output end and the 3rd electric capacity C3 input, 3rd resistor R3 both ends difference respectively
The 3rd electric capacity C3 output end and the 4th electric capacity C4 input are connected, the 4th resistance R4 both ends connect the 4th electric capacity C4 respectively
Output end and the first electric capacity C1 input；First resistor R1 output end and the first electric capacity C1 output end, the 5th resistance
R5 input and the 5th electric capacity C5 input are connected；Second resistance R2 output end and the second electric capacity C2 output end, the
Seven resistance R7 input and the 7th electric capacity C7 input are connected；3rd resistor R3 output end and the 3rd electric capacity C3 output
The input at end, the 6th resistance R6 input and the 6th electric capacity C6 is connected；4th resistance R4 output end and the 4th electric capacity C4
Output end, the 8th resistance R8 input and the 8th electric capacity C8 input be connected；5th electric capacity C5 both ends connect respectively
First electric capacity C1 output end and the second positive output end QOUT+ of second level quadrature module, the 6th electric capacity C6 both ends connect respectively
Connect the 3rd electric capacity C3 output end and the first negative output terminal IOUT- of second level quadrature module, the 7th electric capacity C7 both ends difference
Connect the second electric capacity C2 output end and the second negative output terminal QOUT-, the 8th electric capacity C8 of second level quadrature module both ends point
Lian Jie not the 4th electric capacity C4 output end and the first positive output end IOUT+ of second level quadrature module.
In first order quadrature module, due to producing two limits, so in two paths of first order quadrature module top layer
It is different from the resistance capacitance value of two paths of bottom.First order quadrature module output end voltage V1 and V3 formula is first derived,
Then voltage V1 and V3 formula are made into business, obtaining output function H (s) is：
Wherein, Ra represents first resistor R1 and second resistance R2 resistance size, and Rb represents the electricity of 3rd resistor R3 and the 4th
R4 resistance size is hindered, Ca represents the first electric capacity C1 and the second electric capacity C2 capacitance size, and Cb represents the 3rd electric capacity C3 and the 4th
Electric capacity C4 capacitance size.
R in postulation formulaaCa＜ RbCb, when meeting condition 8RaCa=RbCbWhen, two pole frequencies calculated are respectively
1/2RaCaAnd 1/4RaCa。
In the quadrature module of the second level, pole frequency approximation is near 1/2 π RC, first fixed resistance R value, it is determined as 100 Europe
Nurse, it is then determined that electric capacity C value；Finally, the numerical value of electric capacity or resistance is adjusted near fixed limit, this can be penetrated by finding out
The increased limit direction of frequency signal in orthogonal.
The orthogonal signal generator first order quadrature module has two limits 4GHZ and 7GHZ, and second level quadrature module has one
Individual limit 5GHZ, for the relative error of phase within 0.5 degree, gain S21 decay is smaller, can ignore its decline.
Reference picture 4, the analog adder in this example include active inductance, four groups of nmos pass transistors, four path analoging switch
And variable resistance circuit.Wherein：
First active inductance, for as the load port in analog adder, it to include the first active inductance resistance R9
With single-end triode N1, resistance R9 both ends connect single-end triode N1 base stage and supply voltage VDD respectively；
Four groups of nmos pass transistors, for being amplified to the signal amplitude in analog adder, it includes eight NMOS crystalline substances
Body pipe M1, M2, M3, M4, M5, M6, M7 and M8, the first transistor M1 drain electrode are connected with the 5th transistor M5 source electrode；Should
Second transistor M2 drain electrode is connected with the 6th transistor M6 source electrode；Third transistor M3 drain electrode and the 7th transistor M7
Source electrode be connected；4th transistor M4 drain electrode is connected with the 8th transistor M8 source electrode, this four transistors M1, M2, M3
With M4 source ground；5th transistor M5 and the 6th transistor M6 grid is connected；7th transistor M7 and the 8th is brilliant
Body pipe M8 grid is connected；
Four path analoging switch, for controlling the break-make of signal in analog adder, it include four switch SI, SIN, SQ and
SQN, first switch SI and second switch SIN opposite polarities, first switch SI both ends connect the 5th transistor M5's respectively
Drain electrode and triode N1 emitter stage；Second switch SIN both ends connect the 6th transistor M6 drain electrode and triode respectively
N1 emitter stage；3rd switch SQ and the 4th switch SQN opposite polarities, the 3rd switch SQ both ends connect the 7th crystal respectively
Pipe M7 drain electrode and triode N1 emitter stage；4th switch SQN both ends connect respectively the 8th transistor M8 drain electrode and
Triode N1 emitter stage.
Variable resistance circuit, for controlling the grid voltage of output transistor in analog adder, it includes two resistances
1 to the low resistance resistance between 5K and two resistances more than 5K high resistance measurement；
The low resistance resistance, for as the input resistance in variable resistance circuit, it include two resistance R10 and
R12；
The high resistance measurement, for as the output resistance in variable resistance circuit, it include two resistance R11 and
R13；
First input resistance R10 one end is connected with the second output resistance R11 one end, and the first input resistance R10's is another
One termination supply voltage VDD, the second output resistance R11 other end ground connection GND；
3rd input resistance R12 one end is connected with the 4th output resistance R13 one end, and the 3rd input resistance R12's is another
One termination supply voltage VDD, the 4th output resistance R13 other end ground connection GND.
Single-stage cascode amplifier in analysis mode adder, consider small-signal resistance ro1And ro2, derive the whole of circuit
Body mutual conductance gm and voltage gain | Av | be respectively：
|Av|=gm1ro1[(gm2+gmb2)ro2+1] <3>
Wherein, gm1 represents the mutual conductance of input transistors, and gm2 represents the mutual conductance of bank tube altogether, and gmb2 is represented caused by bulk effect
Mutual conductance, ro1Represent the small-signal resistance of input transistors, ro2Represent the small-signal resistance of bank tube altogether.
By formula<2>And formula<3>As can be seen that the gain of circuit | Av | with the mutual conductance gm1 of input transistors and altogether
The mutual conductance gm2 of bank tube has relation, by controlling the two transistor transconductances gm1 and gm2 big I to change the entirety of circuit
Gain, and then make the changes in amplitude such as single-end output signal, finally synthesize equiphase signal.
The analog adder forms cascode structure using NFET RF tubes, utilizes bias voltage caused by variable resistor
The grid voltage Va and Vb of the common bank tube of control, voltage Va and Vb excursion are between 0.7 to 3.1 volts, Va change spacing
In 0.3V or so, Vb change spacing after removing some nonlinear phase states, is obtained 16 between 0-90 degree in 0.5V or so
The individual preferable phase state curve of the linearity.
Reference picture 5, the double baluns of single-turn in this example include active inductance, PMOS current mirrors, difference block, biased electrical
Resistance, filter capacitor and shunt capacitance；
Second active inductance, for as the load port in the double baluns of single-turn, including two the second active inductive loads
Resistance R14, R15 and two loads triode N2, N3, the first load resistance R14 both ends connect the first load triode respectively
N2 base stage and supply voltage VDD, the second load resistance R15 both ends connect the second load triode N3 base stage and electricity respectively
Source voltage VDD；
PMOS current mirrors, for producing the bias current in the double baluns of single-turn, it include three PMOS mirrored transistors M9,
M10 and M11, these three transistors M9, M10 are connected with M11 grid, and source electrode is connected to supply voltage VDD, and the first mirror image is brilliant
Body pipe M9 grid leak is connected, the second mirrored transistor M10 the second load triode of drain terminal connection N3 emitter stage, the 3rd mirror image
Transistor M11 the first load triode of drain terminal connection N2 emitter stage；
Difference block, for lifting the gain of signal in the double baluns of single-turn, including four difference type triodes N4, N5, N6
And N7, the first difference type triode N4 colelctor electrode connecting triode N2 emitter stage, the first difference type triode N4 base
Pole connecting triode N5 base stage, the first difference type triode N4 emitter stage connecting triode N6 colelctor electrode, the 3rd difference
Type triode N6 base stage connection electric capacity C9 one end, the 3rd difference type triode N6 emitter stage connecting triode N9 current collection
Pole, the second difference type triode N5 colelctor electrode connecting triode N3 emitter stage, the second difference type triode N5 emitter stage
Connecting triode N7 colelctor electrode, the 4th difference type triode N7 base stage connection electric capacity C11 one end, the pole of the 4th difference type three
Pipe N7 emitter stage connecting triode N9 colelctor electrode；
Biasing resistor, for producing the DC offset voltage in the double baluns of single-turn, including three biasing resistors R16, R17 and
R18, the first biasing resistor R16 both ends are respectively connecting to triode N4 base stage and bias voltage Vc, the second biasing resistor R17 two
End is respectively connecting to triode N6 base stage and bias voltage Vbias, the 3rd biasing resistor R18 both ends are respectively connecting to triode
N7 base stage and bias voltage Vbias；
Filter capacitor, for the filtering of output end signal in the double baluns of single-turn, including electric capacity C9, the 9th electric capacity C9 both ends
Rf inputs RF_in and triode N6 base stage is connected respectively；
Shunt capacitance, for stablizing the direct current biasing in the double baluns of single-turn, it includes three electric capacity C10, C11 and C12, the
Bypass capacitor C10 both ends connect bias voltage Vbias and ground GND respectively, and the second shunt capacitance C11 both ends connect respectively
The base stage and ground GND of triode N7 base stage and ground GND, the 3rd shunt capacitance C12 both ends difference connecting triode N5.
Reference picture 6, the buffer in this example include amplification module, load resistance, biasing resistor, shunt capacitance, filtering
Electric capacity and NPN triode current mirror；
Amplification module, for improving the gain of radiofrequency signal in buffer, it include four scale-up version triode N14,
N15, N16 and N17, the first scale-up version triode N14 and the second scale-up version triode N15 emitter stage connect the 3rd amplification respectively
Type triode N16 and the 4th scale-up version triode N17 colelctor electrode, the first scale-up version triode N14 and the pole of the second scale-up version three
Pipe N15 base stage is connected, the first scale-up version triode N14 colelctor electrode connection resistance R19 one end, the second scale-up version triode
N15 colelctor electrode connection resistance R21 one end, the 3rd scale-up version triode N16 and the 4th scale-up version triode N17 emitter stage
The second mirror image triode N20 colelctor electrode is connected, the 3rd scale-up version triode N16 base stage connects input positive terminal mouth Vin+, the
Four scale-up version triode N17 base stage connection input negative terminal mouth Vin-；
Load resistance, for as the load port in buffer, it to include two resistance R19 and R21, resistance R19's
Both ends difference connecting triode N14 colelctor electrode and supply voltage VDD, resistance R21 both ends connect the second scale-up version three respectively
Pole pipe N15 colelctor electrode and supply voltage VDD；
Biasing resistor, for producing the DC offset voltage in buffer, it includes two resistance R20 and R22, resistance
R20 both ends difference connecting triode N15 base stage and supply voltage VDD, resistance R22 both ends connect the second scale-up version respectively
Triode N15 base stage and ground GND；
Shunt capacitance, for the direct current biasing in stabilizing bumper, it includes an electric capacity C14, electric capacity C14 both ends
The second scale-up version triode N15 base stage and supply voltage VDD is connected respectively；
Filter capacitor, for the filtering of output end signal in buffer, it includes an electric capacity C15, and the two of electric capacity C15
End connects the emitter stage and output port RF_OUT penetrated with triode N18 respectively；
NPN triode current mirror, for producing the bias current in buffer, it includes three NPN mirror image triodes
N19, N20 and N21, these three mirror image triode N19, N20 are connected with N21 base stage, and emitter stage is connected to the ground GND, the first NPN
Mirror image triode N19 colelctor electrode connection current mirror input port Ic3, the 2nd NPN mirror image triodes N20 colelctor electrode connection three
Pole pipe N16 emitter stage, the 3rd NPN mirror image triodes N21 colelctor electrode connecting triode N18 emitter stage.
The emulation experiment of the present invention is described further：
First, experiment condition
In this experiment, supply voltage VDD is 3.3V, and ground GND is 0V, image current Ic1, Ic2 of the double baluns of single-turn with
Image current Ic3 in buffer is 1mA, and variable resistance circuit medium or low resistance value resistance R10 and R12 change in resistance scope is in 1K
To between 5K, high resistance measurement R11 and R13 change in resistance scope is between 5K to 8K, caused bias voltage Va and Vb change
For scope between 0.7V to 3.1V, the metal-oxide-semiconductor in cascode amplifier uses NMOS tube, active inductance, amplification module and difference
Triode in sub-module uses NPN type triode, and filter capacitor and shunt capacitance capacitance size are 2PF, biasing resistor
Resistance size 5K.
2nd, emulation experiment
This experiment uses cadence softwares, based on 0.18um BiCMOS techniques, under ADE emulation platforms, builds the shifting
Phase device circuit module, integrated circuit emulation is then carried out, the performance of the phase shifter is reflected eventually through phase curve figure.
First, by the single-turn put up double balun, orthogonal signal generator, analog adder, buffer and controllers point
Do not establish module symbol, then by modular single-turn double balun, orthogonal signal generator, analog adder and buffers according to
Secondary connection, controller are connected with analog adder, are completed artificial circuit and are built.
Secondly, under ADE emulation platforms, simulation parameter is set, wherein, radio frequency signal frequency scope 3 arrives 8GHZ, signal
Amplitude 10mV, center frequency points 5GHZ, the linear stepping of each simulation curve is counted 50, after setting above parameter,
The emulation of circuit, and phase curve caused by the output port test in phase shifter are carried out under ADE platforms, as shown in Figure 7.
Fig. 7 represents 16 linearities preferable phase state curve of the phase shifter output end between 0-90 degree, longitudinal axis table
Show the size of the phase shifter output phase, transverse axis represents the frequency range of the phase shifter, can be obtained by Fig. 7 simulation result：Arrived 3
In 8GHZ frequency ranges, the phase error of the phase shifter meets design requirement within 4.6 degree.
Claims (8)
1. a kind of broadband of high dB gains becomes six active phase shifters of mutual conductance, including：The double balun of single-turn, orthogonal signal generator,
Analog adder, buffer and controller, single-turn double balun, orthogonal signal generator, analog adder and buffers connect successively
Connect, controller is connected with analog adder, it is characterised in that：
The analog adder, using cascode amplifier, by changing grid voltage so that the gain equivalent change of circuit,
The signal that output amplitude is continuous and phase is flat；
The controller, the transistor gate directly acted on using bias voltage caused by variable resistance circuit in analog adder
Pole, from the radiofrequency signal of the phase shifts such as the output port generation of analog adder.
2. active phase shifter according to claim 1, it is characterised in that cascode amplifier includes：First active inductance,
Four groups of nmos pass transistors, four path analoging switch, the both ends of the active inductance connect one end and the power supply of four path analoging switch respectively
Voltage VDD, the other end of four path analoging switch connect the output port of four groups of nmos pass transistors respectively, four groups of nmos pass transistors
The other end is connected to the ground GND.
3. active phase shifter according to claim 1, it is characterised in that the double baluns of single-turn include：Second active inductance, PMOS
Current mirror, difference block, biasing resistor, filter capacitor and shunt capacitance, the both ends of the active inductance connect difference block respectively
Output port and supply voltage VDD, the both ends of the PMOS current mirrors connect the output port and power supply electricity of difference block respectively
VDD is pressed, the both ends of the biasing resistor connect the control port and bias voltage of difference block, the both ends point of the filter capacitor respectively
Not Lian Jie difference block input port and radio-frequency input signals, the both ends of the shunt capacitance connect respectively biasing resistor one end and
Ground GND.
4. active phase shifter according to claim 1, it is characterised in that buffer includes：Amplification module, load resistance, partially
Resistance, shunt capacitance, filter capacitor and NPN triode current mirror are put, the output port connection load resistance of the amplification module
One end, the other end connection supply voltage VDD of load resistance, the both ends of the biasing resistor connect the control terminal of amplification module respectively
Mouth and bias voltage, the both ends of the shunt capacitance connect one end and the supply voltage VDD of biasing resistor respectively, the filter capacitor
Both ends connect the output port and radio frequency output signal of amplification module respectively, and the both ends of the NPN triode current mirror connect respectively
The current mirror port of amplification module and ground GND.
5. active phase shifter according to claim 1, it is characterised in that variable resistance circuit includes：Two resistances arrive 1
The high resistance measurement of low resistance resistance and two resistances between 5K in more than 5K；
The low resistance resistance, for as the input resistance in variable resistance circuit, it to include two resistance R10 and R12；
The high resistance measurement, for as the output resistance in variable resistance circuit, it to include two resistance R11 and R13；
First input resistance R10 one end is connected with the second output resistance R11 one end, the first input resistance R10 other end
Meet supply voltage VDD, the second output resistance R11 other end ground connection GND；
3rd input resistance R12 one end is connected with the 4th output resistance R13 one end, the 3rd input resistance R12 other end
Meet supply voltage VDD, the 4th output resistance R13 other end ground connection GND.
6. active phase shifter according to claim 1, it is characterised in that orthogonal signal generator includes：Two-stage orthogonal mode
Block, and the both ends of first order quadrature module connect the input port and radio-frequency input signals of second level quadrature module respectively, second
The input port of the other end connection analog adder of level quadrature module.
7. active phase shifter according to claim 4, it is characterised in that amplification module include two Differential Input pipe N16,
N17 and two cobasis amplifier tube N14, N15, two Differential Input pipes N16 and N17 base stage connect input positive signal Vin+ respectively
With negative signal Vin-, its emitter stage is connected to the output port of NPN triode current mirror, and colelctor electrode connects cobasis amplification respectively
Pipe N14 and N15 emitter stage；Two cobasis amplifier tube N14 are connected with N15 base stage, and emitter stage connects one end of load resistance.
8. active phase shifter according to claim 6, it is characterised in that first order quadrature module includes the first limit module
With the second limit module, the left end of the first limit module connects input positive signal Vin+ and negative signal Vin-, right-hand member connection respectively
The input port of second level quadrature module, bottom connect the top port of the second limit module, the left end point of the second limit module
Positive signal Vin+ and negative signal Vin- Lian Jie not be inputted, right-hand member connects the input port of second level quadrature module.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711143857.9A CN107707217B (en) | 2017-11-17 | 2017-11-17 | high-dB-gain broadband variable-transconductance six-bit active phase shifter |
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| CN201711143857.9A CN107707217B (en) | 2017-11-17 | 2017-11-17 | high-dB-gain broadband variable-transconductance six-bit active phase shifter |
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| CN107707217A true CN107707217A (en) | 2018-02-16 |
| CN107707217B CN107707217B (en) | 2021-06-08 |
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| CN109546987A (en) * | 2018-11-16 | 2019-03-29 | 西安电子科技大学 | Broadband active phase shifter |
| CN110212887A (en) * | 2019-04-28 | 2019-09-06 | 南京汇君半导体科技有限公司 | A kind of radio frequency active phase shifter structure |
| WO2020135612A1 (en) * | 2018-12-26 | 2020-07-02 | 深圳市中兴微电子技术有限公司 | Vector synthesis phase shifter and vector synthesis phase shifting method |
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| CN111819793B (en) * | 2018-03-08 | 2023-09-12 | 三菱电机株式会社 | Variable inductor circuit |
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| CN109546987B (en) * | 2018-11-16 | 2021-09-03 | 西安电子科技大学 | Broadband active phase shifter |
| CN109546987A (en) * | 2018-11-16 | 2019-03-29 | 西安电子科技大学 | Broadband active phase shifter |
| WO2020135612A1 (en) * | 2018-12-26 | 2020-07-02 | 深圳市中兴微电子技术有限公司 | Vector synthesis phase shifter and vector synthesis phase shifting method |
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