CN107706244A - 一种垂直型氮化镓肖特基二极管的制作工艺 - Google Patents

一种垂直型氮化镓肖特基二极管的制作工艺 Download PDF

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CN107706244A
CN107706244A CN201710838474.7A CN201710838474A CN107706244A CN 107706244 A CN107706244 A CN 107706244A CN 201710838474 A CN201710838474 A CN 201710838474A CN 107706244 A CN107706244 A CN 107706244A
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gallium nitride
layer
type gallium
silicon
vertical
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周炳
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Ningbo Haite Gen Electric Co Ltd
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Ningbo Haite Gen Electric Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes
    • H01L29/8725Schottky diodes of the trench MOS barrier type [TMBS]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609Diodes
    • H01L29/66143Schottky diodes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明涉及一种垂直型氮化镓肖特基二极管的制作工艺,包括从下至上依序设置的硅衬底层、N型氮化镓层和P型氮化镓层,该方法包括以下步骤:在P型氮化镓层上刻蚀上下贯通的氮化镓沟槽;在氮化镓沟槽内以及P型氮化镓上表面上生长肖特基金属层,在硅衬底层上刻蚀上下贯通的硅通孔;在硅通孔内以及硅衬底层下表面上生长金属层。本发明结构设置合理,通过垂直传输,有效提升肖特基势垒高度而达到降低漏电流和增高击穿电压的目的。

Description

一种垂直型氮化镓肖特基二极管的制作工艺
技术领域
本发明涉及二极管制作技术,特别涉及一种垂直型氮化镓肖特基二极管的制作工艺。
背景技术
现有技术中,氮化镓肖特基二极管是在蓝宝石、硅或碳化硅衬底上生长N+氮化镓层和N-氮化镓层,蚀刻N-氮化镓层至N+氮化镓层,在N-氮化镓层上淀积肖特基金属层作为阳极,在N+氮化镓层上淀积欧姆金属层作为阴极,从而构成肖特基二极管。现有氮化镓肖特基二极管的缺点在于:由于氮化镓通过在生长过程中的掺杂来降低N型氮化镓层中的电子浓度有限,因此无法有效提升肖特基势垒高度而达到降低漏电流和增高击穿电压的目的。
发明内容
本发明的目的在于针对现有技术的缺陷和不足,提供一种垂直型氮化镓肖特基二极管的制作工艺,在P型氮化镓层上刻蚀上下贯通的氮化镓沟槽,通过在氮化镓沟槽内以及P型氮化镓上表面上生长肖特基金属,和在硅衬底层上刻蚀上下贯通的硅通孔,通过在硅通孔内以及硅衬底层下表面上生长金属,即通过垂直传输,有效提升肖特基势垒高度而达到降低漏电流和增高击穿电压的目的。
为实现上述目的,本发明采用以下技术方案。
本发明所述的一种垂直型氮化镓肖特基二极管的制作工艺,包括从下至上依序设置的硅衬底层、N型氮化镓层和P型氮化镓层,该方法包括以下步骤:
步骤1:在P型氮化镓层上刻蚀上下贯通的氮化镓沟槽;
步骤2:在氮化镓沟槽内以及P型氮化镓上表面上生长肖特基金属层,在硅衬底层上刻蚀上下贯通的硅通孔;
步骤3:在硅通孔内以及硅衬底层下表面上生长金属层。
本发明有益效果为:本发明所述的垂直型氮化镓肖特基二极管在P型氮化镓层上刻蚀上下贯通的氮化镓沟槽,通过在氮化镓沟槽内以及P型氮化镓上表面上生长肖特基金属层,和在硅衬底层上刻蚀上下贯通的硅通孔,通过在硅通孔内以及硅衬底层下表面上生长金属层,即通过垂直传输,有效提升肖特基势垒高度而达到降低漏电流和增高击穿电压的目的。
附图说明
图1是本发明中垂直型氮化镓肖特基二极管。
图2是步骤一的示意图。
图3是步骤二的示意图。
图4是步骤三的示意图。
图中:1、P型氮化镓层;2、N型氮化镓层;3、硅衬底层;4、氮化镓沟槽;5、肖特基金属层;6、硅通孔;7、金属层。
具体实施方式
下面结合附图对本发明作进一步的说明。
如图1至图4所示,本发明所述的一种垂直型氮化镓肖特基二极管的制作工艺,包括从下至上依序设置的硅衬底层3、N型氮化镓层2和P型氮化镓层1,该方法包括以下步骤:
步骤1:在P型氮化镓1层上刻蚀上下贯通的氮化镓沟槽4;
步骤2:在氮化镓沟槽4内以及P型氮化镓1上表面上生长肖特基金属5,在硅衬底层3上刻蚀上下贯通的硅通孔6;
步骤3:在硅通孔6内以及硅衬底层3下表面上生长金属7。
本发明通过垂直传输,有效提升肖特基势垒高度而达到降低漏电流和增高击穿电压的目的。
以上所述仅是本发明的较佳实施方式,故凡依本发明专利申请范围所述的构造、特征及原理所做的等效变化或修饰,均包括于本发明专利申请范围内。

Claims (1)

1.一种垂直型氮化镓肖特基二极管的制作工艺,其特征在于,包括从下至上依序设置的硅衬底层(3)、N型氮化镓层(2)和P型氮化镓层(1),该方法包括以下步骤:
步骤1:在P型氮化镓(1)层上刻蚀上下贯通的氮化镓沟槽(4);
步骤2:在氮化镓沟槽(4)内以及P型氮化镓(1)上表面上生长肖特基金属层(5),在硅衬底层(3)上刻蚀上下贯通的硅通孔(6);
步骤3:在硅通孔(6)内以及硅衬底层(3)下表面上生长金属层(7)。
CN201710838474.7A 2017-09-18 2017-09-18 一种垂直型氮化镓肖特基二极管的制作工艺 Pending CN107706244A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112992674A (zh) * 2021-02-05 2021-06-18 中国电子科技集团公司第十三研究所 一种垂直结构的氮化镓太赫兹二极管及制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103107204A (zh) * 2011-11-11 2013-05-15 万国半导体股份有限公司 垂直氮化镓肖特基二极管
US20130256680A1 (en) * 2012-03-30 2013-10-03 Richtek Technology Corporation Vertical Semiconductor Device and Manufacturing Method Thereof
CN103346083A (zh) * 2013-07-09 2013-10-09 苏州捷芯威半导体有限公司 氮化镓肖特基二极管及其制造方法
CN103904135A (zh) * 2014-04-18 2014-07-02 苏州捷芯威半导体有限公司 肖特基二极管及其制造方法
JP2016143841A (ja) * 2015-02-04 2016-08-08 国立研究開発法人情報通信研究機構 半導体装置とその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103107204A (zh) * 2011-11-11 2013-05-15 万国半导体股份有限公司 垂直氮化镓肖特基二极管
US20130256680A1 (en) * 2012-03-30 2013-10-03 Richtek Technology Corporation Vertical Semiconductor Device and Manufacturing Method Thereof
CN103346083A (zh) * 2013-07-09 2013-10-09 苏州捷芯威半导体有限公司 氮化镓肖特基二极管及其制造方法
CN103904135A (zh) * 2014-04-18 2014-07-02 苏州捷芯威半导体有限公司 肖特基二极管及其制造方法
JP2016143841A (ja) * 2015-02-04 2016-08-08 国立研究開発法人情報通信研究機構 半導体装置とその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112992674A (zh) * 2021-02-05 2021-06-18 中国电子科技集团公司第十三研究所 一种垂直结构的氮化镓太赫兹二极管及制备方法
CN112992674B (zh) * 2021-02-05 2022-08-09 中国电子科技集团公司第十三研究所 一种垂直结构的氮化镓太赫兹二极管及制备方法

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