CN107706196A - A kind of array base palte and preparation method thereof, display device - Google Patents
A kind of array base palte and preparation method thereof, display device Download PDFInfo
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- CN107706196A CN107706196A CN201710897693.2A CN201710897693A CN107706196A CN 107706196 A CN107706196 A CN 107706196A CN 201710897693 A CN201710897693 A CN 201710897693A CN 107706196 A CN107706196 A CN 107706196A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 85
- 230000004888 barrier function Effects 0.000 claims abstract description 28
- 229920002120 photoresistant polymer Polymers 0.000 claims description 33
- 239000010408 film Substances 0.000 claims description 32
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 14
- 239000010409 thin film Substances 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 6
- 230000000717 retained effect Effects 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 43
- 230000007797 corrosion Effects 0.000 description 9
- 238000005260 corrosion Methods 0.000 description 9
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 238000000059 patterning Methods 0.000 description 3
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052779 Neodymium Inorganic materials 0.000 description 1
- VVTQWTOTJWCYQT-UHFFFAOYSA-N alumane;neodymium Chemical compound [AlH3].[Nd] VVTQWTOTJWCYQT-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The present invention provides a kind of array base palte and preparation method thereof, display device, is related to display technology field, can improve and show the problem of bad caused by signal wire is corroded.The array base palte includes substrate; also include setting gradually signal wire, conductive protection pattern, at least one layer of insulating barrier and transparent conductive patterns over the substrate; the conductive protection pattern is arranged on the surface of the signal wire; via is provided with least one layer of insulating barrier, the transparent conductive patterns pass through the via and the signal linear contact lay；The orthographic projection of the via over the substrate is fallen into the orthographic projection of the conductive protection pattern over the substrate, and the orthographic projection of the conductive protection pattern over the substrate is fallen into the orthographic projection of the signal wire over the substrate.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of array base palte and preparation method thereof, display device.
Background technology
Existing display device includes array base palte, and array base palte includes the signal wire being arranged on substrate, IC
(integrated circuit, integrated circuit) is connected in binding area with signal wire, and corresponding signal is exported to signal wire.Due to
Signal wire and IC different layers, when signal wire is connected with IC, the different transparent conductive patterns of generally use by via respectively with letter
The mode of number line connection, to complete the switching of signal wire.
As shown in Fig. 1 (a), signal wire 20 is generally by setting gradually Nd (neodymium) alloy film layers and Mo (molybdenum) over the substrate 10
Film layer is prepared to be formed, and when forming via by dry etch process, process gas is ionized, and caused plasma can be to metal
There is material stronger bombardment to act on, and is destroyed metal Mo metal lattice state, causes to form hole on Mo metal levels 21.
Because transparent conductive patterns 30 are relatively thin and structure is not fine and close, and the corrosion rate of Nd alloy-layers 22 is very fast, causes environment
By the hole on Mo metal levels 21, the corrosion of large area is easily caused to Nd alloy-layers 22 for middle steam.As shown in Fig. 1 (b), one
Aspect, after the corrosion of the large area of Nd alloy-layers 22, Mo metal levels 21 can easily cause at the place that is corroded of Nd alloy-layers 22 to lower recess
Mo metal levels 21 are broken；On the other hand, Nd alloy-layers 22 can have an impact to Mo metal levels 21 in corrosion process, cause Mo
A certain degree of corrosion also occurs in metal level 21, ultimately results in signal wire 20 and is broken, bad so as to produce display.
The content of the invention
Embodiments of the invention provide a kind of array base palte and preparation method thereof, display device, can improve because of signal wire quilt
The problem of bad is shown caused by corrosion.
To reach above-mentioned purpose, embodiments of the invention adopt the following technical scheme that：
First aspect, there is provided a kind of array base palte, including substrate, in addition to set gradually signal over the substrate
Line, conductive protection pattern, at least one layer of insulating barrier and transparent conductive patterns, the conductive protection pattern are arranged on the signal wire
Surface, be provided with via at least one layer of insulating barrier, the transparent conductive patterns pass through the via and the signal
Linear contact lay；The orthographic projection of the via over the substrate falls into the orthographic projection of the conductive protection pattern over the substrate
Interior, the orthographic projection of the conductive protection pattern over the substrate is fallen into the orthographic projection of the signal wire over the substrate.
Preferably, the signal wire includes grid line and public electrode wire；The conductive protection pattern is described including being arranged on
The first conductive protection pattern on grid line surface and the second conductive protection pattern for being arranged on the public electrode wire surface.
Preferably, the orthographic projection over the substrate of channel region in the thin film transistor (TFT) that the array base palte includes and institute
The orthographic projection of conductive protection pattern over the substrate is stated not overlap.
Preferably, the thickness of the conductive protection pattern is
Preferably, the material of the conductive protection pattern is identical with the material of the transparent conductive patterns.
Preferably, the signal wire includes setting gradually Nb alloy-layers and Mo metal levels over the substrate.
Second aspect, there is provided a kind of preparation method of array base palte, including：Signal wire and conductive protection are formed on substrate
Pattern, the orthographic projection of the conductive protection pattern over the substrate fall into the orthographic projection of the signal wire over the substrate
It is interior；At least one layer of insulating barrier is formed on the substrate formed with the conductive protection pattern；Shape at least one layer of insulating barrier
Into there is via, the orthographic projection of the via over the substrate falls into the orthographic projection of the conductive protection pattern over the substrate
It is interior；Transparent conductive patterns are formed on the substrate formed with least one layer of insulating barrier, the transparent conductive patterns pass through institute
State via and the signal linear contact lay.
Preferably, methods described also includes：Semiconductor layer is formed on substrate, the semiconductor layer includes channel region；Institute
The orthographic projection of the orthographic projection of channel region over the substrate with the conductive protection pattern over the substrate is stated not overlap.
Optionally, the step of forming the signal wire and the conductive protection pattern, including：Gold is sequentially formed on substrate
Belong to film and conductive film, and form the photoresist for covering the conductive film；Photoresist is exposed using semi-transparent mask plate
Light, development, form that area is fully retained in photoresist, the reserved area of photoresist half, photoresist remove area completely；To complete corresponding to photoresist
The full conductive film for removing area and the metallic film perform etching, and form the signal wire；To the reserved area of photoresist half
Photoresist be ashed；To being performed etching corresponding to the conductive film of the reserved area of photoresist half, the conductive guarantor is formed
Protect pattern；Peel off and correspond to the photoresist that area is fully retained in photoresist；
Optionally, the step of forming the signal wire and the conductive protection pattern, including：Metal foil is formed on substrate
Film, and pattern and form the signal wire；Conductive film is formed on the substrate formed with the signal wire, and patterns and to be formed
The conductive protection pattern.
The third aspect, there is provided a kind of display device, including the array base palte described in first aspect.
The embodiment of the present invention provides a kind of array base palte and preparation method thereof, display device, by the surface of signal wire
One layer of conductive protection pattern is formed, so, etching, which is formed, on the insulating layer is used to make transparent conductive patterns connect with signal wire
During tactile via, conductive protection pattern can multi signal line play a protective role, etching technics gas will not be to the letter below via
Number line has an impact.The metal lattice state of signal wire will not be destroyed, and can so avoid in steam entering signal line, from
And the resistance to corrosion of signal wire can be improved, avoid showing bad.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 (a) is a kind of structural representation one for array base palte that prior art provides；
Fig. 1 (b) is a kind of structural representation two for array base palte that prior art provides；
Fig. 2 is a kind of structural representation one of array base palte provided in an embodiment of the present invention；
Fig. 3 is a kind of structural representation two of array base palte provided in an embodiment of the present invention；
Fig. 4 is a kind of structural representation three of array base palte provided in an embodiment of the present invention；
Fig. 5 is a kind of structural representation four of array base palte provided in an embodiment of the present invention；
Fig. 6 is a kind of flow chart of the preparation method of array base palte provided in an embodiment of the present invention；
Fig. 7 (a)-Fig. 7 (f) is a kind of preparation process schematic diagram for array base palte that inventive embodiments provide；
Fig. 8 is a kind of structural representation five of array base palte provided in an embodiment of the present invention.
Reference
10- substrates；20- signal wires；21-Mo metal levels；22-Nd alloy-layers；23- grid lines；24- data wires；30- is transparent to be led
Electrical pattern；The transparent conductive patterns of 31- first；The transparent conductive patterns of 32- second；40- conductive protection patterns；41- first is conductive to be protected
Protect pattern；42- the second conductive protection patterns；The insulating barriers of 51- first；The insulating barriers of 52- second.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
The embodiment of the present invention provides a kind of array base palte, as shown in Fig. 2 including substrate 10, setting gradually over the substrate 10
Signal wire 20, conductive protection pattern 40, at least one layer of insulating barrier (illustrated in Fig. 2 exemplified by comprising the first insulating barrier 51,
Illustrated in Fig. 3 exemplified by comprising the first insulating barrier 51 and the second insulating barrier 52) and transparent conductive patterns 30, conductive protection figure
Case 40 is arranged on the surface of signal wire 20, is provided with via at least one layer of insulating barrier, transparent conductive patterns 30 by via with
Signal wire 20 contacts；The orthographic projection of via over the substrate 10 is fallen into the orthographic projection of conductive protection pattern 40 over the substrate 10, is led
The orthographic projection of electric protection pattern 40 over the substrate 10 is fallen into the orthographic projection of signal wire 20 over the substrate 10.
It should be noted that first, signal wire 20 is not defined, such as can be grid line, data wire, public electrode
Any one in line.
Second, when being performed etching to insulating barrier, process gas is to signal when conductive protection pattern 40 is used to prevent to etch
Line 20 damages, therefore it will be understood by those skilled in the art that conductive protection pattern 40 preferably not with etching when process gas
React, the speed either to be reacted with process gas during etching is slower or conductive protection pattern 40 is sufficiently thick.
Wherein, can be identical with the material of signal wire 20 for the material of conductive protection pattern 40, can also be different.
3rd, the orthographic projection of conductive protection pattern 40 over the substrate 10 falls into the orthographic projection of signal wire 20 over the substrate 10
It is interior, therefore, for the shape of conductive protection pattern 40, pattern registration that can as shown in Figure 3 with signal wire 20；Can also be such as figure
Fallen into shown in 2 in the pattern of signal wire 20.
4th, transparent conductive patterns 30 herein can be for tandem signal line 20 and IC or work as signal wire
20 with other wires are overlapping need wire jumper when, the signal converting of the gap of signal wire 20 is completed using transparent conductive patterns 30.
5th, as shown in Fig. 2 being provided with via during only the first insulating barrier 51, on the first insulating barrier 51 makes electrically conducting transparent
Pattern 30 contacts with signal wire 20；As shown in figure 3, when there is multilayer dielectric layer, what is set on every layer insulating crosses hole site pair
Should, composition one can make the big via that transparent conductive patterns 30 contact with signal wire 20.
The orthographic projection of via over the substrate 10 is fallen into the orthographic projection of conductive protection pattern 40 over the substrate 10, therefore, right
, can be with being used for the via for making transparent conductive patterns 30 be contacted with signal wire 20 on insulating barrier in the shape of conductive protection pattern 40
Pattern registration；Can also be used to making the pattern of via that transparent conductive patterns 30 contact with signal wire 20 to fall on insulating barrier
In the pattern of conductive protection pattern 40.
The embodiment of the present invention provides a kind of array base palte, and one layer of conductive protection pattern 40 is formed on the surface of signal wire 20,
So, etching is formed when being used to make via that transparent conductive patterns 30 contacts with signal wire 20 on the insulating layer, conductive guarantor
The shield meeting multi signal of pattern 40 line 20 plays a protective role, and etching technics gas will not produce shadow to the signal wire 20 below via
Ring.The metal lattice state of signal wire 20 will not be destroyed, and can so avoid in steam entering signal line 20, so as to carry
The resistance to corrosion of high RST line 20, avoid showing bad.
Preferably, signal wire 20 includes grid line and public electrode wire；Conductive protection pattern 40 includes being arranged on grid line surface
The first conductive protection pattern and be arranged on the second conductive protection pattern on public electrode wire surface.
Certainly, transparent conductive patterns 30 include the first transparent conductive patterns for being contacted with grid line and with public electrode linear contact lay
The second transparent conductive patterns.
It is further preferred that grid line and public electrode wire are set with layer, the first conductive protection pattern and the second conductive protection
Pattern is set with layer.
Optionally, as shown in figure 4, signal wire 20 includes grid line 23 and data wire 24, between grid line 23 and data wire 24 also
It is provided with interlayer insulating film；Conductive protection pattern includes the first conductive protection pattern 41 for being arranged on the surface of grid line 23 and is arranged on
The second conductive protection pattern 42 on the surface of data wire 24；Transparent conductive patterns 30 include the first electrically conducting transparent contacted with grid line 23
Pattern 31 and the second transparent conductive patterns 32 contacted with data wire 24.
In order to avoid conductive protection pattern 40 has an impact to the electron mobility of thin-film transistor channel region, so as to influence
The performance of thin film transistor (TFT), as shown in figure 5, the embodiment of the present invention is preferable, the ditch in the thin film transistor (TFT) that array base palte includes
Orthographic projection of the orthographic projection of road area over the substrate 10 with conductive protection pattern 40 over the substrate 10 does not overlap.
That is, conductive protection pattern 40 also further needs the not ditch with thin film transistor (TFT) on the premise of above-mentioned condition is met
Road area has overlapping.That is, there is no conductive protection pattern 40 in channel region opening position.
Channel region in the semiconductor layer of channel region in thin film transistor (TFT), as thin film transistor (TFT), channel region is in film
Raceway groove is formed after transistor turns.
In order on the premise of playing a protective role, reduce the thickness of array base palte as far as possible, the embodiment of the present invention is preferable,
The thickness of conductive protection pattern 40 is
For example, the thickness of conductive protection pattern 40 can be
Preferably, the material of conductive protection pattern 40 is identical with the material of transparent conductive patterns 30.
For example, the material of conductive protection pattern 40 and transparent conductive patterns 30 can be ITO (Indium tin oxide,
Tin indium oxide).
The embodiment of the present invention provides is arranged to phase by the material of conductive protection pattern 40 and the material of transparent conductive patterns 30
Together, the contact interface of via would not be increased, will not also increase the transition resistor of via, will not be to signal loading (Loading)
Have an impact.
In order to reduce the resistance of signal wire 20, the embodiment of the present invention is preferable, and signal wire 20 includes being successively set on substrate
Nb alloy-layers and Mo metal levels on 10.
Wherein, Nb alloy-layers for example can be AlNb (aluminium neodymium) alloy.
The embodiment of the present invention also provides a kind of preparation method of array base palte, as shown in fig. 6, methods described includes：
S10, form signal wire 20 and conductive protection pattern 40 over the substrate 10, conductive protection pattern 40 is over the substrate 10
Orthographic projection is fallen into the orthographic projection of signal wire 20 over the substrate 10.
S20, at least one layer of insulating barrier is formed on the substrate formed with conductive protection pattern 40；On at least one layer of insulating barrier
Formed with via, the orthographic projection of via over the substrate 10 is fallen into the orthographic projection of conductive protection pattern 40 over the substrate 10.
S30, transparent conductive patterns 30 are formed on the substrate formed with least one layer of insulating barrier, transparent conductive patterns 30 are logical
Via contacts with signal wire 20.
The embodiment of the present invention provides a kind of array base palte, and one layer of conductive protection pattern 40 is formed on the surface of signal wire 20,
So, etching is formed when being used to make via that transparent conductive patterns 30 contacts with signal wire 20 on the insulating layer, conductive guarantor
The shield meeting multi signal of pattern 40 line 20 plays a protective role, and etching technics gas will not produce shadow to the signal wire 20 below via
Ring.The metal lattice state of signal wire 20 will not be destroyed, and can so avoid in steam entering signal line 20, so as to carry
The resistance to corrosion of high RST line 20, avoid showing bad.
It is further preferred that methods described also includes forming semiconductor layer on substrate, the semiconductor layer includes raceway groove
Area；Orthographic projection of the orthographic projection of channel region over the substrate 10 with conductive protection pattern 40 over the substrate 10 does not overlap.
By making conductive protection pattern 40 not overlapped with channel region, conductive protection pattern 40 can be avoided to thin film transistor (TFT)
The electron mobility of channel region has an impact, so as to influence the performance of thin film transistor (TFT).
Optionally, step S10 is specifically included：
Shown in S11, such as Fig. 7 (a), metallic film and conductive film are sequentially formed over the substrate 10, and it is conductive to form covering
The photoresist of film.
Wherein, when signal wire 20 includes more metal layers, metal film layer herein should be multilayer.
Shown in S12, such as Fig. 7 (b), photoresist is exposed using semi-transparent mask plate, developed, formed photoresist and protect completely
Area, the reserved area of photoresist half, photoresist is stayed to remove area completely.
Shown in S13, such as Fig. 7 (c), to removing the conductive film in area completely corresponding to photoresist and metallic film is carved
Erosion, form signal wire 20.
Shown in S14, such as Fig. 7 (d), the photoresist of the reserved area of photoresist half is ashed.
Shown in S15, such as Fig. 7 (e), to being performed etching corresponding to the conductive film of the reserved area of photoresist half, conductive protect is formed
Protect pattern 40.
Shown in S16, such as Fig. 7 (f), peel off and correspond to the photoresist that area is fully retained in photoresist.
That is, signal wire 20 and conductive protection pattern 40 with a patterning processes by forming.
Optionally, step S10 is specifically included：
Metallic film is formed over the substrate 10, and is patterned and formed the signal wire 20.
Conductive film is formed on the substrate formed with signal wire 20, and patterns and forms conductive protection pattern 40.
That is, a patterning processes are first passed through and form signal wire 20, then conductive protection pattern is formed by a patterning processes
40。
As shown in figure 8, methods described also includes forming at least one layer on the substrate formed with conductive protection pattern 40
Insulating barrier and transparency conducting layer 30 and other film layers.
The embodiment of the present invention also provides a kind of display device, including above-mentioned array base palte.
Wherein, the display device can be display panel or the display device comprising display panel.
The display device can be liquid crystal display, organic electroluminescent LED display, LCD TV, digital phase
Any product or part with display function such as frame, mobile phone or tablet personal computer.
The beneficial effect of display device provided in an embodiment of the present invention is identical with the beneficial effect of above-mentioned array base palte, herein
Repeat no more.
When display device is liquid crystal display (Liquid Crystal Display, LCD), it include array base palte,
To box substrate and the liquid crystal layer being disposed there between.Wherein, array base palte includes thin film transistor (TFT), with thin film transistor (TFT)
The pixel electrode of first drain electrode electrical connection；Public electrode can also further be included.Black matrix can be included to box substrate
With color film.Herein, color film can be arranged on on box substrate, may also be arranged on array base palte；Public electrode can be arranged on
On array base palte, it may also be arranged on on box substrate.
When display device is organic electroluminescent LED (Organic Light Emitting Diode, abbreviation OLED)
During display, it includes array base palte and package substrate.Wherein, array base palte includes thin film transistor (TFT), with thin film transistor (TFT)
Anode, negative electrode and the organic material functional layer between anode and negative electrode of first drain electrode electrical connection.
The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, change or replacement can be readily occurred in, should all be contained
Cover within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (10)
1. a kind of array base palte, including substrate, it is characterised in that also include setting gradually signal wire over the substrate, lead
Electric protection pattern, at least one layer of insulating barrier and transparent conductive patterns, the conductive protection pattern are arranged on the table of the signal wire
Face, via is provided with least one layer of insulating barrier, the transparent conductive patterns are connect by the via and the signal wire
Touch；
The orthographic projection of the via over the substrate is fallen into the orthographic projection of the conductive protection pattern over the substrate, institute
The orthographic projection of conductive protection pattern over the substrate is stated to fall into the orthographic projection of the signal wire over the substrate.
2. array base palte according to claim 1, it is characterised in that the signal wire includes grid line and public electrode wire；
The conductive protection pattern includes being arranged on the first conductive protection pattern on the grid line surface and is arranged on described public
The second conductive protection pattern on electrode wires surface.
3. array base palte according to claim 1, it is characterised in that in the thin film transistor (TFT) that the array base palte includes
Orthographic projection of the orthographic projection of channel region over the substrate with the conductive protection pattern over the substrate does not overlap.
4. array base palte according to claim 1, it is characterised in that the thickness of the conductive protection pattern is
5. array base palte according to claim 1, it is characterised in that the material of the conductive protection pattern with it is described transparent
The material of conductive pattern is identical.
6. array base palte according to claim 1, it is characterised in that the signal wire includes being successively set on the substrate
On Nb alloy-layers and Mo metal levels.
A kind of 7. preparation method of array base palte, it is characterised in that including：
Signal wire is formed on substrate and conductive protection pattern, the orthographic projection of the conductive protection pattern over the substrate are fallen into
In the orthographic projection of the signal wire over the substrate；
At least one layer of insulating barrier is formed on the substrate formed with the conductive protection pattern；Shape at least one layer of insulating barrier
Into there is via, the orthographic projection of the via over the substrate falls into the orthographic projection of the conductive protection pattern over the substrate
It is interior；
Transparent conductive patterns are formed on the substrate formed with least one layer of insulating barrier, the transparent conductive patterns pass through institute
State via and the signal linear contact lay.
8. preparation method according to claim 6, it is characterised in that methods described also includes：Formed on substrate and partly led
Body layer, the semiconductor layer include channel region；
Orthographic projection of the orthographic projection of the channel region over the substrate with the conductive protection pattern over the substrate is not handed over
It is folded.
9. the preparation method according to claim 7 or 8, it is characterised in that form the signal wire and the conductive protection
The step of pattern, including：
Metallic film and conductive film are sequentially formed on substrate, and forms the photoresist for covering the conductive film；
Photoresist is exposed using semi-transparent mask plate, developed, formed photoresist be fully retained area, the reserved area of photoresist half,
Photoresist removes area completely；
The conductive film and the metallic film for removing area completely corresponding to photoresist are performed etching, form the signal
Line；
The photoresist of the reserved area of photoresist half is ashed；
To being performed etching corresponding to the conductive film of the reserved area of photoresist half, the conductive protection pattern is formed；
Peel off and correspond to the photoresist that area is fully retained in photoresist；
Or
Metallic film is formed on substrate, and patterns and forms the signal wire；
Conductive film is formed on the substrate formed with the signal wire, and patterns and forms the conductive protection pattern.
10. a kind of display device, it is characterised in that including the array base palte described in claim any one of 1-6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710897693.2A CN107706196B (en) | 2017-09-28 | 2017-09-28 | Array substrate, preparation method thereof and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710897693.2A CN107706196B (en) | 2017-09-28 | 2017-09-28 | Array substrate, preparation method thereof and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107706196A true CN107706196A (en) | 2018-02-16 |
| CN107706196B CN107706196B (en) | 2021-05-25 |
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| CN110928085A (en) * | 2019-11-26 | 2020-03-27 | Tcl华星光电技术有限公司 | Array substrate and display panel |
| CN113096849A (en) * | 2021-06-10 | 2021-07-09 | 苏州华星光电技术有限公司 | Conductive silver paste composite material, display device and preparation method thereof |
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