CN107704701A - A kind of analysis method and system for being directed to different pull-up resistors in low speed signal - Google Patents
A kind of analysis method and system for being directed to different pull-up resistors in low speed signal Download PDFInfo
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- CN107704701A CN107704701A CN201710979302.1A CN201710979302A CN107704701A CN 107704701 A CN107704701 A CN 107704701A CN 201710979302 A CN201710979302 A CN 201710979302A CN 107704701 A CN107704701 A CN 107704701A
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- resistors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
Abstract
The present invention provides a kind of analysis method and system for being directed to different pull-up resistors in low speed signal, and methods described includes：Connect different pull-up resistors respectively on I2C signal wires；Obtain I2C link topology；Set simulation parameter；Generate the simulation waveform under different pull-up resistors；According to the overshoot of simulation waveform and rise time selection pull-up resistor.The embodiment of the present invention is by being connected into different pull-up resistors, obtain I2C link topologies, generate the simulation waveform under different pull-up resistors, suitable pull-up resistor is selected according to the overshoot of simulation waveform and rise time, avoid the resistance value from mistake, cause the loss of signal energy, realize and improve circuit design correctness, ensure the reliability of the intercommunication of each device by being communicated under I2C agreements, and then ensure the safety of server operation, greatly enhance the signal integrity and reliability of RACK whole machine cabinet servers.
Description
Technical field
The present invention relates to serial communication bus field, particularly a kind of analysis for being directed to different pull-up resistors in low speed signal
Method and system.
Background technology
I2C (Inter-Integrated Circuit) bus is that the twin wire developed by PHILIPS companies is serially total
Line, for connecting microcontroller and its ancillary equipment.It is a kind of widely used bus standard in microelectronics Control on Communication field.
The bus standard is a kind of special shape of synchronous communication, with interface line is few, control mode is simple, device encapsulation
The advantages that form is small, traffic rate is higher.I2C buses support any IC production processes, by serial data (SDA) line and serially
Clock (SCL) line transmission information between the device of bus is connected to.In circuit design, it is necessary to which this two signal line is connect respectively
Pull-up resistor, to by the voltage high of this signal wire to high potential, and will high electricity using the pull down resistor in I2C interface component
Position is pulled down to low potential.Because each device has a unique Address Recognition, (either microcontroller --- MCU, LCD drive
Dynamic device, memory or keyboard interface), therefore can serve as a transmitter or receiver (being determined by the function of device).
Existing I2C design be substantially according to pull-up resistor be 1.5K Ω, 2.2K Ω and tri- kinds of 4.7K Ω set into
Capable, different pull-up resistors can produce different signal waveforms, but in the design process, due to lacking in low speed signal
The analysis and research of different pull-up resistors, therefore the size of pull-up resistor is selected according to personal experience, and easily lead
Cause to cause design defect easily using the pull-up resistance values of mistake in circuit design.
The content of the invention
It is an object of the invention to provide a kind of analysis method and system for being directed to different pull-up resistors in low speed signal, it is intended to
Solve in current line design, the problem of selection of I2C pull-up resistors rely on personal experience, avoid from wrong resistance value,
The loss of signal energy is caused, realizes and improves circuit design correctness.
To reach above-mentioned technical purpose, the invention provides a kind of analysis side for being directed to different pull-up resistors in low speed signal
Method, comprise the following steps：
S1, connect different pull-up resistors respectively on I2C signal wires；
S2, the link topology for obtaining I2C；
S3, setting simulation parameter；
Simulation waveform under S4, the different pull-up resistors of generation；
S5, pull-up resistor selected according to the overshoot of simulation waveform and rise time.
Preferably, the link topology includes SDA link topologies and SCL link topologies.
Preferably, the simulation parameter includes acquiescence cut-off frequency and measurement period, and the acquiescence cut-off frequency is set as
10GHz, the measurement period are 5-8s。
Preferably, the setting simulation parameter also includes setting different message transmission rates.
Preferably, the overshoot and the selection standard of rise time are that overshoot is minimum and the rise time is most short.
Present invention also offers a kind of analysis system for being directed to different pull-up resistors in low speed signal, including：
Pull-up resistor AM access module, for connecting different pull-up resistors respectively on I2C signal wires；
Link topology acquisition module, for obtaining I2C link topology；
Simulation parameter setting module, for setting simulation parameter；
Simulation waveform generation module, for generating the simulation waveform under different pull-up resistors；
Pull-up resistor selecting module, for the overshoot according to simulation waveform and rise time selection pull-up resistor.
Preferably, the link topology includes SDA link topologies and SCL link topologies.
Preferably, the simulation parameter includes acquiescence cut-off frequency and measurement period, and the acquiescence cut-off frequency is set as
10GHz, the measurement period are 5-8s。
Preferably, the setting simulation parameter also includes setting different message transmission rates.
Preferably, the overshoot and the selection standard of rise time are that overshoot is minimum and the rise time is most short.
The effect provided in the content of the invention is only the effect of embodiment, rather than whole effects that invention is all, above-mentioned
A technical scheme in technical scheme has the following advantages that or beneficial effect：
Compared with prior art, the present invention obtains I2C link topologies, generation by being connected into different pull-up resistors
Simulation waveform under different pull-up resistors, suitable pull-up resistor is selected according to the overshoot of simulation waveform and rise time,
The resistance value from mistake is avoided, causes the loss of signal energy, realizes and improves circuit design correctness, ensure to assist by I2C
The reliability of the intercommunication of each device of the lower communication of view, and then ensure the safety of server operation, greatly enhance RACK
The signal integrity and reliability of whole machine cabinet server.
Brief description of the drawings
Fig. 1 is a kind of analysis method stream for being directed to different pull-up resistors in low speed signal provided in the embodiment of the present invention
Cheng Tu；
Fig. 2 is a kind of common I2C signal line structure schematic diagrames provided in the embodiment of the present invention；
Fig. 3 is that a kind of analysis system for different pull-up resistors in low speed signal provided in the embodiment of the present invention is whole
Body block diagram.
Embodiment
In order to the technical characterstic of clear explanation this programme, below by embodiment, and its accompanying drawing is combined, to this
Invention is described in detail.Following disclosure provides many different embodiments or example is used for realizing the different knots of the present invention
Structure.In order to simplify disclosure of the invention, hereinafter the part and setting of specific examples are described.In addition, the present invention can be with
Repeat reference numerals and/or letter in different examples.This repetition is that for purposes of simplicity and clarity, itself is not indicated
Relation between various embodiments are discussed and/or set.It should be noted that part illustrated in the accompanying drawings is not necessarily to scale
Draw.Present invention omits the description to known assemblies and treatment technology and process to avoid being unnecessarily limiting the present invention.
A kind of point for being directed to different pull-up resistors in low speed signal provided below in conjunction with the accompanying drawings the embodiment of the present invention
Analysis method and system is described in detail.
As shown in figure 1, the embodiment of the invention discloses it is a kind of be directed to low speed signal in different pull-up resistors analysis method,
Comprise the following steps：
S1, connect different pull-up resistors respectively on I2C signal wires；
S2, the link topology for obtaining I2C；
Simulation waveform under S3, the different pull-up resistors of generation；
S4, pull-up resistor selected according to the overshoot of simulation waveform and rise time.
Fig. 2 is one group of common I2C line, and the I2C lines bus reaches BMC chip (U2) by EMC chips (U1).System
Clock produces 33MHz clocks by clock driver, and the transfer rate of SDA and SCL signal be 100K, for the individual device in I2C buses
Part provides synchronizing clock signals.
In the I2C cabling modes, during actual PCB trace, for the ease of comparing sequence problem, I2C signals of the invention
All it is from U1, reaches L6 layers by VIA holes after outer layer walks one section of microstrip line, in internal layer cabling, then pass through VIA holes again
Top layer is reached, finally reaches chip U2.Such a cabling mode is difference cabling, either SDA signal or SCL signal, is all needed
To have certain space length apart from other signal wires, and be also required between SDA and SCL signal line certain space away from
From.
In difference cabling, the requirement of distance is needed between the VIA vias at the VIA vias and SCL of SDA signal line,
And the distance of VIA vias during differential pair and other HW High Ways needs bigger space length, in addition, walking I2C difference
During signal, it is impossible to through Sensitive Apparatuses such as inductance, crystal oscillators.
Different pull-up resistors are connected on I2C signal wires respectively.
The link of SDA and SCL two kinds of signals of cabling mode and SDA, SCL is carried by SigXplorer softwares
Take, the topological structure under different pull-up resistors can be obtained.
Parameter is configured in SigXplorer softwares, cut-off frequency is given tacit consent to and is set as 10GHz, measurement period
It is set as 5-8s.By being configured to parameter, the simulation waveform of the signal wire obtained.
Under 100K data rates, three kinds of pull-up resistor 1.5K Ω, 2.2K Ω and 4.7K Ω waveform are basically identical, and it is super
Tune amount and rise time are essentially identical；
Under 200K data rates, in three kinds of pull-up resistor 1.5K Ω, 2.2K Ω and 4.7K Ω waveform, 2.2K Ω's is upper
Pull-up resistor waveform overshoot is minimum and the rise time is most short；
Under 3.4M data rates, in three kinds of pull-up resistor 1.5K Ω, 2.2K Ω and 4.7K Ω waveform, 4.7K Ω's is upper
Pull-up resistor waveform overshoot is minimum and the rise time is most short.
Above-mentioned three kinds of pull-up resistors have different performances under different pieces of information speed to the influence of signal, are tied according to analysis
Fruit, designer can be made to select different pull-up resistors according to different demands.
The embodiment of the present invention obtains I2C link topologies, generates different pull-up electricity by being connected into different pull-up resistors
Simulation waveform under resistance, suitable pull-up resistor is selected according to the overshoot of simulation waveform and rise time, is avoided from mistake
Resistance value, the loss of signal energy is caused, realize and improve circuit design correctness, ensure to pass through what is communicated under I2C agreements by mistake
The reliability of the intercommunication of each device, and then ensure the safety of server operation, greatly enhance RACK whole machine cabinet services
The signal integrity and reliability of device.
As shown in figure 3, the embodiment of the invention also discloses a kind of analysis system for being directed to different pull-up resistors in low speed signal
System, including pull-up resistor AM access module, link topology acquisition module, simulation parameter setting module, simulation waveform generation mould
Block and pull-up resistor selecting module.
Pull-up resistor AM access module, for connecting different pull-up resistors respectively on I2C signal wires.
Link topology acquisition module, for obtaining I2C link topology, the link topology includes
SDA link topologies and SCL link topologies.
Simulation parameter setting module, for setting simulation parameter, the simulation parameter includes acquiescence cut-off frequency and measurement
Cycle, the acquiescence cut-off frequency are set as 10GHz, and the measurement period is 5-8s。
Simulation waveform generation module, for generating the simulation waveform under different pull-up resistors.
Pull-up resistor selecting module, it is described for the overshoot according to simulation waveform and rise time selection pull-up resistor
Overshoot and the selection standard of rise time are that overshoot is minimum and the rise time is most short.
The setting simulation parameter also includes setting different message transmission rates, sets respectively in embodiments of the present invention
100K, 200K and 3.4M data rate, check simulation waveform at different rates.
Under 100K data rates, three kinds of pull-up resistor 1.5K Ω, 2.2K Ω and 4.7K Ω waveform are basically identical, and it is super
Tune amount and rise time are essentially identical；
Under 200K data rates, in three kinds of pull-up resistor 1.5K Ω, 2.2K Ω and 4.7K Ω waveform, 2.2K Ω's is upper
Pull-up resistor waveform overshoot is minimum and the rise time is most short；
Under 3.4M data rates, in three kinds of pull-up resistor 1.5K Ω, 2.2K Ω and 4.7K Ω waveform, 4.7K Ω's is upper
Pull-up resistor waveform overshoot is minimum and the rise time is most short.
Above-mentioned three kinds of pull-up resistors have different performances under different pieces of information speed to the influence of signal, are tied according to analysis
Fruit, designer can be made to select different pull-up resistors according to different demands.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
All any modification, equivalent and improvement made within refreshing and principle etc., should be included in the scope of the protection.
Claims (10)
1. a kind of analysis method for being directed to different pull-up resistors in low speed signal, it is characterised in that comprise the following steps：
S1, connect different pull-up resistors respectively on I2C signal wires；
S2, the link topology for obtaining I2C；
S3, setting simulation parameter；
Simulation waveform under S4, the different pull-up resistors of generation；
S5, pull-up resistor selected according to the overshoot of simulation waveform and rise time.
A kind of 2. analysis method for being directed to different pull-up resistors in low speed signal according to claim 1, it is characterised in that
The link topology includes SDA link topologies and SCL link topologies.
A kind of 3. analysis method for being directed to different pull-up resistors in low speed signal according to claim 1, it is characterised in that
The simulation parameter includes acquiescence cut-off frequency and measurement period, and the acquiescence cut-off frequency is set as 10GHz, the measurement week
Phase is 5-8s。
A kind of 4. analysis method for being directed to different pull-up resistors in low speed signal according to claim 1, it is characterised in that
The setting simulation parameter also includes setting different message transmission rates.
5. a kind of analysis method for being directed to different pull-up resistors in low speed signal according to claim 1-4 any one,
Characterized in that, the overshoot and the selection standard of rise time are that overshoot is minimum and the rise time is most short.
A kind of 6. analysis system for being directed to different pull-up resistors in low speed signal, it is characterised in that including：
Pull-up resistor AM access module, for connecting different pull-up resistors respectively on I2C signal wires；
Link topology acquisition module, for obtaining I2C link topology；
Simulation parameter setting module, for setting simulation parameter；
Simulation waveform generation module, for generating the simulation waveform under different pull-up resistors；
Pull-up resistor selecting module, for the overshoot according to simulation waveform and rise time selection pull-up resistor.
A kind of 7. analysis system for being directed to different pull-up resistors in low speed signal according to claim 6, it is characterised in that
The link topology includes SDA link topologies and SCL link topologies.
A kind of 8. analysis system for being directed to different pull-up resistors in low speed signal according to claim 6, it is characterised in that
The simulation parameter includes acquiescence cut-off frequency and measurement period, and the acquiescence cut-off frequency is set as 10GHz, the measurement week
Phase is 5-8s。
A kind of 9. analysis system for being directed to different pull-up resistors in low speed signal according to claim 6, it is characterised in that
The setting simulation parameter also includes setting different message transmission rates.
10. a kind of analysis system for being directed to different pull-up resistors in low speed signal according to claim 6-9 any one,
Characterized in that, the overshoot and the selection standard of rise time are that overshoot is minimum and the rise time is most short.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710979302.1A CN107704701A (en) | 2017-10-19 | 2017-10-19 | A kind of analysis method and system for being directed to different pull-up resistors in low speed signal |
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| CN201710979302.1A CN107704701A (en) | 2017-10-19 | 2017-10-19 | A kind of analysis method and system for being directed to different pull-up resistors in low speed signal |
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Cited By (3)
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| CN109062832A (en) * | 2018-07-26 | 2018-12-21 | 郑州云海信息技术有限公司 | A kind of method, apparatus and storage medium adjusting I2C bus parameter |
| CN110912791A (en) * | 2019-11-07 | 2020-03-24 | 苏州浪潮智能科技有限公司 | System management bus link and pull-up resistance determination method, device and equipment thereof |
| CN114443542A (en) * | 2022-01-23 | 2022-05-06 | 苏州浪潮智能科技有限公司 | Method and device for optimizing bus signal rising time and computer equipment |
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| CN110912791A (en) * | 2019-11-07 | 2020-03-24 | 苏州浪潮智能科技有限公司 | System management bus link and pull-up resistance determination method, device and equipment thereof |
| WO2021088255A1 (en) * | 2019-11-07 | 2021-05-14 | 苏州浪潮智能科技有限公司 | System management bus link, method and apparatus for determining pull-up resistance thereof, and device |
| CN110912791B (en) * | 2019-11-07 | 2021-06-29 | 苏州浪潮智能科技有限公司 | System management bus link and pull-up resistance determination method, device and equipment thereof |
| CN114443542A (en) * | 2022-01-23 | 2022-05-06 | 苏州浪潮智能科技有限公司 | Method and device for optimizing bus signal rising time and computer equipment |
| CN114443542B (en) * | 2022-01-23 | 2023-08-11 | 苏州浪潮智能科技有限公司 | Method and device for optimizing rising time of bus signal and computer equipment |
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