CN107689372B - Semiconductor device, manufacturing method thereof and electronic device - Google Patents

Semiconductor device, manufacturing method thereof and electronic device Download PDF

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CN107689372B
CN107689372B CN201610633429.3A CN201610633429A CN107689372B CN 107689372 B CN107689372 B CN 107689372B CN 201610633429 A CN201610633429 A CN 201610633429A CN 107689372 B CN107689372 B CN 107689372B
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device area
voltage device
layer
oxide layer
core
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CN107689372A (en
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周飞
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Zhongxin Nanfang integrated circuit manufacturing Co.,Ltd.
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

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  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, wherein the manufacturing method comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a low-voltage device area, a high-voltage device area and a core device area, and a virtual grid oxide layer, a virtual grid and an interlayer dielectric layer surrounding the virtual grid oxide layer and the virtual grid are formed in the low-voltage device area, the high-voltage device area and the core device area; removing the dummy gate in the high-voltage device region to form a first opening, and forming an additional oxide layer on the dummy gate oxide layer in the first opening; removing the dummy gates in the low-voltage device area and the core device area to form a second opening and a third opening respectively; removing the dummy gate oxide layer in the third opening and forming an interface layer in the third opening; forming a high-K material layer and a metal gate in the first, second and third openings. The manufacturing method can improve the performance of the device. The semiconductor device and the electronic apparatus have high performance.

Description

Semiconductor device, manufacturing method thereof and electronic device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.
Background
With the development of semiconductor process technology, the critical dimension of semiconductor devices such as MOSFET (metal oxide semiconductor field effect transistor) is continuously shrinking, and at the same time, the Short Channel Effect (SCE) is becoming more and more serious. FinFET devices can be scaled to 20nm and below technology nodes due to their good gate control capability on channel charge. Also, to better overcome problems such as short channel effects, the post-high-K/metal gate process and the replacement gate process are referred to as common processes for 14nm and below technology nodes.
In practical applications, multiple-IO devices (multi-IO devices) are required for high voltage SOC (system on chip) chips, and the multiple-IO devices require gate oxide layers with different thicknesses because the threshold voltages of the devices are different, for example, the threshold voltage of a high threshold voltage IO device is, for example, 3.3V, which correspondingly requires a thicker gate oxide layer, the threshold voltage of a low threshold voltage IO device is, for example, 1.8V, which correspondingly requires a thinner gate oxide layer, and the device threshold voltage of a core (core) device region is, for example, 0.8V, which requires better interface performance and higher dielectric constant. However, in the current multi-IO device (multi-IO device) manufacturing process, the gate oxide layer of the low-voltage device is mostly formed by ALD (atomic layer deposition), CVD (chemical vapor deposition) and other processes, and the interface quality is poor, resulting in the performance degradation of the device.
Therefore, it is necessary to provide a new method for manufacturing a semiconductor device to at least partially solve the above problems.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
Aiming at the defects of the prior art, the invention provides a novel manufacturing method of a semiconductor device, which can improve the interface performance of each grid oxide layer of a multi-IO device and improve the device performance.
In order to overcome the problems existing at present, the invention provides a method for manufacturing a semiconductor device, which comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a low-voltage device area, a high-voltage device area and a core device area, and a virtual grid oxide layer, a virtual grid and an interlayer dielectric layer surrounding the virtual grid oxide layer and the virtual grid are formed on the semiconductor substrate of the low-voltage device area, the high-voltage device area and the core device area; removing the virtual grid electrode in the high-voltage device area to form a first opening, and forming an additional oxide layer on the virtual grid electrode oxide layer in the first opening; removing the dummy gates in the low-voltage device area and the core device area to form a second opening and a third opening respectively; removing the dummy gate oxide layer in the third opening, and forming an interface layer on the semiconductor substrate in the third opening; forming a high-K material layer in the first, second and third openings, and forming a metal gate on the high-K material layer.
Further, the step of removing the dummy gate in the high-voltage device region to form the first opening includes: forming a first shielding layer for shielding the low-voltage device area and the core device area and exposing the high-voltage device area; and removing the virtual grid in the high-voltage device area by taking the first shielding layer as a mask.
Further, the step of forming an additional oxide layer on the dummy gate oxide layer in the first opening includes: forming a dummy gate oxide layer in the opening and an additional oxide layer covering the low-voltage device region and the core device region; forming a second shielding layer for shielding the high-voltage device area and exposing the low-voltage device area and the core device area; and removing the second parts of the additional oxide layer positioned in the low-voltage device area and the core device area by taking the second shielding layer as a mask.
Further, still include: and removing the dummy gates of the low-voltage device area and the core device area by taking the second shielding layer as a mask so as to form the second opening and the third opening respectively.
Further, the step of removing the dummy gate oxide layer in the third opening includes:
forming a third shielding layer for shielding the low-voltage device area and the high-voltage device area and exposing the core device area; and removing the dummy gate oxide layer in the third opening by using the third shielding layer as a mask.
Further, the interfacial layer is formed by a chemical oxidation method.
Further, the method also comprises the following steps: and forming a source electrode and a drain electrode on two sides of the grid electrode.
Further, the method also comprises the following steps: and forming fins on the semiconductor substrate of the low-voltage device area, the high-voltage device area and the core device area, and forming a virtual grid oxide layer, a virtual grid, a source electrode and a drain electrode on the fins.
Further, the dummy gate oxide layer is formed by a thermal oxidation method.
According to the manufacturing method of the semiconductor device, the grid dielectric layer of the low-voltage device area adopts the virtual grid oxide layer of the thermal oxidation method, the interface performance and the film quality are high, the grid dielectric layer of the high-voltage device area adopts the combination of the virtual grid oxide layer, the additional oxide layer and the high-K material, the threshold voltage is high, the grid dielectric layer of the core device area adopts the combination of the interface layer and the high-K material layer, the grid dielectric layer of each area has the thickness meeting the requirements, the interface performance is good, and the device performance is improved.
In another aspect, the present invention provides a semiconductor device fabricated by the above method, the semiconductor device comprising: the semiconductor substrate comprises a low-voltage device area, a high-voltage device area and a core device area, wherein a grid stack and a source electrode and a drain electrode which are positioned on two sides of the grid stack are formed on the semiconductor substrate of the low-voltage device area, the high-voltage device area and the core device area, the grid stack positioned in the low-voltage device area comprises a grid oxide layer, a high-K material layer and a metal grid electrode, the grid stack positioned in the high-voltage device area comprises a grid oxide layer, an additional oxide layer, a high-K material layer and a metal grid electrode, and the grid stack positioned in the core device area comprises an interface layer, a high-K material layer and a metal grid electrode.
Each device area of the semiconductor device provided by the invention is provided with the grid dielectric layer with the thickness and the interface performance meeting the requirements, so that the semiconductor device has higher performance.
A further aspect of the invention provides an electronic device comprising a semiconductor device as described above and an electronic component connected to the semiconductor device.
The electronic device provided by the invention has similar advantages due to the semiconductor device.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIGS. 1A-1I schematically illustrate steps in a present fabrication process for a multi-IO semiconductor device;
FIG. 2 is a flow chart illustrating steps in a method of fabricating a semiconductor device according to an embodiment of the present invention;
fig. 3A to 3I are schematic cross-sectional views of a semiconductor device obtained by sequentially performing steps according to a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 4 shows a cross-sectional view of a semiconductor device according to an embodiment of the invention;
fig. 5 shows a schematic view of an electronic device according to an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity to indicate like elements throughout.
It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
For better understanding of the present invention, a method for fabricating a multi-IO semiconductor device is first described with reference to fig. 1A to 1I. Fig. 1A to 1I schematically show steps of a current manufacturing process of a multi-IO semiconductor device.
As shown in fig. 1A to 1I, the current method for manufacturing a multi-IO semiconductor device includes the following steps:
first, as shown in fig. 1A, a semiconductor substrate 100 is provided, the semiconductor substrate 100 includes a low voltage device region L, a high voltage device region H, and a CORE device region CORE, the low voltage device region L, the high voltage device region H, and the CORE device region CORE are separated by an isolation structure 101, a fin 102 is formed on the low voltage device region L, the high voltage device region H, and the CORE device region CORE, a dummy gate structure and source/drain electrodes 106 located at two sides of the dummy gate structure are formed on the fin 102, wherein the dummy gate structure includes a dummy gate oxide layer 103, a dummy gate 104, and a spacer 105. An etch stop layer 107 and an interlayer dielectric layer including the dummy gate structure are formed on the dummy gate structure and the semiconductor substrate. The inter-layer dielectrics include an initial inter-layer dielectric (ILD0)108, a high aspect ratio process layer (HARP)109, and a first inter-layer dielectric (ILD1)110, which may be USG (undoped silicon glass), PSG (phosphorus doped silicon glass), BPSG (boron phosphorus silicon glass), low K or ULK (ultra low K) materials.
Then, as shown in fig. 1B, a planarization operation is performed to remove the portion of the interlayer dielectric layer higher than the dummy gate structure.
Next, as shown in fig. 1C, the dummy gate in the dummy gate structure is removed to form an opening.
Next, as shown in fig. 1D, a first shielding layer 111 is formed to shield the high voltage device region H and expose the low voltage device region L and the core device region core.
Next, as shown in fig. 1E, the dummy gate oxide layer 103 in the low voltage device region L and the core device region core is removed by using the first shielding layer 111 as a mask.
Next, as shown in fig. 1F, an additional oxide layer 112 is formed in the low-voltage device region L, the high-voltage device region H, and the CORE device region CORE, which is formed by, for example, an ALD method.
Next, as shown in fig. 1G, a second shielding layer 113 shielding the low voltage device region L and the high voltage device region H and exposing the core device region core is formed.
Next, as shown in fig. 1H, the additional oxide layer 112 in the core device region core is removed by using the second shielding layer 113 as a mask.
Then, as shown in fig. 1I, an interface layer 114 is formed on the semiconductor substrate of the CORE device region CORE, and a high-K material layer 115 and a metal gate (not shown) are formed on the low-voltage device region L, the high-voltage device region H, and the CORE device region CORE.
As described above, in the current multi-IO device (multi-IO device) manufacturing process, the gate oxide layer of the low-voltage device is mostly formed by ALD (atomic layer deposition), CVD (chemical vapor deposition) and other processes, and the interface quality is poor, which results in the performance degradation of the device. In order to solve the above problem, the present invention provides a method for manufacturing a semiconductor device, which is used for a multi-IO semiconductor device, and as shown in fig. 2, the method includes: step 201: providing a semiconductor substrate, wherein the semiconductor substrate comprises a low-voltage device area, a high-voltage device area and a core device area, and a virtual grid oxide layer, a virtual grid and an interlayer dielectric layer surrounding the virtual grid oxide layer and the virtual grid are formed on the semiconductor substrate of the low-voltage device area, the high-voltage device area and the core device area; step 202: removing the virtual grid electrode in the high-voltage device area to form a first opening, and forming an additional oxide layer on the virtual grid electrode oxide layer in the first opening; step 203: removing the dummy gates in the low-voltage device area and the core device area to form a second opening and a third opening respectively; step 204: removing the dummy gate oxide layer in the third opening, and forming an interface layer on the semiconductor substrate in the third opening; step 205: forming a high-K material layer in the first, second and third openings, and forming a metal gate on the high-K material layer.
According to the manufacturing method of the semiconductor device, the grid dielectric layer of the low-voltage device area adopts the virtual grid oxide layer of the thermal oxidation method, the interface performance and the film quality are high, the grid dielectric layer of the high-voltage device area adopts the combination of the virtual grid oxide layer, the additional oxide layer and the high-K material, the threshold voltage is high, the grid dielectric layer of the core device area adopts the combination of the interface layer and the high-K material layer, the grid dielectric layer of each area has the thickness meeting the requirements, the interface performance is good, and the device performance is improved.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Example one
A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail below with reference to fig. 3A to 3I.
First, as shown in fig. 3A, a semiconductor substrate 300 is provided, the semiconductor substrate 300 includes a low voltage device region L, a high voltage device region H, and a CORE device region CORE, the low voltage device region L, the high voltage device region H, and the CORE device region CORE are separated by an isolation structure 301, a fin 302 is formed on the low voltage device region L, the high voltage device region H, and the CORE device region CORE, and a dummy gate structure and source/drain electrodes 306 located at two sides of the dummy gate structure are formed on the fin 302. An etch stop layer 307 and an interlayer dielectric layer covering or surrounding the dummy gate structure are also formed on the semiconductor substrate 300.
Among them, the semiconductor substrate 300 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). As an example, in the present embodiment, the constituent material of the semiconductor substrate 300 is single crystal silicon.
The semiconductor substrate 300 at least comprises a low-voltage device region L, a high-voltage device region H and a CORE device region CORE, wherein the low-voltage device region L is used for manufacturing devices with low threshold voltage, and the device region needs to form a thinner gate dielectric layer. The high voltage device region H is used for making high threshold voltage devices, which requires the formation of a thicker gate dielectric layer. The CORE device region CORE is used to fabricate CORE devices, which have smaller threshold voltages and thus require high-K materials. The high-voltage device region L, the high-voltage device region H, and the CORE device region CORE may be separated by an isolation structure 301. The isolation structure 301 may employ a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure. Illustratively, in the present embodiment, the isolation structure 301 employs Shallow Trench Isolation (STI), and the isolation material thereof employs an oxide such as silicon oxide.
In the present embodiment, the semiconductor devices in the low-voltage device region L, the high-voltage device region H and the CORE device region CORE adopt a finfet structure, so that the low-voltage device region L, the high-voltage device region H and the CORE device region CORE are formed with the fin 302 on the semiconductor substrate, and the fin 302 may be exemplarily defined together with the isolation structure 301 by using a method commonly used in the art. Of course, in other embodiments, a planar semiconductor device may be used instead of the finfet structure, and the method for manufacturing the multi-IO device of the present invention may also be applied.
The dummy gate structure includes a dummy gate oxide layer 303, a dummy gate 304, and spacers 305. The dummy gate oxide layer 303 is illustratively silicon oxide, which is formed by a thermal oxidation method, having good film quality and high interface performance. The dummy gate 304 is made of a semiconductor material such as polysilicon, and is formed by one of selective Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD), and Selective Epitaxial Growth (SEG). The spacers 305 may be formed by conventional materials such as oxide, nitride, oxynitride, etc. through ALD, CVD, PVD processes, and will not be described herein.
The source and drain 306 may be formed by LDD implantation, ion doping, and sige epitaxy processes in the art, which are not described herein.
The etch stop layer 307 may be made of nitride such as silicon nitride, and is used as a stop layer for the subsequent formation of a contact hole.
The ILD layers include initial ILD0 (ILD0), high aspect ratio process layer (HARP)309 (ILD1) and first ILD1 (ILD1), which may be USG (undoped silicate glass), PSG (phosphorous doped silicate glass), BPSG (boron phosphorous silicate glass), low K or ULK (ultra low K) suitable materials. The interlayer dielectric layer may be formed by ALD, CVD, spin coating, or the like.
Next, as shown in FIG. 3B, planarization of the interlayer dielectric layer is performed to remove the portion above the dummy gate structure.
Specifically, a planarization process such as CMP (chemical mechanical planarization), mechanical polishing, etc. is performed on the interlayer dielectric layer to remove a portion of the interlayer dielectric layer higher than the dummy gate structure.
Next, as shown in fig. 3C, the dummy gate 304 in the high-voltage device region is removed to form a first opening 311.
Specifically, removing the dummy gate 304 in the high-voltage device region to form the first opening 311 is accomplished by: first, a first shielding layer (not shown) shielding the low voltage device region L and the core device region core while exposing the high voltage device region H is formed; then, the dummy gate 304 in the high-voltage device region H is removed by using the first shielding layer as a mask, so as to form a first opening 311.
The first shielding layer is illustratively a photoresist layer, which can be patterned by exposure, development, etc. to shield the low voltage device region L and the core device region core and expose the high voltage device region H. The removal of the dummy gate 304 may be accomplished using a suitable etch process. The etching process adopts a proper wet etching process and a proper dry etching process. The wet etching process includes various suitable wet etching processes such as a mixed solution of nitric acid and hydrofluoric acid, and the dry etching process includes but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting.
Next, as shown in fig. 3D, an additional oxide layer 312 is formed on the dummy gate oxide layer 303 in the first opening 311 to increase the thickness of the gate oxide layer in the high-voltage device region H, thereby achieving a better threshold voltage.
Illustratively, the additional oxide layer 312 is silicon oxide, which is formed by a process such as CVD, ALD, or the like. The thickness of which can be adjusted as required.
It is understood that, inevitably, an additional oxide layer 312 is formed on the sidewalls of the first opening 311 and the surfaces of the low voltage device region L and the core device region.
Next, as shown in fig. 3E, a second shielding layer 313 is formed to shield the high voltage device region H and expose the low voltage device region L and the core device region core.
The second shielding layer 313 is illustratively a photoresist layer, which may be patterned by exposure, development, etc. to shield the high voltage device region H and expose the low voltage device region L and the core device region core.
Next, as shown in fig. 3F, portions of the additional oxide layer 312 in the low voltage device region L and the core device region core are removed, and the dummy gate 304 in the low voltage device region L and the core device region core is removed to form a second opening 314 and a third opening 315, respectively.
Specifically, with the second shielding layer 313 as a mask, the portions of the additional oxide layer 312 located in the low-voltage device region L and the core device region core are removed through a suitable wet etching process or a suitable dry etching process, and the dummy gate 304 in the low-voltage device region L and the core device region core is removed, so as to form a second opening 314 and a third opening 315, respectively. The wet etching process includes various suitable wet etching processes such as hydrofluoric acid, and a mixed solution of nitric acid and hydrofluoric acid, and the dry etching process includes but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting.
After this operation is performed, the second shielding layer 313 may be removed by a suitable volume or ashing method.
Next, as shown in fig. 3G, a third shielding layer 316 is formed to shield the low voltage device region L and the high voltage device region H and expose the core device region core.
The third shielding layer 316 is illustratively a photoresist layer, which may be patterned by exposure, development, etc., to shield the low voltage device region L and the high voltage device region H and expose the core device region core.
Next, as shown in fig. 3H, the dummy gate oxide layer 303 of the core device region core is removed.
Specifically, the dummy gate oxide layer 303 of the core device region core is removed by a suitable wet etching or dry etching process using the third shielding layer 316 as a mask. The wet etching process includes various suitable wet etching processes such as hydrofluoric acid, and a mixed solution of nitric acid and hydrofluoric acid, and the dry etching process includes but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting.
After this operation is performed, the third shielding layer 316 may be removed by a suitable volume or ashing method.
Finally, as shown in fig. 3I, an interface layer 317 is formed on the semiconductor substrate of the CORE device region CORE, and a high-K material layer 318 and a metal gate (not shown) are formed on the low-voltage device region L, the high-voltage device region H, and the CORE device region CORE.
Illustratively, the interfacial layer 317 is formed by a chemical oxidation method, such as oxidizing the semiconductor substrate 300 by a hydrogen peroxide solution with a proper ratio, so as to form the interfacial layer 317 on the semiconductor substrate of the core device region core, thereby obtaining a thinner interfacial layer with good interfacial properties. Illustratively, the interfacial layer 317 is as thick as
Figure BDA0001069434680000111
The high-K material layer 318 may be formed by a method such as ALD (atomic layer deposition) using a high dielectric constant material such as hafnium oxide (HfO2), titanium dioxide (TiO2), zirconium dioxide (ZrO2), or the like. The metal gate may be made of a metal gate material such as Al and/or TiAl, which may be formed by PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), or the like.
Now, the process steps performed by the method according to the embodiment of the present invention are completed, and it is understood that the method for manufacturing a semiconductor device according to the embodiment of the present invention may include not only the above steps, but also other required steps, such as the removal of photoresist and the wafer cleaning step, before, during or after the above steps.
In the method for manufacturing the semiconductor device, the gate dielectric layer of the low-voltage device region adopts the virtual gate oxide layer of the thermal oxidation method, which has high interface performance and film quality, the gate dielectric layer of the high-voltage device region adopts the combination of the virtual gate oxide layer, the additional oxide layer and the high-K material, so that the gate dielectric layer of the core device region has a thickness meeting the requirements and has good interface performance, and the device performance is improved.
Example two
The present invention also provides a semiconductor device manufactured by the above method, as shown in fig. 4, the semiconductor device including: the semiconductor substrate 400 comprises a low-voltage device region L, a high-voltage device region H and a core device region core, wherein a gate stack and a source and a drain 408 which are positioned on two sides of the gate stack are formed on the semiconductor substrate of the low-voltage device region L, the high-voltage device region H and the core device region core, wherein the gate stack positioned in the low-voltage device region L comprises a gate oxide layer 403, a high-K material layer 406 and a metal gate (not shown), the gate stack positioned in the high-voltage device region H comprises the gate oxide layer 403, an additional oxide layer 404, the high-K material layer 406 and the metal gate (not shown), and the gate stack positioned in the core device region core comprises an interface layer 405, the high-K material layer 406 and the metal gate (not shown).
Among them, the semiconductor substrate 400 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). Devices, such as NMOS and/or PMOS, etc., may be formed on the semiconductor substrate. Also, a conductive member may be formed in the semiconductor substrate, and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like. In this embodiment, the constituent material of the semiconductor substrate 400 is monocrystalline silicon.
The semiconductor substrate 400 includes at least a low voltage device region L for making devices with low threshold voltage, a high voltage device region H for making devices with low threshold voltage, and a CORE device region CORE. The high voltage device region H is used for making high threshold voltage devices, which requires the formation of a thicker gate dielectric layer. The CORE device region CORE is used to fabricate CORE devices, which have smaller threshold voltages and thus require high-K materials. The piezoelectric device region L, the high-voltage device region H, and the CORE device region CORE may be separated by an isolation structure 401. The isolation structure 401 may employ a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure. Illustratively, in the present embodiment, the isolation structure 401 employs Shallow Trench Isolation (STI), and the isolation material thereof employs an oxide such as silicon oxide.
In the present embodiment, the semiconductor devices in the low-voltage device region L, the high-voltage device region H and the CORE device region CORE adopt a finfet structure, so that the semiconductor substrate in the low-voltage device region L, the high-voltage device region H and the CORE device region CORE is formed with a fin 402, and the fin 402 may be exemplarily defined together with the isolation structure 401 by using a method commonly used in the art. Of course, in other embodiments, a planar semiconductor device may be used instead of the finfet structure, and the method for manufacturing the multi-IO device of the present invention may also be applied.
The gate oxide layer 403 is illustratively a silicon oxide layer, which may be formed by a thermal oxidation method to obtain good interface properties and film quality. The additional oxide layer 404 is illustratively a silicon oxide layer which may be formed by PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), or the like. Interface layer 405 is illustratively a silicon oxide layer, which is formed by a chemical oxidation process. The high-K material layer 406 may be formed using a high dielectric constant material such as hafnium oxide (HfO2), titanium dioxide (TiO2), zirconium dioxide (ZrO2), or the like, by a method such as ALD (atomic layer deposition). The metal gate may be made of a metal gate material such as Al and/or TiAl, which may be formed by PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), or the like.
The semiconductor device of this embodiment further includes spacers 407 formed on both sides of the gate stack, which may be formed of a suitable material such as oxide, nitride, oxynitride, or the like.
The source and drain 408 may be formed by LDD implantation, ion doping, and sige epitaxy processes in the art, which are not described herein.
The semiconductor device of this embodiment further includes an etch stop layer 409 and an interlayer dielectric layer 410 surrounding the gate stack. Wherein the etch stop layer 409 may be a nitride such as silicon nitride, etc., and is used as a stop layer for the subsequent fabrication of contact holes. The interlayer dielectric layer 410 may be made of suitable materials such as USG (undoped silicate glass), PSG (phosphorus doped silicate glass), BPSG (borophosphosilicate glass), low K or ULK (ultra low K). The interlayer dielectric layer may be formed by ALD, CVD, spin coating, or the like.
Each device region of the semiconductor device of the embodiment has the gate dielectric layer with the thickness and the interface performance meeting the requirements, so that the semiconductor device has higher performance.
EXAMPLE III
Yet another embodiment of the present invention provides an electronic apparatus including a semiconductor device and an electronic component connected to the semiconductor device. Wherein, this semiconductor device includes: the semiconductor substrate comprises a low-voltage device area, a high-voltage device area and a core device area, wherein a grid stack and a source electrode and a drain electrode which are positioned on two sides of the grid stack are formed on the semiconductor substrate of the low-voltage device area, the high-voltage device area and the core device area, the grid stack positioned in the low-voltage device area comprises a grid oxide layer, a high-K material layer and a metal grid electrode, the grid stack positioned in the high-voltage device area comprises a grid oxide layer, an additional oxide layer, a high-K material layer and a metal grid electrode, and the grid stack positioned in the core device area comprises an interface layer, a high-K material layer and a metal grid electrode.
Wherein the semiconductor substrate may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). Devices, such as NMOS and/or PMOS, etc., may be formed on the semiconductor substrate. Also, a conductive member may be formed in the semiconductor substrate, and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like. In addition, an isolation structure, which is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure, may be formed in the semiconductor substrate. As an example. In this embodiment, the constituent material of the semiconductor substrate is monocrystalline silicon.
The gate oxide layer is illustratively a silicon oxide layer, which may be formed by a thermal oxidation process to obtain good interface properties and film quality. The additional oxide layer is illustratively a silicon oxide layer which can be formed by PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), or the like. The high-K material layer may be formed using a high dielectric constant material such as hafnium oxide (HfO2), titanium dioxide (TiO2), zirconium dioxide (ZrO2), or the like, by a method such as ALD (atomic layer deposition). The metal gate may be made of a metal gate material such as Al and/or TiAl, which may be formed by PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), or the like.
The electronic component may be any electronic component such as a discrete device and an integrated circuit.
The electronic device of this embodiment may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice pen, an MP3, an MP4, and a PSP, and may also be any intermediate product including the semiconductor device.
Fig. 5 shows an example of a mobile phone. The exterior of the cellular phone 500 is provided with a display portion 502, operation buttons 503, an external connection port 504, a speaker 505, a microphone 506, and the like, which are included in a housing 501.
The electronic device of the embodiment of the invention has higher performance because each device area of the contained semiconductor device is provided with the grid dielectric layer with the thickness and the interface performance meeting the requirements. The electronic device also has similar advantages.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (11)

1. A method for manufacturing a semiconductor device, comprising the steps of:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a low-voltage device area, a high-voltage device area and a core device area, and a virtual grid oxide layer, a virtual grid and an interlayer dielectric layer surrounding the virtual grid oxide layer and the virtual grid are formed on the semiconductor substrate of the low-voltage device area, the high-voltage device area and the core device area;
removing the virtual grid electrode in the high-voltage device area to form a first opening, and forming an additional oxide layer on the virtual grid electrode oxide layer in the first opening;
removing the dummy gates in the low-voltage device area and the core device area to form a second opening and a third opening respectively;
removing the dummy gate oxide layer in the third opening, and forming an interface layer on the semiconductor substrate in the third opening;
forming a high-K material layer in the first, second and third openings, and forming a metal gate on the high-K material layer.
2. The method for manufacturing the semiconductor device according to claim 1, wherein the step of removing the dummy gate in the high-voltage device region to form the first opening comprises:
forming a first shielding layer for shielding the low-voltage device area and the core device area and exposing the high-voltage device area;
and removing the virtual grid in the high-voltage device area by taking the first shielding layer as a mask.
3. The method of claim 2, wherein the step of forming an additional oxide layer over the dummy gate oxide layer in the first opening comprises:
forming a dummy gate oxide layer in the opening and an additional oxide layer covering the low-voltage device region and the core device region;
forming a second shielding layer for shielding the high-voltage device area and exposing the low-voltage device area and the core device area;
and removing the parts of the additional oxide layer positioned in the low-voltage device area and the core device area by taking the second shielding layer as a mask.
4. The method for manufacturing a semiconductor device according to claim 3, further comprising:
and removing the dummy gates of the low-voltage device area and the core device area by taking the second shielding layer as a mask so as to form the second opening and the third opening respectively.
5. The method of claim 1, wherein the step of removing the dummy gate oxide layer in the third opening comprises:
forming a third shielding layer for shielding the low-voltage device area and the high-voltage device area and exposing the core device area;
and removing the dummy gate oxide layer in the third opening by using the third shielding layer as a mask.
6. The method for manufacturing a semiconductor device according to claim 1, wherein the interface layer is formed by a chemical oxidation method.
7. The method for manufacturing a semiconductor device according to claim 1, further comprising the steps of:
and forming a source electrode and a drain electrode on two sides of the grid electrode.
8. The method for manufacturing a semiconductor device according to claim 7, further comprising the steps of:
and forming fins on the semiconductor substrate of the low-voltage device area, the high-voltage device area and the core device area, and forming a virtual grid oxide layer, a virtual grid, a source electrode and a drain electrode on the fins.
9. The method for manufacturing a semiconductor device according to claim 1, wherein the dummy gate oxide layer is formed by a thermal oxidation method.
10. A semiconductor device manufactured by the manufacturing method according to any one of claims 1 to 9, comprising: the semiconductor substrate comprises a low-voltage device area, a high-voltage device area and a core device area, wherein a grid stack and a source electrode and a drain electrode which are positioned on two sides of the grid stack are formed on the semiconductor substrate of the low-voltage device area, the high-voltage device area and the core device area, the grid stack positioned in the low-voltage device area comprises a grid oxide layer, a high-K material layer and a metal grid electrode, the grid stack positioned in the high-voltage device area comprises a grid oxide layer, an additional oxide layer, a high-K material layer and a metal grid electrode, and the grid stack positioned in the core device area comprises an interface layer, a high-K material layer and a metal grid electrode.
11. An electronic device comprising the semiconductor device according to claim 10 and an electronic component connected to the semiconductor device.
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