CN107682126B - Ethernet network transmission performance testing device - Google Patents
Ethernet network transmission performance testing device Download PDFInfo
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- CN107682126B CN107682126B CN201711177802.XA CN201711177802A CN107682126B CN 107682126 B CN107682126 B CN 107682126B CN 201711177802 A CN201711177802 A CN 201711177802A CN 107682126 B CN107682126 B CN 107682126B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0805—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability
- H04L43/0817—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability by checking functioning
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0006—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format
- H04L1/0007—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format by modifying the frame length
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
Abstract
The invention discloses an Ethernet network transmission performance testing device, which belongs to the field of network communication testing and comprises a sending part and a receiving part; the sending part mainly comprises a test frame data storage circuit, a frame interval control circuit, a burst control circuit, a time control circuit, a sending state machine, a time mark sequence number inserting circuit, a check inserting circuit and an output circuit; the receiving part mainly comprises an input circuit, a test frame identification circuit, an error check circuit, a sending time mark extraction circuit, a receiving time mark latch circuit, a serial number extraction circuit, a test frame counting circuit, a pseudo-random sequence extraction circuit, a reset time test circuit, a time delay test circuit, a recovery time test circuit, a packet loss rate test circuit, a throughput test circuit, an error code test circuit and a test result memory. The invention can complete the test of all performance parameters at one time, improve the test efficiency and shorten the test time.
Description
Technical Field
The invention belongs to the field of network communication testing, and particularly relates to an Ethernet network transmission performance testing device.
Background
Network technologies are widely used, with increasingly higher transmission rates. The testing requirements for network communication devices are high. How to simulate data generation of an actual network is one of the key technologies of network transmission test. At present, in general Ethernet tests, a static data frame is respectively edited to carry out single parameter tests, and test frames of various manufacturers are incompatible and cannot be tested mutually.
Disclosure of Invention
Aiming at the technical problems in the prior art, the invention provides an Ethernet network transmission performance testing device, which can edit a testing frame and can finish the testing of all network transmission performance parameters at one time. Reasonable in design has overcome prior art's not enough, has improved efficiency of software testing, has good application effect.
In order to achieve the purpose, the invention adopts the following technical scheme:
an Ethernet network transmission performance testing device firstly defines the format of an Ethernet testing frame:
editing one or more test frames, wherein each test frame comprises a source MAC address, a destination MAC address, a source IP address, a destination IP address, a test frame mark, test data and a time mark; wherein, the source MAC address, the destination MAC address, the source IP address and the destination IP address in the test frame are determined according to the test scene; the length value of the test frame in the test frame is determined according to the frame length set by a user, and the length value of the test frame is equal to the frame length of-46 bytes; the test data in the test frame is set by a user, and the length of the test data is-12 bytes which is the length value of the test frame; the pseudo-random sequence in the test frame is continuous; the time mark in the test frame is automatically generated through the FPGA circuit and is synthesized into the test frame when being sent;
the Ethernet network transmission performance testing device specifically comprises a sending part and a receiving part;
a transmitting part configured to complete the construction of the test frame and transmit the test frame; the system mainly comprises a test frame data storage circuit, a frame interval control circuit, a burst control circuit, a time control circuit, an address control circuit, a sending state machine circuit, a time mark sequence number inserting circuit, a sending sequence number and time mark generating circuit, a sending time mark latching circuit, a verification inserting circuit and an output circuit;
a test frame data storage circuit configured to store frame data defined by the test frame;
a frame interval control circuit configured to control an interval time period between each frame;
a burst control circuit configured to control the number of consecutive transmission frames;
a time control circuit configured to control a transmission duration of the test frame;
the address control circuit is configured to perform multi-port RFC2544 test, and automatically insert the MAC destination address, the IP destination address and the channel identification number of a port which needs to be reached by a test frame into the test frame;
a transmit state machine circuit configured to generate a test frame;
a time stamp sequence number insertion circuit configured to insert a sequence number of a currently transmitted frame and a time stamp into the currently transmitted frame;
a transmission sequence number and time mark generating circuit for generating a transmission sequence number and a time mark, which are inserted into the transmission frame by using the time mark sequence number inserting circuit;
a transmission time mark latch circuit configured to test the system recovery time, latch the last time mark when the test period is finished according to the overload rate, and then retransmit the test frame according to the normal rate for the sum of the test period time and the threshold time;
check insertion circuitry configured to insert the calculated CRC32 check value into the last four byte positions of the frame;
the output circuit is configured to transmit the entire test frame;
a receiving part configured to complete the reception, identification and measurement of each parameter of the test frame; the device mainly comprises an input circuit, a test frame identification circuit, a test frame error detection circuit, a sending time mark extraction circuit, a receiving time mark latch circuit, a serial number extraction circuit, a test frame counting circuit, a pseudo-random sequence extraction circuit, a reset time test circuit, a time delay test circuit, a recovery time test circuit, a packet loss rate test circuit, a throughput test circuit, an error code test circuit and a test result memory;
an input circuit configured to receive and process Ethernet frames arriving at a port, including test frames and non-test frames;
the test frame identification circuit is configured to continuously detect the test frame mark, latch the length byte of the test frame mark into a RAM, and judge whether the length of the actually detected test frame is consistent with the latched length or not when the frame is finished;
the test frame error detection circuit is configured to perform error detection on the identified test frame, mainly detect whether the test frame is verified correctly or not, if not, directly discard the test frame, and do not perform the following operations;
a transmit time stamp extraction circuit configured to extract a transmit time stamp in the valid time stamp test frame;
a receiving time scale latch circuit configured to latch arrival times of all the test frames;
a sequence number extraction circuit configured to extract a transmission sequence number in the test frame;
a test frame counting circuit configured to count the number of all valid time scale test frames, and calculate an average interval time (interval time is the arrival time of the current frame-arrival time of the previous frame), that is, a jitter value;
the pseudo-random sequence extraction circuit is configured to strip out pseudo-random sequence data from the received test frame, and send the pseudo-random sequence data to the error code test circuit for error code test;
the reset time test circuit is configured to continuously latch arrival moments of two adjacent lost frames, and the difference value of the arrival moments is the system reset time;
the time delay test circuit is configured to continuously count the delay time of all time delay test frames and latch the maximum delay time and the minimum delay time;
the recovery time testing circuit is configured to latch the time of a time delay testing frame which arrives when the time exceeds a time threshold after the frame is lost, and subtract the time with a sending time mark latched by a sender to obtain the system recovery time;
the packet loss rate testing circuit is configured to count the number of the testing frames received after the testing is started, compare the number with the sent frame data and calculate the packet loss rate;
the throughput testing circuit is configured to count the maximum number of testing frames received in unit time after the testing is started, compare the maximum number of testing frames with the sent frame data and calculate the throughput;
the error code testing circuit is configured to carry out bit synchronization on the pseudo-random sequence shared from the testing frame and the pseudo-random sequence generated by the receiving end, detect errors and calculate an error rate;
a test result storage configured to store all test results.
The invention has the following beneficial technical effects:
(1) the test frame format suitable for all parameter tests is defined, the types of the test frames are reduced, the use of programming is facilitated, the programming workload is reduced, and the efficiency is improved.
(2) The test of all parameters of the network transmission performance can be completed at one time, and the test time is shortened;
(3) the method is suitable for testing the transmission performance of the Ethernet with the speed of less than 10 Gbps;
drawings
Fig. 1 is a diagram illustrating a test frame definition format.
Fig. 2 is a schematic block diagram of the transmit section of the present invention.
Fig. 3 is a schematic block diagram of the receive part of the present invention.
Detailed Description
The invention is described in further detail below with reference to the following figures and detailed description:
the invention provides an Ethernet network transmission performance testing device, which edits a testing frame and can finish the testing of all network transmission performance parameters at one time.
As shown in fig. 1, the present invention defines an ethernet test frame. The test includes the source MAC address (6 bytes), the destination MAC address (6 bytes), the type (2 bytes), the IP header (20 bytes), the UDP header (8 bytes), the test data portion (N bytes), and the CRC check (4 bytes). The source MAC address, the destination MAC address, the source IP address, and the destination IP address may all be preset with a fixed value, and if required by the test, the dynamic address may be automatically generated by the hardware circuit shown in fig. 2. The CRC check is automatically generated by the hardware circuit shown in fig. 2.
The test data section consists of a test frame ID (4 bytes), a test frame length (2 bytes), test data (N-12 bytes) and a time stamp (6 bytes). The test frame ID is fixed as a character, and the length value of the test frame is determined according to the length of the test data part. The time stamp is automatically generated by the hardware circuit shown in fig. 2. The test data portion is automatically generated by the hardware circuit shown in FIG. 2 as a set certain dummyRandom sequences (e.g. 2)n-1 sequence, n being a part of 11,13,15,17,20,23, 31). This data in each frame is concatenated to form a complete pseudo-random sequence.
One or more test frames are set for each transmit port using the test frame format shown in fig. 1. Each test frame data is written into a frame data memory of the transmission circuit. Each frame has a maximum length of 16384 bytes.
As shown in fig. 2, the transmitting part mainly comprises a test frame data storage circuit, a frame interval control circuit, a burst control circuit, a time control circuit, an address control circuit, a transmitting state machine circuit, a time mark sequence number insertion circuit, a transmitting time mark latch circuit, a check insertion circuit and an output circuit.
Writing frame data defined by the test frame into a test frame data memory; generating a test frame according to the timing generated by the frame interval control circuit and the burst control circuit; the sending duration of the test frame is realized by a time control circuit; the address control circuit is used for multi-port RFC2544 test, and automatically inserts the MAC destination address, the IP destination address and the channel identification number of a test frame to a port; the sending state machine circuit generates a test frame according to the information; the time mark and sequence number inserting circuit inserts the sequence number and the time mark of the current sending frame into the current sending frame; the mark control circuit is used for testing time delay, when a test frame is transmitted for half, a time delay test mark needs to be inserted, and the time delay test mark is used for identifying and extracting a transmission time mark by a receiving part; the sending time mark latch circuit is used for testing the recovery time of the system, latching the last time mark when the test period is sent according to the overload rate, then resending the test frame according to the normal rate, and continuing the sum of the time of one test period and the threshold time; and finally, inserting the CRC32 check value obtained by calculation into the last four byte positions of the frame by the check insertion circuit, and sending the whole test frame by the output circuit.
As shown in fig. 3, a receiving section configured to complete reception, identification, and measurement of each parameter of the test frame; the device mainly comprises an input circuit, a test frame identification circuit, a test frame error detection circuit, a sending time mark extraction circuit, a receiving time mark latch circuit, a sequence number extraction circuit, a test frame counting circuit, a pseudo-random sequence extraction circuit, a reset time test circuit, a time delay test circuit, a recovery time test circuit, a packet loss rate test circuit, a throughput test circuit, an error code test circuit and a test result memory.
The input circuit of the receiving end receives and processes the Ethernet frames arriving at the port, wherein the Ethernet frames comprise test frames and non-test frames. And the test frame identification circuit continuously detects the test frame mark, latches the length byte of the test frame mark into a RAM, and judges whether the length of the actually detected test frame is consistent with the latched length or not when the frame is finished. The design supports nesting of test frames and always enables the last valid test frame. The test frame error detection circuit carries out error detection on the identified test frame, mainly detects whether the test frame is verified correctly or not, if not, the test frame is directly abandoned, and the following operation is not carried out.
An input circuit configured to receive and process Ethernet frames arriving at a port, including test frames and non-test frames;
the test frame identification circuit is configured to continuously detect the test frame mark, latch the length byte of the test frame mark into a RAM, and judge whether the length of the actually detected test frame is consistent with the latched length or not when the frame is finished;
the test frame error detection circuit is configured to perform error detection on the identified test frame, mainly detect whether the test frame is verified correctly or not, if not, directly discard the test frame, and do not perform the following operations;
a transmit time stamp extraction circuit configured to extract a transmit time stamp in the valid time stamp test frame;
a receiving time scale latch circuit configured to latch arrival times of all the test frames;
a sequence number extraction circuit configured to extract a transmission sequence number in the test frame;
a test frame counting circuit configured to count the number of all valid time scale test frames, and calculate an average interval time (interval time is the arrival time of the current frame-arrival time of the previous frame), that is, a jitter value;
the pseudo-random sequence extraction circuit is configured to strip out pseudo-random sequence data from the received test frame, and send the pseudo-random sequence data to the error code test circuit for error code test;
the reset time test circuit is configured to continuously latch arrival moments of two adjacent lost frames, and the difference value of the arrival moments is the system reset time;
the time delay test circuit is configured to continuously count the delay time of all time delay test frames and latch the maximum delay time and the minimum delay time;
the recovery time testing circuit is configured to latch the time of a time delay testing frame which arrives when the time exceeds a time threshold after the frame is lost, and subtract the time with a sending time mark latched by a sender to obtain the system recovery time;
the packet loss rate testing circuit is configured to count the number of the testing frames received after the testing is started, compare the number with the sent frame data and calculate the packet loss rate;
the throughput testing circuit is configured to count the maximum number of testing frames received in unit time after the testing is started, compare the maximum number of testing frames with the sent frame data and calculate the throughput;
the error code testing circuit is configured to carry out bit synchronization on the pseudo-random sequence shared from the testing frame and the pseudo-random sequence generated by the receiving end, detect errors and calculate an error rate;
and the test result storage is configured to store all the test results and send the test results to the host computer through the data bus in a timing mode to form a test report or a test graph.
It is to be understood that the above description is not intended to limit the present invention, and the present invention is not limited to the above examples, and those skilled in the art may make modifications, alterations, additions or substitutions within the spirit and scope of the present invention.
Claims (1)
1. An Ethernet network transmission performance testing device is characterized in that: firstly, defining the format of an Ethernet test frame:
editing one or more test frames, wherein each test frame comprises a source MAC address, a destination MAC address, a source IP address, a destination IP address, a test frame mark, test data and a time mark; wherein, the source MAC address, the destination MAC address, the source IP address and the destination IP address in the test frame are determined according to the test scene; the length value of the test frame in the test frame is determined according to the frame length set by a user, and the length value of the test frame is equal to the frame length of-46 bytes; the test data in the test frame is set by a user, and the length of the test data is-12 bytes which is the length value of the test frame; the pseudo-random sequence in the test frame is continuous; the time mark in the test frame is automatically generated through the FPGA circuit and is synthesized into the test frame when being sent;
the Ethernet network transmission performance testing device specifically comprises a sending part and a receiving part;
a transmitting part configured to complete the construction of the test frame and transmit the test frame; the system comprises a test frame data storage circuit, a frame interval control circuit, a burst control circuit, a time control circuit, an address control circuit, a sending state machine circuit, a time mark sequence number inserting circuit, a sending sequence number and time mark generating circuit, a sending time mark latching circuit, a verification inserting circuit and an output circuit;
a test frame data storage circuit configured to store frame data defined by the test frame;
a frame interval control circuit configured to control an interval time period between each frame;
a burst control circuit configured to control the number of consecutive transmission frames;
a time control circuit configured to control a transmission duration of the test frame;
the address control circuit is configured to perform multi-port RFC2544 test, and automatically insert the MAC destination address, the IP destination address and the channel identification number of a port which needs to be reached by a test frame into the test frame;
a transmit state machine circuit configured to generate a test frame;
a time stamp sequence number insertion circuit configured to insert a sequence number of a currently transmitted frame and a time stamp into the currently transmitted frame;
a transmission sequence number and time mark generating circuit for generating a transmission sequence number and a time mark, which are inserted into the transmission frame by using the time mark sequence number inserting circuit;
a transmission time mark latch circuit configured to test the system recovery time, latch the last time mark when the test period is finished according to the overload rate, and then retransmit the test frame according to the normal rate for the sum of the test period time and the threshold time;
check insertion circuitry configured to insert the calculated CRC32 check value into the last four byte positions of the frame;
the output circuit is configured to transmit the entire test frame;
a receiving part configured to complete the reception, identification and measurement of each parameter of the test frame; the device comprises an input circuit, a test frame identification circuit, a test frame error detection circuit, a sending time mark extraction circuit, a receiving time mark latch circuit, a serial number extraction circuit, a test frame counting circuit, a pseudo-random sequence extraction circuit, a reset time test circuit, a time delay test circuit, a recovery time test circuit, a packet loss rate test circuit, a throughput test circuit, an error code test circuit and a test result memory;
an input circuit configured to receive and process Ethernet frames arriving at a port, including test frames and non-test frames;
the test frame identification circuit is configured to continuously detect the test frame mark, latch the length byte of the test frame mark into a RAM, and judge whether the length of the actually detected test frame is consistent with the latched length or not when the frame is finished;
the test frame error detection circuit is configured to perform error detection on the identified test frame, detect whether the test frame verification is correct or not, if not, directly discard the test frame verification, and do not perform the following operation any more;
a transmit time stamp extraction circuit configured to extract a transmit time stamp in the valid time stamp test frame;
a receiving time scale latch circuit configured to latch arrival times of all the test frames;
a sequence number extraction circuit configured to extract a transmission sequence number in the test frame;
a test frame counting circuit configured to count the number of all valid time scale test frames for calculating an average interval time, i.e., a jitter value;
the pseudo-random sequence extraction circuit is configured to strip out pseudo-random sequence data from the received test frame, and send the pseudo-random sequence data to the error code test circuit for error code test;
the reset time test circuit is configured to continuously latch arrival moments of two adjacent lost frames, and the difference value of the arrival moments is the system reset time;
the time delay test circuit is configured to continuously count the delay time of all time delay test frames and latch the maximum delay time and the minimum delay time;
the recovery time testing circuit is configured to latch the time of a time delay testing frame which arrives when the time exceeds a time threshold after the frame is lost, and subtract the time with a sending time mark latched by a sender to obtain the system recovery time;
the packet loss rate testing circuit is configured to count the number of the testing frames received after the testing is started, compare the number with the sent frame data and calculate the packet loss rate;
the throughput testing circuit is configured to count the maximum number of testing frames received in unit time after the testing is started, compare the maximum number of testing frames with the sent frame data and calculate the throughput;
the error code testing circuit is configured to carry out bit synchronization on the pseudo-random sequence shared from the testing frame and the pseudo-random sequence generated by the receiving end, detect errors and calculate an error rate;
a test result storage configured to store all test results;
the above definition is suitable for the test frame format of all parameter tests, and the types of the test frames are reduced;
the device is suitable for testing the transmission performance of the Ethernet with the speed of less than 10Gbps, can test all parameters of the transmission performance of the network, including jitter, reset time, time delay, recovery time, packet loss rate, throughput, error codes and bit error rate at one time, and shortens the test time.
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| CN103078767A (en) * | 2012-12-31 | 2013-05-01 | 中国电子科技集团公司第四十一研究所 | Method and device for testing throughput of WAN (Wide Area Network) at single port and at full wire speed |
| CN106375161A (en) * | 2016-12-06 | 2017-02-01 | 中国电子科技集团公司第四十研究所 | 10-gigabit Ethernet tester |
| CN107241238A (en) * | 2017-06-09 | 2017-10-10 | 中国电子科技集团公司第四十研究所 | A kind of network testing device of hand-held 10,000,000,000 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103078767A (en) * | 2012-12-31 | 2013-05-01 | 中国电子科技集团公司第四十一研究所 | Method and device for testing throughput of WAN (Wide Area Network) at single port and at full wire speed |
| CN106375161A (en) * | 2016-12-06 | 2017-02-01 | 中国电子科技集团公司第四十研究所 | 10-gigabit Ethernet tester |
| CN107241238A (en) * | 2017-06-09 | 2017-10-10 | 中国电子科技集团公司第四十研究所 | A kind of network testing device of hand-held 10,000,000,000 |
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