CN107680032A - A kind of image gradation data piecemeal storage method - Google Patents
A kind of image gradation data piecemeal storage method Download PDFInfo
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- CN107680032A CN107680032A CN201710693908.9A CN201710693908A CN107680032A CN 107680032 A CN107680032 A CN 107680032A CN 201710693908 A CN201710693908 A CN 201710693908A CN 107680032 A CN107680032 A CN 107680032A
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Abstract
The present invention relates to a kind of image gradation data piecemeal storage method, including：The first sub- memory space, the second sub- memory space are divided the memory into, the first sub- memory space, the second sub- memory space include multiple bit plane spaces；Serioparallel exchange is carried out to current image frame data to be stored, with matched data bus bit wide；Bit plane space corresponding to the frame data to the first sub- memory space of the serioparallel exchange is write successively, and/or is read the previous frame data stored in bit plane space corresponding to the second sub- memory space and exported；Wherein, the number in institute's bit planes space determines that the first sub- memory space is identical with the second sub- storage size according to image intensity value bit wide to be stored.Input of the invention in data solves the problems, such as that the utilization rate of data storage bandwidth in DMD real-time displays is low by the scheme for data being carried out with serioparallel exchange, design piecemeal stores.
Description
Technical field
The invention belongs to field of data storage, and in particular to a kind of image gradation data piecemeal storage method.
Background technology
It is synchronously dynamic that high frame frequency and high resolution is carried out in DMD (Digital Micromirror Device DMDs)
In state display system, to be related to the problems such as form conversion of image is with DMD gray modulations.Enter row format conversion to image with regard to phase
It is exactly inevitably to need to delay data during data recombination when in once being recombinated to view data
Deposit.How timely data to be cached and exported, be a very crucial technological difficulties all the time.
In the prior art, typically global storage mode is used.Specifically, using image data amount as XGA (Extended
Graphics Array XGAs)@200Hz, image intensity value bit wide 8bit, the image of resolution ratio 1024 × 768 are deposited
Store up exemplified by during external memory storage is the KTL-TP667 DDR2 sdram memory bar of Kingston companies.
, it is necessary to which what is obtained is the data of bit plane form when DMD carries out data loading, and DDR2 SDRAM
(Double Data Rate 2Synchronous Dynamic Random Access Memory, double data rate 2 are synchronous dynamic
State random access memory) read operation be directed to address, often read an address date can all obtain a DQ [63:0].
DQ[63:0] 64bit data are had altogether, but system is not to be all required for, so data selection must be carried out.Such as carry out
When bit plane 0 loads, the DQ [63 that reads:0] there was only DQ [0], DQ [8], DQ [16], DQ [24], DQ [32], DQ in
[40], DQ [48], DQ [56] belong to preceding 8 pixels of bit plane 0, and remaining is all the data of other 7 bit planes.For it
There is also same case for his bit plane loading., it is necessary to which the storage to whole two field picture is empty within a complete PWM algorithm time
Between read 8 times, respectively obtain 8 bit planes.It is as shown in Figure 1 the storage mode of data in the memory space of whole two field picture, it is cloudy
What shadow represented is the data of bit plane 0.
In the frame time that image is shown, need to complete write-once and 8 read operations for DDR2 SDRAM,
But because DMD 8 bit planes are not averagely continuously to be loaded in a frame time one by one, DMD adds every time
The time for carrying a bit plane is 30.72us, and this just needs whole frame figure of the system by DDR2 SDRAM within 30.72us time
98304 addresses of the memory space of picture are read one time, can just obtain the data of a bit plane.Due to being read in memory
Cheng Zhong, 56bit invalid data in the data obtained every time be present, this has resulted in the significant wastage of data transfer bandwidth, real
The effective rate of utilization of data transfer bandwidth only has 12.5% on border.In this under mode of operation, to meet that DMD loads demand,
The transmission rate for needing DDR2 SDRAM is 98304 ÷ 30.72us=3.2GHz, and this is beyond DDR2 SDRAM transmission
Rate-limit, even if the DDR4SDRAM of highest ranking message transmission rate also is difficult to meet demand at present.
Therefore, although the storage mode logic of prior art is simple, to DDR2 SDRAM when digital independent
Transmission bandwidth utilization rate is too low, can not realize high frame per second, the storage of high-resolution image.
The content of the invention
It is high the invention provides a kind of bandwidth availability ratio in order to solve the above-mentioned problems in the prior art, Neng Goushi
Existing high frame per second, the image gradation data piecemeal storage method of high-definition picture storage.
In order to realize foregoing invention purpose, the technical solution adopted by the present invention is：
A kind of image gradation data piecemeal storage method, including：
The first sub- memory space, the second sub- memory space are divided the memory into, the first sub- memory space, the second son are deposited
Storage space includes multiple bit plane spaces；
Serioparallel exchange is carried out to current image frame data to be stored, with matched data bus bit wide；
Bit plane space corresponding to the frame data to the first sub- memory space of the serioparallel exchange is write successively, and/or is read
The previous frame data stored in bit plane space corresponding to the second sub- memory space are taken to be exported；
Wherein, the number in institute's bit planes space determines according to image intensity value bit wide to be stored, first son
Memory space is identical with the second sub- storage size.
Further, serioparallel exchange is carried out to current image frame data to be stored, specifically included：To current to be stored
Image frame data uses two-stage FIFO cascade system serioparallel exchanges.
Further, institute's bit planes space includes several memory cell；
Wherein, the data volume of each memory cell storage determines according to data/address bus bit wide.
Further, the number of memory cells in each institute's bit planes space is determined by the resolution ratio of image.
Input of the invention in data solves by the scheme for data being carried out with serioparallel exchange, design piecemeal stores
The problem of utilization rate of data storage bandwidth is low in DMD real-time displays.
Brief description of the drawings
Fig. 1 show existing data storage method schematic diagram.
Fig. 2 show the image gradation data piecemeal storage method flow chart of the present invention.
Fig. 3 show the piecemeal memory space logical partitioning schematic diagram in an embodiment of the invention.
Piecemeal that Fig. 4 is shown in an embodiment of the invention is data cached to flow to block diagram.
Embodiment
With reference to embodiment, the present invention is described in further detail.But this should not be interpreted as to the present invention
The scope of above-mentioned theme is only limitted to following embodiment, all models that the present invention is belonged to based on the technology that present invention is realized
Enclose.
Embodiment one
Fig. 2 show the image gradation data piecemeal storage method flow chart of the present invention, including：
The first sub- memory space, the second sub- memory space are divided the memory into, the first sub- memory space, the second son are deposited
Storage space includes multiple bit plane spaces；
Serioparallel exchange is carried out to current image frame data to be stored, with matched data bus bit wide；
Bit plane space corresponding to the frame data to the first sub- memory space of the serioparallel exchange is write successively, and/or is read
The previous frame data stored in bit plane space corresponding to the second sub- memory space are taken to be exported；
Wherein, the number in institute's bit planes space determines according to image intensity value bit wide to be stored, first son
Memory space is identical with the second sub- storage size.Serioparallel exchange, specific bag are carried out to current image frame data to be stored
Include：Two-stage FIFO cascade system serioparallel exchanges are used to current image frame data to be stored.If institute's bit planes space includes
Dry memory cell；Wherein, the data volume of each memory cell storage determines according to data/address bus bit wide.It is each described
The number of memory cells in bit plane space is determined by the resolution ratio of image.
In a detailed embodiment, the present invention is using image data amount as XGA@200Hz, image intensity value bit wide
8bit, the image of resolution ratio 1024 × 768 are stored in the KTL-TP667 DDR2 that external memory storage is Kingston companies
Exemplified by sdram memory bar.
The a width of 64bit of data bus bit of data is transmitted between the model memory bar and FPGA, in semiduplex Working mould
Under formula, 64bit data can be read or write every time.Include positive and negative two rank on memory bar, each rank is by 8
The storage particle composition of ELPIDA companies, each specification for storing particle is 16M × 8bit.Pass through the level of 16 storage particles
Connection, the DDR2 SDRAM of composition specification is 32M × 64bit.Rank1 is made up of storage particle DO-D7, and Rank2 is by storage
On grain D8-D15 compositions, each data/address bus 8bit for storing particle, 8 particles, which are connected in parallel, forms 64bit.
Therefore, in order to make full use of DDR2 SDRAM readwrite bandwidth, before data write-in, for the number after fractionation
According to, need also exist for carry out serioparallel exchange, continuous 64 1bit data are merged into a 64bit data and carry out depositing read operation.
In order to ensure the continuity of data processing, whole memory is divided into two sub-spaces by the present invention, and data write to subspace 1
During, the previous frame data of subspace 2 are read, during data write to subspace 2 in turn, read subspace 1
Previous frame data, two sub-spaces alternately read-write ensure data processing continuity.It is being divided into 8 again inside per sub-spaces
Bit plane space.One bit plane includes 1024 × 768 × 1bit data, and a memory cell in bit plane space can deposit
64bit data are put, so a bit plane space comprises at least 12288 memory cell.Deposited referring specifically to the piecemeal shown in Fig. 3
DDR2 SDRAM memory space division schematic diagram in the case of storage.
During the peak of DDR2 SDRAM data transfers is equally the loading of DMD data, by the way of piecemeal storage,
Due to initial data has been carried out into segmentation restructuring so that read what DDR2 SDRAM were obtained every time when DMD data load
It is valid data entirely, it is only necessary to read 12288 addresses and can be obtained by a complete bit plane.DDR2 during this
SDRAM message transmission rate is 12288 ÷ 30.72us=400MHz.This speed is less than in DDR2 SDRAM data transfers
Limit, so although the mode of piecemeal storage implements, logic is complicated still can greatly to reduce DDR2 SDRAM data transfers
Bandwidth pressure.
In memory operation, referring to Fig. 4, each difference of the 8bit data transmitted first to the host computer received
Serioparallel exchange is carried out, this process can be realized with RAM.Because RAM conversion ratio at most can be to 1:32, so making herein
The mode cascaded with two-stage FIFO, every grade of RAM conversion ratio respectively 1:16 and 1:4, changing for two-stage cascade is compared into 1:64.
DDR2 SDRAM should be sent into by the data of serioparallel exchange, ping-pong operation selecting unit first can be selected subspace,
The idle subspace of selection deposits into data, and 8 in selected subspace bit plane space can be accessed one by one, divides 8
Secondary 8 64bit data for obtaining first time serioparallel exchange are sequentially stored into corresponding bit plane space.Current frame data is stored in
While DDR2 SDRAM, another sub-spaces also equally also have one in the output for coordinating DMD loadings to carry out bit plane, output end
Individual ping-pong operation selecting unit, the subspace that it can select to be updated over data and stopped inputting are exported, every time output
The data in one bit plane space give DMD, within 8 bit plane load times of a two field picture, from bit plane space 0 in place
Plane space 7 is run through successively.
Input of the invention in data solves by the scheme for data being carried out with serioparallel exchange, design piecemeal stores
The problem of utilization rate of data storage bandwidth is low in DMD real-time displays.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
The present invention is described in detail with reference to the foregoing embodiments, it will be understood by those within the art that：It still may be used
To be modified to the technical scheme described in foregoing embodiments, or equivalent substitution is carried out to which part technical characteristic；
And these modification or replace, do not make appropriate technical solution essence depart from various embodiments of the present invention technical scheme spirit and
Scope.
Claims (4)
- A kind of 1. image gradation data piecemeal storage method, it is characterised in that including：The first sub- memory space, the second sub- memory space are divided the memory into, the first sub- memory space, the second son storage are empty Between include multiple bit plane spaces；Serioparallel exchange is carried out to current image frame data to be stored, with matched data bus bit wide；Write bit plane space corresponding to the frame data to the first sub- memory space of the serioparallel exchange successively, and/or read the The previous frame data stored in bit plane space corresponding to two sub- memory spaces are exported；Wherein, the number in institute's bit planes space determines according to image intensity value bit wide to be stored, the first son storage Space is identical with the second sub- storage size.
- 2. image gradation data piecemeal storage method according to claim 1, it is characterised in that to current figure to be stored As frame data progress serioparallel exchange, specifically include：Two-stage FIFO cascade system strings are used to current image frame data to be stored And change.
- 3. image gradation data piecemeal storage method according to claim 1, it is characterised in that wrap in institute's bit planes space Include several memory cell；Wherein, the data volume of each memory cell storage determines according to data/address bus bit wide.
- 4. image gradation data piecemeal storage method according to claim 1, it is characterised in that each institute bit planes are empty Between number of memory cells determined by the resolution ratio of image.
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Cited By (1)
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Application publication date: 20180209 |