CN107678894B - Memory test method, device and system - Google Patents
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Abstract
The embodiment of the invention provides a memory test method, a device and a system, which comprises the steps of obtaining the type of a disk array; determining a read-write rule of the disk array according to the type of the disk array; and reading and writing the disk array according to the reading and writing rule, wherein the disk array reads and writes data through the memory cache to be tested in the reading and writing process. The pressure test of the memory is indirectly realized through the read-write operation of the disk array, and the disk array is formed by a plurality of hard disks, so that the redundancy is very high, the system breakdown is prevented, and the smooth performance of the pressure test is effectively ensured.
Description
Technical Field
The present invention relates to the field of computer testing technologies, and in particular, to a method, an apparatus, and a system for testing a memory.
Background
The memory is an important part in the computer and is responsible for caching data information of the processor or the hard disk. The pressure test of the memory is the key for verifying the memory quality and further ensuring the normal operation of the computer.
At present, in order to perform a stress test on the memory, a memory test tool is generally operated on a computer, and a processor occupies a system memory with a high calculation amount, so as to implement the stress test on the memory. However, through research, the inventors found that, during the execution of the memory stress test, the system is down due to the high load of the processor, so that the memory stress test cannot be performed smoothly.
Therefore, how to provide a testing method for testing the memory pressure is a technical problem that needs to be solved urgently by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned shortcomings in the prior art, an object of the present invention is to provide a method, an apparatus and a system for testing a memory to solve the problem of memory stress test in the prior art.
To achieve the above and other related objects, according to a first aspect of the present invention, an embodiment of the present invention provides a memory testing method, including:
acquiring the type of a disk array;
determining a read-write rule of the disk array according to the type of the disk array;
and reading and writing the disk array according to the reading and writing rule, wherein the disk array reads and writes data through the memory cache to be tested in the reading and writing process.
Optionally, the determining, according to the type of the disk array, a read-write rule of the disk array includes:
when the type of the disk array comprises RAID5, RAID6, RAID50 and RAID60, determining to perform read operation on the disk array;
the reading and writing the disk array according to the reading and writing rule comprises:
and performing read operation on the disk array.
Optionally, the determining, according to the type of the disk array, a read-write rule of the disk array includes:
when the type of the disk array comprises RAID0, RAID1, RAID00 and RAID10, determining to write to the disk array;
the reading and writing the disk array according to the reading and writing rule comprises:
and writing the disk array.
Optionally, performing a read operation on the disk array includes:
sequentially reading data with the size corresponding to the first block set from the continuous storage space of the disk array;
and/or the presence of a gas in the gas,
sequentially reading data with the size corresponding to the first block set from a random storage space of the disk array;
the first block set comprises a plurality of block parameters which are arranged according to the size sequence, or the first block set comprises a plurality of block parameters which are arranged randomly; the block parameter of the first set of blocks is used to describe the size of the read data.
The memory test method of claim 3, wherein writing to the disk array comprises:
sequentially writing data with the size corresponding to the second block set into the continuous storage space of the disk array;
and/or the presence of a gas in the gas,
sequentially writing data with the size corresponding to the second block set into a random storage space of the disk array;
the second block set comprises a plurality of block parameters arranged according to a size sequence, or the first block set comprises a plurality of block parameters arranged randomly, and the block parameters in the second block set are used for describing the size of the written data.
Optionally, the method further comprises:
and when the error checking and correcting information returned by the memory interface is acquired, determining that the memory is abnormal.
According to a second aspect of the present invention, an embodiment of the present invention further provides a memory test apparatus, including:
the acquisition module is used for acquiring the type of the disk array;
the read-write rule determining module is used for determining the read-write rule of the disk array according to the type of the disk array;
and the read-write module is used for reading and writing the disk array according to the read-write rule, and the disk array reads and writes data through the memory cache in the read-write process.
Optionally, the read-write rule determining module is configured to determine to perform a read operation on the disk array when the type of the disk array includes RAID5, RAID6, RAID50, and RAID60, or determine to perform a write operation on the disk array when the type of the disk array includes RAID0, RAID1, RAID00, and RAID 10;
the read-write module is used for performing read operation on the disk array when the read-write rule determining module determines that the read-write rule is read operation; or, when the read-write rule determining module determines that the read-write rule is write operation, performing write operation on the disk array.
Optionally, when the read-write rule determining module determines that the read-write rule is a read operation, the read-write module is configured to,
sequentially reading data with the size corresponding to the first block set from the continuous storage space of the disk array;
and/or the presence of a gas in the gas,
sequentially reading data with the size corresponding to the first block set from a random storage space of the disk array;
the first block set comprises a plurality of block parameters which are arranged according to the size sequence, or the first block set comprises a plurality of block parameters which are arranged randomly; the block parameter of the first set of blocks is used to describe the size of read data;
when the read-write rule determining module determines that the read-write rule is write operation, the read-write module is used for sequentially writing data with the size corresponding to the second block set into the continuous storage space of the disk array;
and/or the presence of a gas in the gas,
sequentially writing data with the size corresponding to the second block set into a random storage space of the disk array;
the second block set comprises a plurality of block parameters arranged according to a size sequence, or the first block set comprises a plurality of block parameters arranged randomly, and the block parameters in the second block set are used for describing the size of the written data.
According to a third aspect of the present invention, an embodiment of the present invention further provides a memory test system, including a processor, a RAID controller, and a hard disk, where:
the RAID controller is in communication connection with the hard disk and is used for controlling the establishment of a disk array;
the RAID controller is also in communication connection with the memory interface and is used for caching read-write data through a memory to be tested in the process of controlling the read-write of the disk array;
the processor is in communication connection with the RAID controller and is used for acquiring the type of the disk array from the RAID controller; determining a read-write rule of the disk array according to the type of the disk array; and sending the read-write rule to the RAID controller so that the RAID controller controls the read-write operation of the disk array.
As described above, the memory testing method, device and system provided in the embodiments of the present invention have the following advantages: acquiring the type of a disk array; determining a read-write rule of the disk array according to the type of the disk array; and reading and writing the disk array according to the reading and writing rule, wherein the disk array reads and writes data through the memory cache to be tested in the reading and writing process. The pressure test of the memory is indirectly realized through the read-write operation of the disk array, and the disk array is formed by a plurality of hard disks, so that the redundancy is very high, the system breakdown is prevented, and the smooth performance of the pressure test is effectively ensured.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a schematic flow chart illustrating a memory testing method according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a memory test apparatus according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a memory test system according to an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Please refer to fig. 1 to 3. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
In the embodiment of the invention, in order to perform pressure test on the memory, a RAID controller and a plurality of hard disks are required to be used for constructing a disk array; moreover, the RAID controller may be connected to the memory to be tested through an interface having an ECC (Error correction Code, abbreviated as Error check and correction) function. ECCs can be further classified as Single-Bit ECCs and Multi-Bit ECCs; and in the read-write process, error checking and correcting are carried out on data in the memory particles, when Single-Bit ECC occurs, the memory can be automatically repaired, but when Multi-Bit ECC occurs, the data cannot be repaired, and an error is reported. The embodiment of the present invention performs a pressure test on the memory based on the test architecture, but it should be noted that any other test structure may also be used to perform the pressure test in the embodiment of the present invention, and the embodiment of the present invention is not limited thereto.
Fig. 1 is a schematic flow chart of a memory testing method according to an embodiment of the present invention. As shown in fig. 1, the method comprises the steps of:
step S101: and acquiring the type of the disk array.
In particular, the type of disk array is obtained from configuration information of the RAID controller. Typical disk array types may include RAID0, RAID1, RAID5, RAID6, RAID00, RAID10, RAID50, and RAID 60. Each type of disk array has corresponding characteristics; among them, a RAID0 type disk array can provide high data throughput for large files, a RAID1 type disk array is suitable for small data banks or other environments requiring fault tolerance but small capacity, a RAID5 type disk array has a high read request rate but a low random write request rate, a RAID6 type disk array has a high read request rate but a low random or small block write rate, a RAID00 type disk array provides high data throughput, particularly for large files, a RAID10 type disk array can provide high data transfer rate and full data redundancy, a RAID50 type disk array provides high data throughput, data redundancy and very good performance, and a RAID60 type disk array has a very high read request rate but a low write request rate.
Step S102: and determining the read-write rule of the disk array according to the type of the disk array.
Because different types of disk arrays have different characteristics, the read-write rule of the disk array is determined according to the type of the disk array determined in step S101 and further according to the type of the disk array.
In the first implementation case, since the disk arrays RAID5, RAID6, RAID50 and RAID60 are more suitable for read operations, when the types of the disk arrays include RAID5, RAID6, RAID50 and RAID60, it is determined that a read operation is performed on the disk arrays.
In the second implementation case, since RAID0, RAID1, RAID00, and RAID10 are more suitable for write operations, when the types of disk arrays include RAID0, RAID1, RAID00, and RAID10, it is determined that a write operation is performed on the disk arrays.
Step S103: and reading and writing the disk array according to the reading and writing rule, wherein the disk array reads and writes data through the memory cache to be tested in the reading and writing process.
When it is determined that a read operation needs to be performed on the disk array, in a first implementation case, data of a size corresponding to the first block set is sequentially read from a continuous storage space of the disk array. In particular implementations, an exemplary embodiment may use the IOMeter to read from a disk array in a sequential read manner.
In the second implementation case, data of a size corresponding to the first block set is sequentially read from a random storage space of the disk array. In particular implementations, an exemplary embodiment may use the IOMeter to read from a disk array in a random read manner.
In an embodiment of the present invention, the first block set includes a plurality of block parameters arranged in a size order, and in an exemplary embodiment, the first block set may be {512b, 1k, 2k, 4k, 8k, 16k, 32k, 64k, 128k, 256k, 512k, 1M, 2M }, and the first block set includes 13 block parameters arranged in a small-to-large order, so that when a read operation is performed on the disk array according to the first block set, 13 data blocks with data sizes corresponding to the sequentially arranged block parameters are read.
Or, the first block set comprises a plurality of randomly arranged block parameters; the block parameter of the first set of blocks is used to describe the size of the read data. In an exemplary embodiment, the first set of blocks may be {512b, 2k, 2M, 256k, 8k, 16k, 64k, 128k, 32k, 1k, 512k, 1M }, and the first set of blocks includes 13 randomly arranged block parameters, such that when a read operation is performed on the disk array according to the first set of blocks, sequential random block parameters are read corresponding to data size of data blocks.
When it is determined that a write operation needs to be performed on the disk array, in the first implementation case, data of a size corresponding to the second block set is sequentially written into a continuous storage space of the disk array.
In the second implementation case, data of the size corresponding to the second block set is sequentially written into the random storage space of the disk array.
In the embodiment of the present invention, the second block set includes a plurality of block parameters arranged in a size order, or the first block set includes a plurality of block parameters arranged randomly, and the block parameters in the second block set are used to describe the size of the write data. The same points of the embodiment of the present invention as those in the case of performing the write operation on the disk array described above can be referred to the description of the embodiment described above, and are not described herein again.
Therefore, through the first block set and the second block set which are configured and the rules of sequential reading, sequential writing, random reading and random writing, the disk array can simulate the pressure use condition of the memory under the real condition, so that the precision at the moment is improved
In the process of reading and writing the disk array, the RAID controller may also be configured, and in an exemplary embodiment, three parameters, namely Always Read Ahead in Read Policy, Always Write Back in Write Policy (if a battery is provided), and Cached in I/O Policy are used, so that the memory particles are used when the RAID card reads or writes data, and selecting the three parameters when the RAID array is built effectively applies pressure to the memory when the RAID card reads or writes data, so as to achieve the purpose of pressure test.
In order to determine whether the memory is abnormal, the determination can be made by checking and correcting the error information. Specifically, when the error checking and correcting information returned by the memory interface is acquired and the error checking and correcting information is Multi-Bit ECC, it is determined that the memory is abnormal.
As can be seen from the description of the above embodiment, the memory testing method provided in the embodiment of the present invention includes obtaining the type of the disk array; determining a read-write rule of the disk array according to the type of the disk array; and reading and writing the disk array according to the reading and writing rule, wherein the disk array reads and writes data through the memory cache to be tested in the reading and writing process. The pressure test of the memory is indirectly realized through the read-write operation of the disk array, and the disk array is formed by a plurality of hard disks, so that the redundancy is very high, the system breakdown is prevented, and the smooth performance of the pressure test is effectively ensured.
Through the above description of the method embodiments, those skilled in the art can clearly understand that the present invention can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: various media that can store program codes, such as Read Only Memory (ROM), Random Access Memory (RAM), magnetic or optical disks, and so on.
Corresponding to the embodiment of the memory test method provided by the invention, the invention also provides a memory test device.
Referring to fig. 2, a schematic structural diagram of a memory test apparatus according to an embodiment of the present invention is shown in fig. 2, where the apparatus includes:
an obtaining module 11, configured to obtain a type of a disk array;
a read-write rule determining module 12, configured to determine a read-write rule of the disk array according to the type of the disk array;
and the read-write module 13 is configured to read and write the disk array according to the read-write rule, where the disk array reads and writes data through a memory cache in the read-write process.
In an exemplary embodiment, the read-write rule determining module 12 is configured to determine to perform a read operation on the disk array when the type of the disk array includes RAID5, RAID6, RAID50, and RAID60, or determine to perform a write operation on the disk array when the type of the disk array includes RAID0, RAID1, RAID00, and RAID 10.
The read-write module 13 is configured to perform a read operation on the disk array when the read-write rule determining module determines that the read-write rule is a read operation; or, when the read-write rule determining module determines that the read-write rule is write operation, performing write operation on the disk array.
In an exemplary embodiment, in a first implementation case, when the read-write rule determining module determines that the read-write rule is a read operation, the read-write module is configured to,
sequentially reading data with the size corresponding to the first block set from the continuous storage space of the disk array;
and/or the presence of a gas in the gas,
sequentially reading data with the size corresponding to the first block set from a random storage space of the disk array;
the first block set comprises a plurality of block parameters which are arranged according to the size sequence, or the first block set comprises a plurality of block parameters which are arranged randomly; the block parameter of the first set of blocks is used to describe the size of the read data.
Under a second implementation condition, when the read-write rule determining module determines that the read-write rule is write operation, the read-write module is configured to sequentially write data of a size corresponding to the second block set into a continuous storage space of the disk array;
and/or the presence of a gas in the gas,
sequentially writing data with the size corresponding to the second block set into a random storage space of the disk array;
the second block set comprises a plurality of block parameters arranged according to a size sequence, or the first block set comprises a plurality of block parameters arranged randomly, and the block parameters in the second block set are used for describing the size of the written data.
Fig. 3 is a schematic structural diagram of a memory test system according to an embodiment of the present invention. As shown in fig. 3, the system includes a CPU210, a RAID controller 220, and a hard disk 230.
The RAID controller 220 may be communicatively connected to the hard disk 230 through a backplane, and is configured to control establishment of a disk array.
The RAID controller 220 is also in communication connection with a memory interface, which may be connected to a memory 270 to be tested, and is configured to cache read and write data through the memory to be tested in the process of controlling the read and write of the disk array; in a preferred embodiment, the memory interface may support ECC functionality.
The processor 210 may be communicatively connected to the RAID controller 220 through a PCIE interface 240, and is configured to acquire the type of the disk array from the RAID controller 210; determining a read-write rule of the disk array according to the type of the disk array; and sending the read-write rules to the RAID controller 210, so that the RAID controller 210 controls the read-write operations of the disk array.
In addition, the RAID controller 220 may also be communicatively connected to the peripheral device 260 through a bus, where the peripheral device 260 may include a Flash ROM, an NVSRAM (nonvolatile static random access memory, chinese), a UART (universal asynchronous receiver/transmitter, chinese), and the like; the Flash ROM is used for storing a Flash memory of the RAID card firmware, and the RAID card firmware can be erased or written in the Flash ROM by using an instrument; the NVSRAM is used for storing log files of the RAID card and the like; and collecting serial port printing information of the RAID card or sending a serial port debugging command through the UART interface. The bus may use I2C (Inter-Integrated Circuit, chinese: Integrated Circuit bus), may be used to obtain the temperature of the RAID controller, and the like.
The CPU210 in the embodiment of the present invention may be configured to execute the memory test method described in the above method embodiment, which has corresponding technical effects, and is not described herein again.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the embodiment
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for apparatus or system embodiments, since they are substantially similar to method embodiments, they are described in relative terms, as long as they are described in partial descriptions of method embodiments. The above-described embodiments of the apparatus and system are merely illustrative, and the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (6)
1. A memory test method is characterized by comprising the following steps:
acquiring the type of a disk array;
determining a read-write rule of the disk array according to the type of the disk array, wherein when the type of the disk array comprises RAID5, RAID6, RAID50 and RAID60, the read operation of the disk array is determined; or when the types of the disk arrays comprise RAID0, RAID1, RAID00 and RAID10, determining to write the disk arrays;
reading and writing the disk array according to the reading and writing rules, wherein when the type of the disk array comprises RAID5, RAID6, RAID50 and RAID60, reading operation is carried out on the disk array; or when the types of the disk arrays comprise RAID0, RAID1, RAID00 and RAID10, performing write operation on the disk arrays; and the disk array reads and writes data through the memory cache to be tested in the reading and writing process.
2. The memory test method of claim 1, wherein writing to the disk array comprises:
sequentially writing data with the size corresponding to the second block set into the continuous storage space of the disk array;
and/or the presence of a gas in the gas,
sequentially writing data with the size corresponding to the second block set into a random storage space of the disk array;
the second block set comprises a plurality of block parameters arranged according to a size sequence, or the second block set comprises a plurality of block parameters arranged randomly, and the block parameters in the second block set are used for describing the size of the written data.
3. The memory test method of claim 1, further comprising:
and when the error checking and correcting information returned by the memory interface is acquired, determining that the memory is abnormal.
4. A memory test device, comprising:
the acquisition module is used for acquiring the type of the disk array;
the read-write rule determining module is used for determining the read-write rule of the disk array according to the type of the disk array, and comprises the steps of determining to perform read operation on the disk array when the type of the disk array comprises RAID5, RAID6, RAID50 and RAID60, or determining to perform write operation on the disk array when the type of the disk array comprises RAID0, RAID1, RAID00 and RAID 10;
the read-write module is used for reading and writing the disk array according to the read-write rule, and comprises the step of reading the disk array when the type of the disk array comprises RAID5, RAID6, RAID50 and RAID 60; or when the types of the disk arrays comprise RAID0, RAID1, RAID00 and RAID10, performing write operation on the disk arrays; and the disk array reads and writes data through the memory cache in the reading and writing process.
5. The memory test device of claim 4,
when the read-write rule determining module determines that the read-write rule is a read operation, the read-write module is used for,
sequentially reading data with the size corresponding to the first block set from the continuous storage space of the disk array;
and/or the presence of a gas in the gas,
sequentially reading data with the size corresponding to the first block set from a random storage space of the disk array;
the first block set comprises a plurality of block parameters which are arranged according to the size sequence, or the first block set comprises a plurality of block parameters which are arranged randomly; the block parameter of the first set of blocks is used to describe the size of read data;
when the read-write rule determining module determines that the read-write rule is write operation, the read-write module is used for sequentially writing data with the size corresponding to the second block set into the continuous storage space of the disk array;
and/or the presence of a gas in the gas,
sequentially writing data with the size corresponding to the second block set into a random storage space of the disk array;
the second block set comprises a plurality of block parameters arranged according to a size sequence, or the second block set comprises a plurality of block parameters arranged randomly, and the block parameters in the second block set are used for describing the size of the written data.
6. A memory test system is characterized by comprising a processor, a RAID controller and a hard disk, wherein:
the RAID controller is in communication connection with the hard disk and is used for controlling the establishment of a disk array;
the RAID controller is also in communication connection with the memory interface and is used for caching read-write data through a memory to be tested in the process of controlling the read-write of the disk array;
the processor is connected with the RAID controller address book and is used for acquiring the type of the disk array from the RAID controller; determining a read-write rule of the disk array according to the type of the disk array, wherein the read-write rule comprises determining to perform read operation on the disk array when the type of the disk array comprises RAID5, RAID6, RAID50 and RAID60, or determining to perform write operation on the disk array when the type of the disk array comprises RAID0, RAID1, RAID00 and RAID 10;
and sending the read-write rules to a RAID controller so that the RAID controller controls the read-write operation of the disk array, wherein the read operation is performed on the disk array when the type of the disk array comprises RAID5, RAID6, RAID50 and RAID 60; or when the types of the disk arrays comprise RAID0, RAID1, RAID00 and RAID10, writing is carried out on the disk arrays.
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| CN201710775290.0A CN107678894B (en) | 2017-08-31 | 2017-08-31 | Memory test method, device and system |
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| CN201710775290.0A CN107678894B (en) | 2017-08-31 | 2017-08-31 | Memory test method, device and system |
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