CN107659787A - A kind of ultra high-definition SDI display systems and its method - Google Patents
A kind of ultra high-definition SDI display systems and its method Download PDFInfo
- Publication number
- CN107659787A CN107659787A CN201710899772.7A CN201710899772A CN107659787A CN 107659787 A CN107659787 A CN 107659787A CN 201710899772 A CN201710899772 A CN 201710899772A CN 107659787 A CN107659787 A CN 107659787A
- Authority
- CN
- China
- Prior art keywords
- ultra high
- display
- signal
- definition
- sdi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/18—Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/265—Mixing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Controls And Circuits For Display Device (AREA)
Abstract
The present invention discloses a kind of ultra high-definition SDI display systems and its method,It includes the parallel SDI interfaces in 4 tunnels,FPGA,First internal memory,Central processing unit,Second internal memory and display,A high definition sdi signal is respectively connected to per road SDI interfaces,FPGA is connected by a balanced device respectively per road SDI interfaces,Balanced device is used to single-ended high definition sdi signal becoming differential signal,FPGA is used to 4 tunnel high definition sdi signals being spliced into ultra high-definition sdi signal,FPGA connects the first internal memory and central processing unit respectively,Central processing unit connects the second internal memory and display respectively,First internal memory is used for the high definition sdi signal for storing FPGA receptions,Second internal memory is used for the ultra high-definition sdi signal for storing FPGA splicing generations,Central processing unit is used for the display processing of ultra high-definition sdi signal,Display is used for the output display of ultra high-definition sdi signal.The present invention is spliced into ultra high-definition signal output by multichannel sdi signal and shown, simple in structure and low in cost.
Description
Technical field
The present invention relates to monitor display technology field, more particularly to a kind of ultra high-definition SDI display systems and its method.
Background technology
The development of science and technology preferably regards always in order to preferably serve the mankind in order to be obtained in TV, film viewing
Feel experience, 4k technologies are arisen at the historic moment.So-called 4k technologies, refer to that resolution ratio reaches 3840 × 2160 or 4096 × 2160, be high definition
（1920×1080/2048×1080）4 times, therefore also referred to as ultra high-definition.Along with the popularization and development of 4k technologies, 4k monitoring
The demand of device is also increasing.4k ultra high-definitions monitor resolution can reach 3840 × 2160（4k×2k）, therefore its image,
Video, which is shown, to be become apparent from, is fine and smooth so that 4k monitors commercially obtain numerous pursue.But 4k prisons in the market
All there is following defect for most of visual organ：1st, only all the way, input signal transmission range is small for the sdi signal of input, does not apply to
In the workplace for needing long range transmission signal, made troubles to work；2nd, input is believed using special Scaler chips
The scaling adjustment of signal resolution number is carried out, the complexity of hardware configuration layout is not only increased, also improves the cost of product；
3rd, using LVDS as screen interface, 4k signals are transferred on LCD, LVDS transmission 4k signals need more data line,
It is unfavorable for the lightening of product, and signal transmission rate is slow.4th, 4k monitors currently on the market are due to cost, technical elements
Problem, price is high, makes consumer hang back.
The content of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of ultra high-definition SDI display systems and its method.
The technical solution adopted by the present invention is：
A kind of ultra high-definition SDI display systems, it includes the parallel SDI interfaces in 4 tunnels, FPGA, the first internal memory, central processing unit,
Two internal memories and display, a high definition sdi signal is respectively connected to per road SDI interfaces, 4 road sdi signal input sequences are immutable；For
Correction transmission channel amplitude-frequency characteristic and phase-frequency characteristic, improve the antijamming capability of signal.Per road SDI interfaces difference
FPGA is connected by a balanced device, balanced device is used to single-ended high definition sdi signal becoming differential signal, and FPGA is used for 4 tunnels
High definition sdi signal is spliced into ultra high-definition sdi signal, and FPGA connects the first internal memory and central processing unit, central processing unit point respectively
The second internal memory and display are not connected, and the first internal memory is used for the high definition sdi signal for storing FPGA receptions, and the second internal memory is used to store
The ultra high-definition sdi signal of FPGA splicing generations, central processing unit are used for the display processing of ultra high-definition sdi signal, and display is used for
The output display of ultra high-definition sdi signal.
Further, the high definition sdi signal is 2K × 1K-sdi signal, the ultra high-definition sdi signal be 4K × 2K-
Sdi signal.
Further, ddr3 or ddr4 internal memories are saved as in first internal memory and second.
Further, the central processing unit connects display by eDP interfaces.
Further, the display is liquid crystal display.
The invention also discloses a kind of ultra high-definition SDI display methods, it comprises the following steps：
1）4 tunnel high definition sdi signals are inputted by the parallel SDI interfaces in 4 tunnels respectively；
2）The single-ended high definition sdi signal in every road is become into differential signal by balanced device and exported to FPGA；
3）4 tunnel high definition sdi signals of reception are stored respectively in the first internal memory by FPGA；
4）FPGA reads 4 tunnel high definition sdi signal splicing synthesis ultra high-definition sdi signals from the first internal memory, and exports to centre
Manage device；
5）Central processing unit receives ultra high-definition sdi signal and is stored in the second internal memory；
6）Central processing unit carries out display processing to ultra high-definition sdi signal for the specification of display, and is exported and shown by display
Show.
Further, step 4）Middle FPGA is based on 2-sample the or Square division in SMPTE425-5 standards
4 tunnel high definition sdi signal splicings are synthesized ultra high-definition sdi signals by mode.
Further, step 6）Central processing unit ultra high-definition sdi signal is processed into and the screen physics of display point
Resolution identical output signal.
Further, step 6）Central processing unit use the Scaler of internal generation to zoom to ultra high-definition sdi signal
The screen physical resolution identical output signal of display.
Further, step 6）Central processing unit ultra high-definition sdi signal is exported to display using eDP interfaces.
The present invention uses above technical scheme, has as follows a little：The input mode of 1.SDI signals is the 2k of 4 tunnel independences
× 1k-sdi signal, compared with directly inputting the mode of 1 road 4k × 2k-sdi signal, the distance of signal transmission is farther, can
Preferably it is applied to various occasions, hardware, which is realized, to be also more prone to.2. with the 2-sample in SMPTE425-5 standards or
Square division modes are realized synthesizes 1 road 4k × 2k-SDI letters by 2k × 1k-sdi signal of 4 tunnel independences of input
Number mode, realize and 4k images shown on LCD, greatly reduce the cost of product so that 4k monitor prices, which no longer make, to disappear
Expense person hangs back.3. pair all pass through equalizer processes per the 2k × 1k-sdi signal that inputs all the way so that input it is single-ended
Sdi signal becomes differential signal, improves the antijamming capability of signal；Reduce the hunting range of signal, be advantageous to rear end
Identification when managing signal to signal, improves and signal sequence is accurately positioned.4. used for the resolution ratio scaling of signal in CPU
The Scaler of portion's generation is realized, rather than the special Scaler chips outside use, be not only simplify the structure of hardware, is also reduced
Cost.5. substituting LVDS interface with eDP interfaces, eDP interfaces have following quite obvious advantage in ultra high-definition is shown：It is micro-
Packet structure, more data can be realized（1-4 is to data wire）While transmit；Larger transmission rate, up to 21.6Gbps；
Less size, be advantageous to the lightening of product, carry product more convenient；It is more succinct without LVDS change-over circuits, circuit；
Less EMI, and there is powerful defencive function.
Brief description of the drawings
The present invention is described in further details below in conjunction with the drawings and specific embodiments；
Fig. 1 is a kind of structural representation of ultra high-definition SDI display systems of the present invention；
Fig. 2 is a kind of schematic flow sheet of ultra high-definition SDI display methods of the present invention.
Embodiment
As shown in Figure 1 or 2, the invention discloses a kind of ultra high-definition SDI display systems, it includes the parallel SDI in 4 tunnels and connect
Mouth, FPGA, the first internal memory, central processing unit, the second internal memory and display, high definition SDI letters are respectively connected to per road SDI interfaces
Number, 4 road sdi signal input sequences are immutable；In order to correct transmission channel amplitude-frequency characteristic and phase-frequency characteristic, improve
The antijamming capability of signal.FPGA is connected by a balanced device respectively per road SDI interfaces, balanced device is used for single-ended high definition
Sdi signal becomes differential signal, is advantageous to identification of the rear end to signal, improves the accuracy to signal sequence positioning；FPGA is used
In 4 tunnel high definition sdi signals are spliced into ultra high-definition sdi signal, FPGA connects the first internal memory and central processing unit, centre respectively
Reason device connects the second internal memory and display respectively, and the first internal memory is used for the high definition sdi signal for storing FPGA receptions, and the second internal memory is used
In the ultra high-definition sdi signal of storage FPGA splicing generations, central processing unit is used for the display processing of ultra high-definition sdi signal, display
Device is used for the output display of ultra high-definition sdi signal.
Further, the high definition sdi signal is 2K × 1K-sdi signal, the ultra high-definition sdi signal be 4K × 2K-
Sdi signal.FPGA stores the high definition sdi signal received into the first internal memory, then reads the data in the first internal memory, according to
SMPTE standards, in a manner of 2-sample or square division modes splice four road 2K × 1K of input-sdi signal
Into 4K × 2K all the way-sdi signal.
Further, ddr3 or ddr4 internal memories are saved as in first internal memory and second.
Further, the central processing unit connects display by eDP interfaces.
Further, the display is liquid crystal display.
As shown in Fig. 2 the invention also discloses a kind of ultra high-definition SDI display methods, it comprises the following steps：
1）4 tunnel high definition sdi signals are inputted by the parallel SDI interfaces in 4 tunnels respectively；
2）The single-ended high definition sdi signal in every road is become into differential signal by balanced device and exported to FPGA；
3）4 tunnel high definition sdi signals of reception are stored respectively in the first internal memory by FPGA；
4）FPGA reads 4 tunnel high definition sdi signal splicing synthesis ultra high-definition sdi signals from the first internal memory, and exports to centre
Manage device；
5）Central processing unit receives ultra high-definition sdi signal and is stored in the second internal memory；
6）Central processing unit carries out display processing to ultra high-definition sdi signal for the specification of display, and is exported and shown by display
Show.
Further, step 4）Middle FPGA is based on 2-sample the or Square division in SMPTE425-5 standards
4 tunnel high definition sdi signal splicings are synthesized ultra high-definition sdi signals by mode.
Further, step 6）Central processing unit ultra high-definition sdi signal is processed into and the screen physics of display point
Resolution identical output signal.
Further, step 6）Central processing unit use the Scaler of internal generation to zoom to ultra high-definition sdi signal
The screen physical resolution identical output signal of display.Only when the signal resolution and screen physical resolution phase of output
Meanwhile it can be only achieved optimal point-to-point display effect.
Further, step 6）Central processing unit ultra high-definition sdi signal is exported to display using eDP interfaces, with
Just bigger transmission rate, less electromagnetic interference are obtained.
The present invention uses above technical scheme, has as follows a little：The input mode of 1.SDI signals is the 2k of 4 tunnel independences
× 1k-sdi signal, compared with directly inputting the mode of 1 road 4k × 2k-sdi signal, the distance of signal transmission is farther, can
Preferably it is applied to various occasions, hardware, which is realized, to be also more prone to.2. with the 2-sample in SMPTE425-5 standards or
Square division modes are realized synthesizes 1 road 4k × 2k-SDI letters by 2k × 1k-sdi signal of 4 tunnel independences of input
Number mode, realize and 4k images shown on LCD, greatly reduce the cost of product so that 4k monitor prices, which no longer make, to disappear
Expense person hangs back.3. pair all pass through equalizer processes per the 2k × 1k-sdi signal that inputs all the way so that input it is single-ended
Sdi signal becomes differential signal, improves the antijamming capability of signal；Reduce the hunting range of signal, be advantageous to rear end
Identification when managing signal to signal, improves and signal sequence is accurately positioned.4. used for the resolution ratio scaling of signal in CPU
The Scaler of portion's generation is realized, rather than the special Scaler chips outside use, be not only simplify the structure of hardware, is also reduced
Cost.5. substituting LVDS interface with eDP interfaces, eDP interfaces have following quite obvious advantage in ultra high-definition is shown：It is micro-
Packet structure, more data can be realized（1-4 is to data wire）While transmit；Larger transmission rate, up to 21.6Gbps；
Less size, be advantageous to the lightening of product, carry product more convenient；It is more succinct without LVDS change-over circuits, circuit；
Less EMI, and there is powerful defencive function.
Claims (10)
- A kind of 1. ultra high-definition SDI display systems, it is characterised in that：It include the parallel SDI interfaces in 4 tunnels, FPGA, the first internal memory, Central processing unit, the second internal memory and display, a high definition sdi signal is respectively connected to per road SDI interfaces, per road SDI interfaces difference FPGA is connected by a balanced device, balanced device is used to single-ended high definition sdi signal becoming differential signal, and FPGA is used for 4 tunnels High definition sdi signal is spliced into ultra high-definition sdi signal, and FPGA connects the first internal memory and central processing unit, central processing unit point respectively The second internal memory and display are not connected, and the first internal memory is used for the high definition sdi signal for storing FPGA receptions, and the second internal memory is used to store The ultra high-definition sdi signal of FPGA splicing generations, central processing unit are used for the display processing of ultra high-definition sdi signal, and display is used for The output display of ultra high-definition sdi signal.
- A kind of 2. ultra high-definition SDI display systems according to claim 1, it is characterised in that：The high definition sdi signal is 2K × 1K-sdi signal, the ultra high-definition sdi signal are 4K × 2K-sdi signal.
- A kind of 3. ultra high-definition SDI display systems according to claim 1, it is characterised in that：First internal memory and second Inside save as ddr3 or ddr4 internal memories.
- A kind of 4. ultra high-definition SDI display systems according to claim 1, it is characterised in that：The central processing unit passes through EDP interfaces connect display.
- A kind of 5. ultra high-definition SDI display systems according to claim 1, it is characterised in that：The display is liquid crystal Show device.
- 6. a kind of ultra high-definition SDI display methods, system is shown applied to a kind of ultra high-definition SDI described in one of claim 1 to 5 System, it is characterised in that：Display methods comprises the following steps：1）4 tunnel high definition sdi signals are inputted by the parallel SDI interfaces in 4 tunnels respectively；2）The single-ended high definition sdi signal in every road is become into differential signal by balanced device and exported to FPGA；3）4 tunnel high definition sdi signals of reception are stored respectively in the first internal memory by FPGA；4）FPGA reads 4 tunnel high definition sdi signal splicing synthesis ultra high-definition sdi signals from the first internal memory, and exports to centre Manage device；5）Central processing unit receives ultra high-definition sdi signal and is stored in the second internal memory；6）Central processing unit carries out display processing to ultra high-definition sdi signal for the specification of display, and is exported and shown by display Show.
- A kind of 7. ultra high-definition SDI display methods according to claim 6, it is characterised in that：Step 4）Middle FPGA is based on 4 tunnel high definition sdi signal splicings are synthesized ultra high-definitions by 2-sample the or Square division modes in SMPTE425-5 standards Sdi signal.
- A kind of 8. ultra high-definition SDI display methods according to claim 6, it is characterised in that：Step 6）Central processing unit Ultra high-definition sdi signal is processed into the screen physical resolution identical output signal with display.
- A kind of 9. ultra high-definition SDI display methods according to claim 6, it is characterised in that：Step 6）Central processing unit The screen physical resolution identical that ultra high-definition sdi signal is zoomed to display using the Scaler of inside generation exports letter Number.
- A kind of 10. ultra high-definition SDI display methods according to claim 6, it is characterised in that：Step 6）Central processing unit Ultra high-definition sdi signal is exported to display using eDP interfaces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710899772.7A CN107659787A (en) | 2017-09-28 | 2017-09-28 | A kind of ultra high-definition SDI display systems and its method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710899772.7A CN107659787A (en) | 2017-09-28 | 2017-09-28 | A kind of ultra high-definition SDI display systems and its method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107659787A true CN107659787A (en) | 2018-02-02 |
Family
ID=61117041
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710899772.7A Pending CN107659787A (en) | 2017-09-28 | 2017-09-28 | A kind of ultra high-definition SDI display systems and its method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107659787A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109698937A (en) * | 2018-12-13 | 2019-04-30 | 中电科仪器仪表(安徽)有限公司 | A kind of adaptive LCD controller based on FPGA |
| CN117640871A (en) * | 2023-12-07 | 2024-03-01 | 广东高云半导体科技股份有限公司 | Data conversion device and method from SDI interface to eDP interface |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1972396A (en) * | 2005-10-13 | 2007-05-30 | 索尼株式会社 | Image display system, display apparatus, image re-synthesis apparatus, image re-synthesis method, and recording medium |
| CN203632782U (en) * | 2013-10-31 | 2014-06-04 | 深圳市朗驰欣创科技有限公司 | Picture splicing device |
| CN203632768U (en) * | 2013-10-31 | 2014-06-04 | 深圳市朗驰欣创科技有限公司 | Picture splicing server |
| CN104735297A (en) * | 2013-12-20 | 2015-06-24 | 南京视威电子科技股份有限公司 | Broadcast level monitor and monitoring picture generating method |
| CN105245799A (en) * | 2014-07-08 | 2016-01-13 | 上海菱博电子技术股份有限公司 | 4k*2k ultrahigh-definition liquid crystal control panel |
| CN105472272A (en) * | 2015-11-25 | 2016-04-06 | 浙江工业大学 | Multi-channel video splicing method based on FPGA and apparatus thereof |
| CN105991958A (en) * | 2015-03-03 | 2016-10-05 | 北京华纬讯电信技术有限公司 | Novel video acquisition and display method in video communication system |
-
2017
- 2017-09-28 CN CN201710899772.7A patent/CN107659787A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1972396A (en) * | 2005-10-13 | 2007-05-30 | 索尼株式会社 | Image display system, display apparatus, image re-synthesis apparatus, image re-synthesis method, and recording medium |
| CN203632782U (en) * | 2013-10-31 | 2014-06-04 | 深圳市朗驰欣创科技有限公司 | Picture splicing device |
| CN203632768U (en) * | 2013-10-31 | 2014-06-04 | 深圳市朗驰欣创科技有限公司 | Picture splicing server |
| CN104735297A (en) * | 2013-12-20 | 2015-06-24 | 南京视威电子科技股份有限公司 | Broadcast level monitor and monitoring picture generating method |
| CN105245799A (en) * | 2014-07-08 | 2016-01-13 | 上海菱博电子技术股份有限公司 | 4k*2k ultrahigh-definition liquid crystal control panel |
| CN105991958A (en) * | 2015-03-03 | 2016-10-05 | 北京华纬讯电信技术有限公司 | Novel video acquisition and display method in video communication system |
| CN105472272A (en) * | 2015-11-25 | 2016-04-06 | 浙江工业大学 | Multi-channel video splicing method based on FPGA and apparatus thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109698937A (en) * | 2018-12-13 | 2019-04-30 | 中电科仪器仪表(安徽)有限公司 | A kind of adaptive LCD controller based on FPGA |
| CN117640871A (en) * | 2023-12-07 | 2024-03-01 | 广东高云半导体科技股份有限公司 | Data conversion device and method from SDI interface to eDP interface |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101516015B (en) | Multi-path video data acquiring, processing and transmitting method | |
| CN211184115U (en) | Vehicle-mounted display control terminal with multi-channel video display function | |
| CN202634558U (en) | Image processing device | |
| CN103686314B (en) | Demultiplex device and method adopting HD (high definition) video channel to transmit SD (standard definition) videos | |
| CN102097050B (en) | A kind of apparatus and method realizing display seamless switching | |
| CN111064906A (en) | Domestic processor and domestic FPGA multi-path 4K high-definition video comprehensive display method | |
| CN106537868A (en) | System for dynamic audio visual capabilities exchange | |
| CN105376501A (en) | Image adjusting device and image adjusting method | |
| CN204859440U (en) | Audio frequency and video playback devices | |
| CN103702164B (en) | A kind of ultra high-definition signal transferring device and network machine top box | |
| WO2023000620A1 (en) | Multi-screen display method and device | |
| CN107659787A (en) | A kind of ultra high-definition SDI display systems and its method | |
| WO2020220346A1 (en) | Image processing method and apparatus | |
| US9124861B2 (en) | Display connector with 4K image resolution | |
| CN112492247B (en) | Video display design method based on LVDS input | |
| CN114125328B (en) | Multi-source input multi-screen splicing system and method and display device | |
| CN105516633B (en) | A kind of image processing system | |
| CN206629194U (en) | Vehicular display control device | |
| CN2872534Y (en) | High-resolution liquid-crystal TV-set display circuit with 1080P resolution compatible | |
| CN205212951U (en) | 4K display screen devices that show more | |
| CN105245818A (en) | FPGA-based LED display control system | |
| CN104010137B (en) | The method and apparatus of the upper wall of network HD video splicing | |
| CN105357455A (en) | Method and device for a 4K display to display video sources with one screen | |
| US8237859B2 (en) | Method for video conversion of video stream and apparatus thereof | |
| CN105516632A (en) | Method and system for converting LVDS video signal into DP1.2 video signal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180202 |
|
| RJ01 | Rejection of invention patent application after publication |