CN107659784A - CameraLink image processing apparatus and Electric-Optic Turret - Google Patents
CameraLink image processing apparatus and Electric-Optic Turret Download PDFInfo
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- CN107659784A CN107659784A CN201710769834.2A CN201710769834A CN107659784A CN 107659784 A CN107659784 A CN 107659784A CN 201710769834 A CN201710769834 A CN 201710769834A CN 107659784 A CN107659784 A CN 107659784A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/18—Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/60—Control of cameras or camera modules
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/80—Camera processing pipelines; Components thereof
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/78—Television signal recording using magnetic recording
- H04N5/781—Television signal recording using magnetic recording on disks or drums
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Abstract
The invention provides a kind of CameraLink image processing apparatus and Electric-Optic Turret, it is related to Electric-Optic Turret technical field.Wherein, CameraLink image processing apparatus includes：FPGA processing modules, DSP processing modules and power supply processing module；FPGA processing modules gather the high-definition image of CameraLink standards, the CameraLink data of generation are converted into YUV422 data and are sent to DSP processing modules, and the compressing image data after the compression of DSP processing modules is received, compressing image data is sent to aobvious control end so that aobvious control end monitors the shooting situation of Electric-Optic Turret in real time by Data-Link.Technical scheme provided by the invention uses FPGA+DSP frameworks, can be by the image Compression synchronous transfer of collection to Data-Link, and synchronously it is stored in onboard disk, and it can realize and candid photograph processing is carried out to key area, photo is real-time transmitted to Data-Link, vehicle-mounted various airborne, ship-borne electro-optical system image record direction can extensive use.
Description
Technical field
The present invention relates to Electric-Optic Turret technical field, in particular to a kind of CameraLink image processing apparatus and
Electric-Optic Turret.
Background technology
At present, the image recorder of Electric-Optic Turret, only possess start writing function merely, work(is passed under not possessing in real time
Can, do not possess take pictures in real time and under pass function, the image of Electric-Optic Turret video camera shooting can not be watched in real time, and record data is
Initial data, data volume large volume and power consumption are too high, can not carry out capture pictures to the area-of-interest of Real Time Observation.In addition,
Current image recorder can not adapting to image resolution ratio, therefore changed in image source resolution ratio, image source property
Can not directly it be used when changing, Electric-Optic Turret image recorder at this stage is low in low cost, small size, lightweight
Power consumption, the deficiency of intelligent aspect.Therefore, it is necessary to which a kind of new Electric-Optic Turret image processing equipment realizes Electric-Optic Turret image
Intellectuality, lightweight and the low-power consumption of processing equipment, while can realize and candid photograph processing is carried out to key area, photo passes in real time
It is defeated to arrive Data-Link.
The content of the invention
It is contemplated that at least solves one of technical problem present in prior art or correlation technique.It is proposed a kind of
CameraLink image processing apparatus and Electric-Optic Turret, provide efficient image for Electric-Optic Turret designer and record image transmitting
Mode, can be by the image Compression synchronous transfer of collection to Data-Link, and is synchronously stored in onboard disk, and can realize counterweight
Point region carries out candid photograph processing, and photo is real-time transmitted to Data-Link, in various airborne, vehicle-mounted, ship-borne electro-optical system image record
Direction can extensive use.
The first aspect of the present invention proposes a kind of CameraLink image processing apparatus, including：FPGA processing modules, use
In the high-definition image of collection CameraLink standards, the CameraLink data of generation are converted into YUV422 data and are sent to
DSP processing modules, the compressing image data that DSP processing modules are sent is received, compressing image data is sent to by Data-Link
Aobvious control end；DSP processing modules, FPGA processing modules are connected to, for receiving YUV422 data and being compressed processing, generation pressure
Compressed image data, and compressing image data is sent to FPGA processing modules by bus；Power supply processing module, it is connected to FPGA
Processing module and DSP processing modules, for supply voltage to be converted to the work electricity of FPGA processing modules and DSP processing modules
Pressure.
According to the above-mentioned technical proposal of the present invention, it is preferable that FPGA processing modules, specifically include：CameraLink is gathered
Driving chip, the image information for receiving front-end camera generate CameraLink data；Fpga chip, for inciting somebody to action
CameraLink data are converted to YUV422 data and sent to DSP processing modules, and receive regarding after the compression of DSP processing modules
Frequency evidence；Data-Link synchronizing signal output driving chip, for compressing image data to be sent into aobvious control end by Data-Link.
In any of the above-described scheme preferably, DSP processing modules, specifically include：It is DSP process chips, internal memory, onboard
SATA disk, RTC real-time clocks, RS422 interfaces, RS232 interface, onboard NandFlash and Ethernet interface, for receiving FPGA
YUV422 data compressions are simultaneously entered onboard SATA disk by the YUV422 data of processing module transmission into H.264 data storage, and are passed through
H.264, data/address bus data will be sent to FPGA processing modules in real time.
In any of the above-described scheme preferably, FPGA processing modules processing two-way CameraLink images input, all the way
For visible ray RGB image, another way is infrared thermal imagery gray level image；The resolution ratio and infrared thermal imagery gray scale of visible ray RGB image
The resolution ratio of image is adjusted all in accordance with real image source and is adapted to；The video source images of input are converted into YUV422 data, and press
DSP processing modules are sent to according to BI1120 or BT656 forms.
In any of the above-described scheme preferably, DSP processing modules are using TMS320DM8168 processing serial DAVINCI
Device as master control DSP, DSP start after from RS422 interfaces pair when information, if without pair when information connect from RTC real-time clocks
Receive current temporal information and be used as system clock, DSP receives the YUV422 data that FPGA processing modules send over, to data
It is compressed, H.264 video is stored in onboard disk the high code check of boil down to two-path video respectively, and H.264 video leads to low bit- rate
Cross GPMC buses and be sent to FPGA processing modules, real-time Transmission is set dynamically by RS422 interface control instructions in DSP
Video channel, set storage to stop storage, the H.264 data bit rate of encoder real-time Transmission is set, and set by GPIO
FPGA processing modules are operated under assigned rate pattern.
In any of the above-described scheme preferably, FPGA processing modules receive DSP processing modules by GPMC buses and generated
Low bit- rate H.264 video data with by RS422 interfaces to mission payload information, platform information and status information answer
Packing is closed, subpackage is JPEG picture datas；DSP control instruction is received by GPIO, by data according to default speed through same
422 driving chips are walked to be sent in data link.
In any of the above-described scheme preferably, DSP processing modules are subjected to RS422 photographing instructions, to visible light video,
Thermal imagery infrared video is implemented to capture, and carries out subpackage to the JPEG picture datas for generation of taking pictures, and transmission is utilized by GPMC buses
The gap transmission of real-time video is to FPGA processing modules.
In any of the above-described scheme preferably, DSP processing modules are according to RS422 control instructions, after encoder compresses
The high code check H.264 data and mission payload information, platform information and the status information that are arrived by RS422 interfaces are compound beats
Bag storage, connection specific store cable is supported to be connected using Ethernet interface with outer computer, by File Transfer Protocol by DSP
Manage the composite video data stored in the SATA disk of module and export to outer computer.
In any of the above-described scheme preferably, FPGA processing modules are output to video data and the JPEG subpackages of Data-Link
Data, aobvious control end is transferred to by Data-Link, so that ground display control apparatus will be broadcast after synchronous 422 data parsing by special
Put device to carry out playing display in real time, and the video data received is stored in local disk；FPGA processing modules are additionally operable to
The RS422 that GCU is sent is received to instruct to control the working condition of image recorder, the specific bag of RS422 instructions
Include：Photographing instruction, transmission channel switching command, transmission rate switching command；So that the playout software on the display device of ground enters
Row display switching, switches visible ray and shows, IR image display, it is seen that light and thermal imagery picture-in-picture are shown.
In any of the above-described scheme preferably, DSP processing modules carry out power-on self-test, cycle self-test, instruct self-test, right
Current system-wide running status is detected, and the working condition of designated module is detected in real time, failure reports, and passes through
RS422 interfaces are sent to control terminal, while the information timing of self-test is stored in the journal file of onboard disk, after being easy to
Phase export analysis.
In any of the above-described scheme preferably, power supply processing module, specifically include：Anti- overvoltage surge module, be used for into
Row overvoltage surge is protected；Power down energy-storage module, for ensureing stable power-supplying in the case of the power down of power supply short time；Become pressing mold
Block, for supply voltage to be switched to for the voltage required for FPGA processing modules and DSP processing modules；Electrification reset module, use
Reset operation is carried out when in startup and low voltage.
In any of the above-described scheme preferably, the input voltage of power supply processing module is 28V；Anti- overvoltage surge module can
Handle 50V/50ms overvoltage surges；Power down energy-storage module can ensure system normal operation in the situation of 50ms power down；Voltage changing module
28V input voltages can be transformed to 5V, 3.3V, 2.5V, 1.5V, 1.2V, 1.0V, to ensure each module normal power supply of system；On
Reset module carries out electrification reset using MAX706 to system, and detects supply voltage.
The second aspect of the present invention provides a kind of Electric-Optic Turret, including：As described in above-mentioned technical scheme
CameraLink image processing apparatus.
According to the present invention CameraLink image processing apparatus and Electric-Optic Turret, by way of H.264 video compresses,
The data bit rate of image is reduced, and then prolonged video storage is provided by the onboard disk of small size, its function is integrated
Into image recorder, the power consumption and volume of optoelectronic device are greatly reduced.FPGA+DSP frameworks have been used, can be by collection
Image Compression synchronous transfer is synchronously stored in onboard disk to Data-Link, and can realize and key area is captured
Processing, photo are real-time transmitted to Data-Link, and the technology is a kind of embedded image treatment technology of the small size of low-power consumption, can be fitted
With various video source and resolution ratio, realize that low Data-Link bandwidth hypograph real-time Transmission record is captured.It is vehicle-mounted various airborne,
Ship-borne electro-optical system image record direction can extensive use.Generally, light can be shortened according to technical scheme provided by the invention
The lead time of electric capstan head, the R ＆ D Cost of Electric-Optic Turret is reduced, and special image compressing transmission equipment can be eliminated,
Also there is the advantages that storage time length, Real Time Observation in terms of image record, there is very high Social benefit and economic benefit.
The additional aspect and advantage of the present invention will be set forth in part in the description, and will partly become from the following description
Obtain substantially, or recognized by the practice of the present invention.
Brief description of the drawings
The above-mentioned and/or additional aspect and advantage of the present invention will become in the description from combination accompanying drawings below to embodiment
Substantially and it is readily appreciated that, wherein：
Fig. 1 is the schematic block diagram according to a preferred embodiment of the CameraLink image processing apparatus of the present invention；
Fig. 2 is the block diagram of a preferred embodiment of the modular structure of the CameraLink image processing apparatus of the present invention；
Fig. 3 is the schematic block diagram of a preferred embodiment of the Electric-Optic Turret of the present invention；
Fig. 4 is the hardware principle schematic diagram according to the CameraLink image processing apparatus of the present invention；
Fig. 5 is the software configuration schematic block diagram according to the CameraLink image processing apparatus of the present invention；
Fig. 6 is the work crosslinking figure applied according to the CameraLink image processing apparatus of the present invention in Electric-Optic Turret system.
Embodiment
It is below in conjunction with the accompanying drawings and specific real in order to be more clearly understood that the above objects, features and advantages of the present invention
Mode is applied the present invention is further described in detail.It should be noted that in the case where not conflicting, the implementation of the application
Feature in example and embodiment can be mutually combined.
Many details are elaborated in the following description to facilitate a thorough understanding of the present invention, still, the present invention may be used also
To be different from other modes described here using other to implement, therefore, protection scope of the present invention is not by described below
Specific embodiment limitation.
Fig. 1 is the schematic block diagram according to a preferred embodiment of the CameraLink image processing apparatus of the present invention.
As shown in figure 1, the present invention proposes a kind of CameraLink image processing apparatus 100, including：FPGA processing modules
102, for gathering the high-definition image of CameraLink standards, the CameraLink data of generation are converted into YUV422 data hair
DSP processing modules 104 are given, the compressing image data that DSP processing modules 104 are sent is received, compressing image data is passed through into number
Aobvious control end is sent to according to chain；DSP processing modules 104, FPGA processing modules 102 are connected to, are gone forward side by side for receiving YUV422 data
Row compression is handled, and generates compressing image data, and compressing image data is sent into FPGA processing modules 102 by bus；Electricity
Source processing module 106, FPGA processing modules 102 and DSP processing modules 104 are connected to, for supply voltage to be converted into FPGA
The operating voltage of processing module 102 and DSP processing modules 104.
In this embodiment, using FPGA+DSP frameworks, can by the image Compression synchronous transfer of collection to Data-Link,
Realization carries out candid photograph processing to key area, and photo is real-time transmitted into Data-Link, is a kind of the embedding of small size of low-power consumption
Enter formula image processing techniques, various video source and resolution ratio can be adapted to, realize low Data-Link bandwidth hypograph real-time Transmission record
Capture, can be in various airborne, vehicle-mounted, extensive use on ship-borne electro-optical system image record direction.
Fig. 2 is the modular structure block diagram according to a preferred embodiment of the CameraLink image processing apparatus of the present invention.
As shown in Fig. 2 CameraLink image processing apparatus 100 according to embodiments of the present invention, it is preferable that FPGA processing
Module 102, is specifically included：
CameraLink gathers driving chip 1022, and the image information for receiving front-end camera generates CameraLink numbers
According to；
Fpga chip 1024, sent for CameraLink data to be converted into YUV422 data to DSP processing modules 104, and
Receive the video data after the compression of DSP processing modules 104；
Data-Link synchronizing signal output driving chip 1026, for compressing image data to be sent into aobvious control end by Data-Link.
CameraLink image processing apparatus 100 according to embodiments of the present invention, it is preferable that DSP processing modules 104 are specific
Including：DSP process chips 1041, internal memory 1042, onboard SATA disk 1043, RTC real-time clocks 1044, RS422 interfaces 1045,
RS232 interface 1046, onboard NandFlash1047 and Ethernet interface 1048, for receiving the transmission of FPGA processing modules 102
YUV422 data compressions are simultaneously entered onboard SATA disk by YUV422 data into H.264 data storage, and will H.264 by data/address bus
Data are sent to FPGA processing modules 102 in real time.
CameraLink image processing apparatus 100 according to embodiments of the present invention, it is preferable that at FPGA processing modules 102
The input of two-way CameraLink images is managed, is all the way visible ray RGB image, another way is infrared thermal imagery gray level image；Visible ray
The resolution ratio of RGB image and the resolution ratio of infrared thermal imagery gray level image adjust all in accordance with real image source to be adapted to；The video of input
Source images are converted into YUV422 data, and are sent to DSP processing modules 104 according to BI1120 or BT656 forms.
CameraLink image processing apparatus 100 according to embodiments of the present invention, it is preferable that DSP processing modules 104 use
DAVINCI series TMS320DM8168 processors be used as master control DSP, DSP start after from RS422 interfaces 1045 reception pair when believe
Breath, if information receives current temporal information from RTC real-time clocks 1044 and is used as system clock during nothing pair, DSP is received
Data are compressed by the YUV422 data that FPGA processing modules 102 send over, the two-path video difference high code check of boil down to
H.264 video is stored in onboard disk, and H.264 video is sent to FPGA processing modules 102 to low bit- rate by GPMC buses,
DSP receives control instruction by RS422 interfaces 1045, and the video channel of real-time Transmission is set dynamically, and sets storage to stop storage,
The H.264 data bit rate of encoder real-time Transmission is set, and sets FPGA processing modules 102 to be operated in assigned rate by GPIO
Under pattern.
CameraLink image processing apparatus 100 according to embodiments of the present invention, it is preferable that FPGA processing modules 102 are logical
Cross GPMC buses receive the low bit- rate of the generation of DSP processing modules 104 H.264 video data with being received by RS422 interfaces 1045
The compound packing of mission payload information, platform information and status information arrived, subpackage are JPEG picture datas；Received by GPIO
DSP control instruction, data are sent in data link according to synchronized 422 driving chip of default speed.
CameraLink image processing apparatus 100 according to embodiments of the present invention, it is preferable that DSP processing modules 104 can connect
By RS422 photographing instructions, to visible light video, thermal imagery infrared video is implemented to capture, and to the JPEG picture datas for generation of taking pictures
Subpackage is carried out, by GPMC buses using transmitting the gap transmission of real-time video to FPGA processing modules 102.
CameraLink image processing apparatus 100 according to embodiments of the present invention, it is preferable that the basis of DSP processing modules 104
RS422 control instructions, H.264 the high code check after encoder compresses data and is passed through the received task of RS422 interfaces 1045
Load information, platform information and the compound packing storage of status information, support connection specific store cable to use Ethernet interface
1048 are connected with outer computer, the composite video data that will be stored by File Transfer Protocol in the SATA disk of DSP processing modules 104
Export to outer computer.
CameraLink image processing apparatus 100 according to embodiments of the present invention, it is preferable that FPGA processing modules 102 are defeated
Go out the video data and JPEG packetized datas to Data-Link, aobvious control end is transferred to by Data-Link, so that ground display control is set
It is standby to carry out playing display in real time by special player after synchronous 422 data parsing, and the video data received is stored
In local disk；The RS422 that FPGA processing modules 102 are additionally operable to receive GCU transmission is instructed to control image to remember
The working condition of recording apparatus, RS422 instructions specifically include：Photographing instruction, transmission channel switching command, transmission rate switching refer to
Order；So that the playout software on the display device of ground carries out display switching, switching visible ray is shown, IR image display, it is seen that light and
Thermal imagery picture-in-picture is shown.
CameraLink image processing apparatus 100 according to embodiments of the present invention, it is preferable that DSP processing modules 104 are carried out
Power-on self-test, cycle self-test, self-test is instructed, current system-wide running status is detected, the work shape to designated module
State is detected in real time, and failure reports, and control terminal is sent to by RS422 interfaces 1045, while by the information of self-test regularly
It is stored in the journal file of onboard disk, is easy to later stage export analysis.
CameraLink image processing apparatus 100 according to embodiments of the present invention, it is preferable that power supply processing module 106, tool
Body includes：Anti- overvoltage surge module 1062, for carrying out overvoltage surge protection；Power down energy-storage module 1064, for short in power supply
Ensure stable power-supplying in the case of time power down；Voltage changing module 1066, for supply voltage to be switched to for FPGA processing modules 102
With the voltage required for DSP processing modules 104；Electrification reset module 1068, for carrying out reset behaviour in startup and low voltage
Make.
CameraLink image processing apparatus 100 according to embodiments of the present invention, it is preferable that power supply processing module 106
Input voltage is 28V；Anti- overvoltage surge module 1062 can handle 50V/50ms overvoltage surges；Power down energy-storage module 1064 can be
The situation of 50ms power down ensures system normal operation；Voltage changing module 1066 28V input voltages can be transformed to 5V, 3.3V, 2.5V,
1.5V, 1.2V, 1.0V, to ensure each module normal power supply of system；Electrification reset module 1068 is carried out using MAX706 to system
Electrification reset, and detect supply voltage.
As shown in figure 3, a kind of Electric-Optic Turret 300 provided by the invention, including：As described in above-mentioned embodiment
CameraLink image processing apparatus 100.
In this embodiment, turned using the CameraLink image processing apparatus 100 as described in above-mentioned embodiment for photoelectricity
Deethanizer design person provides fine image record image transmitting mode, shortens the lead time of Electric-Optic Turret, reduces photoelectricity and turn
The R ＆ D Cost of tower, and special image compressing transmission equipment can be eliminated, also there is storage time in terms of image record
It is long, the advantages that Real Time Observation, there is very high Social benefit and economic benefit.
Fig. 4 is the hardware principle schematic diagram of the CameraLink image processing apparatus of the embodiment of the present invention, and Fig. 5 is the present invention
The software configuration schematic block diagram of the CameraLink image processing apparatus of embodiment, as shown in Figure 4 and Figure 5：
This embodiment offers a kind of dual-path high-definition CameraLink image recording structures, hardware configuration is shown in Fig. 5：Using FPGA+
DSP schemes, the picture format of data source can be adapted to, processing is acquired to various non-standard image forms, uses TI
The DAVINCI series TMS320DM8168 processors of company, the multinuclear isomery special image that the processor is DSP+ARM are handled
Device, (SuSE) Linux OS is used, carried out related software exploitation, possessed very powerful image-capable and control is handed over
Mutual function, and possess very strong scalability, the present invention includes from hardware：Power supply processing module, FPGA processing modules,
DSP processing modules, software kit contain：Bootloader, U-boot, linux kernel, Linux drivings, file system and recording equipment
In the NANDflash of application program, software program fixed line and DSP processing modules.
FPGA processing modules are used for the high-definition image for gathering two-way CameraLink standards, by CameraLink data conversions
DSP processing units are sent to for YUV422 data, DSP processing modules receive the YUV422 view data of FPGA processing unit processes
Processing is compressed, the data storage after compression is simultaneously sent to FPGA processing units by bus and is sent to Data-Link.
FPGA processing modules, comprising fpga chip, CameraLink collection driving chips, the output of Data-Link synchronizing signal is driven
Dynamic chip, CameraLink collection driving chips receive the image information of leading portion camera, and FPGA collection image informations are simultaneously changed
DSP is sent to be compressed processing for YUV422 forms, FPGA receives the video data after DSP compressions, defeated through Data-Link synchronizing signal
Go out driving chip and be sent to airborne data link.
Wherein FPGA processing modules select the FPGA of XLINX companies, use two pieces of CameraLink acquisition chips, maximum branch
85Mhz sample rate is held, supports maximum 1080P, 30HZ IMAQ ability, the data collected, FPGA can be to image
Data carry out technology and judgement, use different conversion regimes for colored and black and white gray level image, rgb color space is changed
For YUV422 color space datas, DSP is sent into the data format according to BT656 or BT1120 according to the image resolution ratio of reality
The video input port of chip.
The H.264 compressing image data that FPGA processing modules are sent according to DSP Processor GPMC bus timings, reception DSP,
Picture data, the command information sent according to DSP Processor GPIO and bus, the output frequency set according to DSP, by video and
Photo packetized data, according to synchronous 422 sequential, synchronized 422 driving chip, it is sent on Electric-Optic Turret on-board data link.
Inputted characterized in that, described FPGA processing modules can handle two-way CameraLink images, all the way visible ray
RGB888, all the way infrared thermal imagery gray level image, it is seen that light image resolution ratio, infrared thermal imagery image resolution ratio can be according to actual figures
Image source adjustment adaptation, the video source images of input can carry out color space conversion by FPGA, be converted to YUV422 data, and according to
BI1120 or BT656 forms send DSP processing modules.
Wherein power supply processing module includes the module of anti-overvoltage surge, power down energy-storage module, voltage changing module, electrification reset mould
Block, anti-overvoltage surge module are used to carry out overvoltage surge protection under airborne circumstance, and power down energy-storage module is used in power supply in short-term
Ensure that system power supply is stable in the case of power down, voltage changing module is responsible for switching to supply voltage for FPGA processing modules, DSP processing
Module required voltage, electrification reset module are used to carry out reset operation to total system in startup and low voltage.
Characterized in that, described power supply processing module input voltage is 28V airborne power supplies, meet airborne power reguirements,
Its antisurge module can handle 50V/50ms overvoltage surges, and power down energy-storage module can ensure that system is normal in the situation of 50ms power down
28V input voltages can be transformed to 5V, 3.3V, 2.5V, 1.5V, 1.2V, 1.0V by operation, voltage changing module, ensure each module of system
Normal power supply, electrification reset carries out electrification reset using MAX706 to system, and detects supply voltage.
What power supply processing module used meets GJB181A-2003《Aircraft electrical supply parameters》Related request, possess individually should
Experiment to 50V/50ms overvoltage surges, possess energy-storage module, the abnormity of power supply of 50ms power down is tackled, using two-stage Switching Power Supply
Voltage needed for the complete paired systems of chip is changed, and employs MAX706 chips, is handled electrification reset and is carried out electricity to power supply
Pressure detection ensures system run all right, while MAX706 possesses watchdog function, and software carries out dog feeding operation, different in software work
Reset operation is carried out to system in time when often.
DSP processing modules include, DSP process chips, DDR3 internal memories, onboard SATA electric boards, RTC real-time clocks, all the way
RS422 serial ports, all the way RS232 serial ports, onboard NandFlash, all the way Ethernet interface, dsp chip reception FPGA transmissions regard
Frequency evidences, required H.264 data are compressed into, are stored into onboard SATA disk, are sent to FPGA processing modules in real time by bus,
Aobvious control end is sent to through Data-Link.
DSP module, using 128MB NADNFlash chips as operating system software memory block, extend in 2GB DDR3
Region is deposited as system for content and image procossing buffering area, is configured with view data of the 128GB onboard SSD hard disks as record
Storage dish, meets the storage of two-way HD video, and TMS320DM8168 processors support maximum 4 passages of two-way height dicode rate
1080P 30HZ H.264 compressed capability, high code check high-resolution image storage can lead in onboard disk, low bit- rate low definition
Cross on-board data link and be sent to display device, while DSP module can receive the various of control terminal transmission according to communications protocol
Instruction, the working condition of itself, feedback operation state are adjusted according to environmental factor.
DSP processing modules are subjected to RS422 photographing instructions, and to visible light video, thermal imagery infrared video carries out implementation candid photograph,
And subpackage is carried out to the JPEG picture datas for generation of taking pictures, arrived by GPMC buses using the gap transmission for transmitting real-time video
FPGA processing modules.
H.264 high code check after encoder compresses and can be passed through RS422 according to RS422 control instructions by DSP processing modules
The information that serial ports receives（Include mission payload, platform information, status information）By the compound packing storage of specified format, work as task
After the completion of, specific store cable can be connected, is connected using Ethernet interface with outer computer, by File Transfer Protocol, by DSP moulds
The composite video data stored in block in SATA electronic editions exports to outer computer.
DSP module can carry out power-on self-test, cycle self-test, instruct self-test, and current system-wide running status is examined
Survey, the working condition of counterweight point module is detected in real time, and failure reports, and is sent to control terminal by RS422 ports, simultaneously
The logo files information timing of self-test being stored in onboard disk, it is easy to later stage export analysis.
FPGA module is output to the composite video data and JPEG packetized datas of Data-Link, and ground is transferred to by Data-Link
Display device, ground display control apparatus can will carry out playing display in real time after synchronous 422 data parsing by special player,
And stored the video data received in local disk, RS422 instructions, which can be transmitted, by GCU is used for controlling
The working condition of imaged recording equipment, photographing instruction is sent, send the instruction such as transmission channel switching, transmission rate switching.Ground
Playout software on the display device of face can carry out display switching, and switching visible ray is shown, IR image display, it is seen that in light and thermal imagery picture
Draw display.
Software configuration is shown in Fig. 5：
Wherein U-BOOT is the bootstrap that linux kernel starts, and U_BOOT sets CPU mode of operations, initializes internal memory, NAND
The equipment such as FLASH, terminal network, and detect the bad block in NAND FLASH and mark bad block, according to enabled instruction, carry simultaneously
Linux kernel and file system are decompressed into internal memory, after the environment that initialization kernel starts, starts linux kernel.
Linux kernel and file system, are called for application providing system, and the management of various equipment, linux kernel is opened
Hair is in addition to needing to carry out function cutting according to the actual requirements, it is necessary to which hardware driving corresponding to realization, after kernel startup, kernel opens
It can be initialized after dynamic and hang over root file system, initialize each driving simultaneously used in carry system, generated device file, finally adjust
With application program launching script, application program is run.
The driving for needing to be developed in logging recorder system includes：2 road 1080P30 frames video acquisition drivings, GPMC buses
Communicate driving, SATA drivings, serial port drive, Ethernet driving.
Each driver needs the correctness of test program checking driver corresponding to exploitation simultaneously.
Application software calls bottom video collection driving, realizes 2 road 1080P30 frames video acquisitions, in real time by compression of images
Into H264 forms or jpeg format, low-bit-rate compact view data is put into the transmission buffering area in GPMC buses, according to synchronous 422
Sequential is sent to Data-Link, and high Compression image is stored in STAT disks parallel, and to the real-time detection of SATA disk, carries out circulation and deposit
Storage, the baud rate, data bit, parity check bit of 1 road RS422 serial ports are can configure, receive the control instruction that control terminal is sent,
Control the mode of operation of image recorder, the working condition of feedback image recording equipment.
Fig. 6 is that the work that the CameraLink image processing apparatus of the embodiment of the present invention is applied in Electric-Optic Turret system is handed over
Connection figure.
As shown in fig. 6, present embodiments provide a kind of CameraLink images record that can handle dual-path high-definition image
Device, the device use DC28V direct current supplys, connect CameraLink visible light video source, and thermal imagery infrared video source is synchronous
422 are connected to airborne data link, and RS422 asynchronous 422 is connected to control terminal.
CameraLink image processing apparatus, two-way CameraLink vision signals are received, FPGA after the power-up can be automatic
The working condition of current image source is detected, and DSP is fed back information to by GPIO and bus, DSP is detected simultaneously works as forward sight
The working condition of frequency codec, when image source input is normal, encoder is working properly to enter normal operating conditions afterwards, and ought
Preceding status information is sent to control terminal by RS422.
The dsp software of CameraLink image processing apparatus configures its VIDEO coprocessor, its coprocessor is generated 4
Individual H.264 encoder threads, 2 JPEG encode thread, and set its VPSS coprocessor to complete to the noise reduction of input picture
Reason, passage configuration, send VIDEO coprocessors to perform the encoding operation view data.
The dsp software of CameraLink image processing apparatus sets the coding of codec according to RS422 control instruction
Code check, stores code check, frame per second, and the data buffering after generation is in internal memory, and H.264 the compound RS422 ends of video are sent high code check
After platform information, stored, sent out after the low bit- rate platform information that H.264 the compound RS422 ends of video are sent by GPMC buses
It is sent in FPGA transmission FIFO, is sent according to the transmission rate of setting.
The dsp software of CameraLink image processing apparatus detects current disk size feelings in real time in storing process
Condition, calculating can storage time, by current log file quantity, disk free space, can storage time be sent to control terminal.
The dsp software of CameraLink image processing apparatus receives the photographing instruction of control terminal, and key area is carried out
Take pictures, and return to current state of taking pictures and give control terminal.
When the dsp software of CameraLink image processing apparatus is taken pictures, the photo for generation of taking pictures is after subpackage, in video
The gap of transmission is sent to display terminal, and the player software of display terminal can directly be broadcast when receiving real time video data
Put, picture-in-picture also may be selected and play, while local disk is arrived into the video storage of broadcasting, playout software receives the picture of subpackage
After data, packaged by bag sequence number, and the picture data that group bag is completed is stored in local disk.
For the dsp software of CameraLink image processing apparatus in system worked well, timing carries out self-test, detects leading portion
The information such as the state of image source, encoder turntable, disk working condition, recordable time, sent by RS422 to control eventually
End, while self-test information can be recorded in real time in disk file.
CameraLink image processing apparatus receives the start recording instruction of RS422 transmissions, into recording status, by two
In road CameraLinkH.264 compression video deposit disks, the stop recording data when RS422 sends stop recording instruction.
After the completion of the work of CameraLink image processing apparatus, it client cables can be used to be connected by Ethernet interface and show
Equipment, by the two-way stored in CameraLink image processing apparatus, H.264 video exports to display device, now passes through control
Equipment, which is sent, deletes video instructions, can all delete all videos in disk.
It can be seen from above-mentioned each embodiment, the present invention is analyzed the demand of image recorder, finds to pass through
H.264, the mode that video compresses, the data bit rate of image can be reduced, and then be provided for a long time by the onboard disk of small size
Video stores, and after studying graphic transmission equipment, its function is incorporated into image recorder, greatly reduces light
The power consumption and volume of electric equipment, can be by the image Compression synchronous transfer of collection to Data-Link, and is synchronously stored in onboard magnetic
Disk, and can realize and carry out candid photograph processing to key area, photo is real-time transmitted to Data-Link, overcome prior art it is low into
This, small size, lightweight, low-power consumption, the deficiency of intelligent aspect.In various airborne, vehicle-mounted, ship-borne electro-optical system image record
Direction can extensive use.
The preferred embodiments of the present invention are the foregoing is only, are not intended to limit the invention, for the skill of this area
For art personnel, the present invention can have various modifications and variations.Within the spirit and principles of the invention, that is made any repaiies
Change, equivalent substitution, improvement etc., should be included in the scope of the protection.
Claims (10)
1. a kind of CameraLink image processing apparatus, the image obtained to Electric-Optic Turret front end picture pick-up device is recorded and passed
It is defeated, it is characterised in that including：
FPGA processing modules, for gathering the high-definition image of CameraLink standards, by the CameraLink data conversions of generation
DSP processing modules are sent to for YUV422 data, the compressing image data that the DSP processing modules are sent are received, by the pressure
Compressed image data is sent to aobvious control end by Data-Link, the DSP processing modules, is connected to the FPGA processing modules, is used for
Receive the YUV422 data and be compressed processing, generate the compressing image data, and the compressing image data is led to
Cross bus and be sent to the FPGA processing modules；
Power supply processing module, the FPGA processing modules and the DSP processing modules are connected to, for supply voltage to be converted to
The operating voltage of the FPGA processing modules and the DSP processing modules.
2. CameraLink image processing apparatus according to claim 1, it is characterised in that the FPGA processing modules bag
Include：
CameraLink gathers driving chip, and the image information for receiving front-end camera generates the CameraLink numbers
According to；
Fpga chip, sent for the CameraLink data to be converted into YUV422 data to the DSP processing modules, and
Receive the video data after DSP processing modules compression；
Data-Link synchronizing signal output driving chip, for the compressing image data to be sent into the aobvious control by Data-Link
End.
3. CameraLink image processing apparatus according to claim 2, it is characterised in that the DSP processing modules bag
Include：DSP process chips, internal memory, onboard SATA disk, RTC real-time clocks, RS422 interfaces, RS232 interface, onboard NandFlash
And Ethernet interface, for receive YUV422 data that the FPGA processing modules send and by the YUV422 data compressions into
H.264 data storage enters the onboard SATA disk, and the H.264 data are sent into the FPGA in real time by data/address bus
Processing module.
4. CameraLink image processing apparatus according to claim 3, it is characterised in that at the FPGA processing modules
The input of two-way CameraLink images is managed, is all the way visible ray RGB image, another way is infrared thermal imagery gray level image；It is described can
See that the resolution ratio of light RGB image and the resolution ratio of the infrared thermal imagery gray level image adjust all in accordance with real image source to be adapted to；It is defeated
The video source images entered are converted into YUV422 data, and are sent to the DSP according to BI1120 or BT656 forms and handle mould
Block.
5. CameraLink image processing apparatus according to claim 4, it is characterised in that the DSP processing modules are adopted
By the use of DAVINCI series TMS320DM8168 processors be used as master control DSP, DSP startup after from the RS422 interfaces pair when
Information, if information receives current temporal information from the RTC real-time clocks and is used as system clock during nothing pair, DSP is received
Data are compressed by the YUV422 data that the FPGA processing modules send over, the two-path video difference high code check of boil down to
H.264 video is stored in onboard disk, and H.264 video is sent to the FPGA processing modules to low bit- rate by GPMC buses,
The video channel of real-time Transmission is set dynamically by the RS422 interfaces control instruction in DSP, sets storage to stop storage,
The H.264 data bit rate of encoder real-time Transmission is set, and sets the FPGA processing modules to be operated in by GPIO and specifies speed
Under rate pattern.
6. CameraLink image processing apparatus according to claim 5, it is characterised in that the FPGA processing modules are led to
Cross GPMC buses and receive the low bit- rate of DSP processing modules generation and H.264 video data and arrived by RS422 interfaces
Mission payload information, platform information and the compound packing of status information, subpackage are JPEG picture datas；Receive DSP's by GPIO
Control instruction, data are sent in data link according to synchronized 422 driving chip of default speed.
7. CameraLink image processing apparatus according to claim 3, it is characterised in that the DSP processing modules connect
By RS422 photographing instructions, to visible light video, thermal imagery infrared video is implemented to capture, and to the JPEG picture datas for generation of taking pictures
Subpackage is carried out, by GPMC buses using transmitting the gap transmission of real-time video to FPGA processing modules.
8. CameraLink image processing apparatus according to claim 3, it is characterised in that the DSP processing modules root
According to RS422 control instructions, the high code check after encoder compresses, H.264 data and being arrived by RS422 interfaces for task carry
Lotus information, platform information and compound pack of status information store, and support connection specific store cable is using Ethernet interface and outside
Portion's computer connection, outside meter is exported to by File Transfer Protocol by the composite video data stored in the SATA disk of DSP processing modules
Calculation machine.
9. CameraLink image processing apparatus according to claim 7, it is characterised in that the FPGA processing modules are defeated
Go out the video data and JPEG packetized datas to Data-Link, aobvious control end is transferred to by Data-Link, so that ground display control is set
It is standby to carry out playing display in real time by special player after synchronous 422 data parsing, and the video data received is stored
In local disk；The RS422 that the FPGA processing modules are additionally operable to receive GCU transmission is instructed to control image
The working condition of recording equipment, the RS422 instructions specifically include：Photographing instruction, transmission channel switching command, transmission rate are cut
Change instruction；So that the playout software on the display device of ground carries out display switching, switching visible ray is shown, IR image display, it is seen that
Light and thermal imagery picture-in-picture are shown.
A kind of 10. Electric-Optic Turret, it is characterised in that including：CameraLink figures as claimed in any one of claims 1-9 wherein
As processing unit.
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