CN107659305A - A kind of clock count method, apparatus and medium based on CPLD - Google Patents

A kind of clock count method, apparatus and medium based on CPLD Download PDF

Info

Publication number
CN107659305A
CN107659305A CN201710977085.2A CN201710977085A CN107659305A CN 107659305 A CN107659305 A CN 107659305A CN 201710977085 A CN201710977085 A CN 201710977085A CN 107659305 A CN107659305 A CN 107659305A
Authority
CN
China
Prior art keywords
counting
cycle
level
cpld
count
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710977085.2A
Other languages
Chinese (zh)
Inventor
刘帅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhengzhou Yunhai Information Technology Co Ltd
Original Assignee
Zhengzhou Yunhai Information Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhengzhou Yunhai Information Technology Co Ltd filed Critical Zhengzhou Yunhai Information Technology Co Ltd
Priority to CN201710977085.2A priority Critical patent/CN107659305A/en
Publication of CN107659305A publication Critical patent/CN107659305A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K23/00Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/002Pulse counters comprising counting chains; Frequency dividers comprising counting chains using semiconductor devices

Abstract

Include the invention discloses a kind of clock count method, apparatus and medium based on CPLD, the step of this method:CPLD event duration is obtained, and is set according to event duration and characterizes the level for counting the cycle;Level comprises at least two layers, and lowermost layer characterizes the system cycle;It is positive correlation to count the duration in cycle and the rank of level, and what higher levels characterized counts the integral multiple that the cycle is the counting cycle that lower-level characterizes;The counting cycle that lowermost layer characterizes using in level starts counting up as current period, when counting duration reaches the object count cycle that next level is characterized, using the object count cycle as current period to continue to count, until top sign in current period and level counting cycle phase with untill;Continue to count according to current period to reach event duration.It can be seen that this method is relative to improve whole work efficiencies of the CPLD in clock count.In addition, the present invention also provides a kind of clock count device based on CPLD and medium, beneficial effect are as described above.

Description

A kind of clock count method, apparatus and medium based on CPLD
Technical field
The present invention relates to CPLD fields, more particularly to a kind of clock count method, apparatus and medium based on CPLD.
Background technology
Clock is a very important ring in flogic system, and all sequential logic modules are required to clock as execution Synchronizing signal.
In flogic system huge CPLD, user is to the duration demand of clock often from microsecond rank across to second level Not, there is also larger difference for consumption of the different durations for CPLD logical resources.Clock meter used by current CPLD Number scheme, a length of fundamental clock duration when being with system clock, and combine counter and carry out clock count operation.For example, system Clock is 50MHz, i.e. the system cycle is 20ns, and if necessary to produce the clock signal of 1us durations, then counter needs counting 50 Secondary (1us/20ns=50), 50 need the binary number of 6 to count.It can be seen that when the duration of clock signal is longer, required meter The digit of number devices is more, and is as the counting numerical digit used in logic unit provides counter in CPLD, but works as logic list When member is used to provide counting numerical digit, the logic unit is unrenewable in other logical operations.But in CPLD logic unit number Amount is relatively in short supply, therefore when using above-mentioned clock count scheme, and using signal duration longer, is accounted for for logic unit With larger, the overall CPLD operating efficiency of relative reduction.
As can be seen here, there is provided a kind of clock count method based on CPLD, with relative raising CPLD in clock count Whole work efficiency, it is those skilled in the art's urgent problem to be solved.
The content of the invention
It is an object of the invention to provide a kind of clock count method, apparatus and medium based on CPLD, is improved with relative Whole work efficiencies of the CPLD in clock count.
In order to solve the above technical problems, the present invention provides a kind of clock count method based on CPLD, including:
CPLD event duration is obtained, and is set according to event duration and characterizes the level for counting the cycle;Wherein, level is at least Including two layers, and lowermost layer characterizes the system cycle;It is positive correlation to count the duration in cycle and the rank of level, in adjacent level In, what higher levels characterized counts the integral multiple that the cycle is the counting cycle that lower-level characterizes;
The counting cycle that lowermost layer characterizes using in level starts counting up as current period, reaches next layer when counting duration Level characterized the object count cycle when, using the object count cycle as current period to continue to count, until current period and The counting cycle phase of top sign is with untill in level;
Continue to count according to current period to reach event duration.
Preferably, the counting cycle that lowermost layer characterizes using in level starts counting up specially as current period:
Display look-up table LUT is used to be opened as the counter counting cycle that lowermost layer characterizes using in level as current period Begin to count.
Preferably, this method further comprises:
The resource occupation amount of CPLD in counting process is obtained, and is shown to user.
Preferably, this method further comprises:
Resource threshold is set, and judges whether resource occupation amount exceedes the scope of resource threshold;
If it is, carry out abnormal prompt to user.
Preferably, when judging that resource occupation amount exceedes the scope of resource threshold, this method further comprises:
Resource occupation amount is recorded to daily record.
Preferably, the system cycle is specially 20ns.
In addition, the present invention also provides a kind of clock count device based on CPLD, including:
Initial module, for obtaining CPLD event duration, and set according to event duration and characterize the level for counting the cycle;
First counting module, started counting up for the counting cycle that lowermost layer characterizes using in level as current period, when Duration is counted when reaching the object count cycle that next level is characterized, using the object count cycle as current period in terms of continuing Number, untill the counting cycle phase of top sign in current period and level is same;
Second counting module, for continuing to count to reach event duration according to current period.
Preferably, the device further comprises:
Display module, for obtaining the resource occupation amount of CPLD in counting process, and it is shown to user.
In addition, the present invention also provides a kind of clock count device based on CPLD, including:
Memory, for storing computer program;
Processor, the step of clock count method based on CPLD described above is realized during for performing computer program.
In addition, the present invention also provides a kind of computer-readable recording medium, meter is stored with computer-readable recording medium Calculation machine program, the step of clock count method based on CPLD described above is realized when computer program is executed by processor.
Clock count method provided by the present invention based on CPLD, the duration counted according to required for CPLD event, Counting cycle level of the setting for the duration.Because each level correspond to count the cycle, and level is from low to high The corresponding counting cycle, the counting cycle characterized using lowermost layer in the level started as current period from short to long Count, when counting duration reaches the object count cycle that more high-level in the level is characterized, by object count week Phase is as the new current period to continue to count.It can be seen that when often rising a level, the cycle all can be used by counting Increase, accordingly reaching the counts of counting duration will accordingly be reduced, and counts decrease counter while reduction The binary digit required for counts is represented, resource occupation for logic unit in CPLD is reduced with this, ensure that Operating efficiency overall CPLD.In addition, the present invention also provides a kind of clock count device and medium based on CPLD, beneficial effect As described above.
Brief description of the drawings
In order to illustrate the embodiments of the present invention more clearly, the required accompanying drawing used in embodiment will be done simply below Introduce, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for ordinary skill people For member, on the premise of not paying creative work, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is a kind of flow chart of the clock count method based on CPLD provided in an embodiment of the present invention;
Fig. 2 is the flow chart of another clock count method based on CPLD provided in an embodiment of the present invention;
Fig. 3 is a kind of clock count structure drawing of device based on CPLD provided in an embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.Based on this Embodiment in invention, for those of ordinary skill in the art under the premise of creative work is not made, what is obtained is every other Embodiment, belong to the scope of the present invention.
The core of the present invention is to provide a kind of clock count method based on CPLD, relative to improve CPLD in clock count When whole work efficiency.Another core of the present invention is to provide a kind of clock count device and medium based on CPLD.
In order that those skilled in the art more fully understand the present invention program, with reference to the accompanying drawings and detailed description The present invention is described in further detail.
Embodiment one
Fig. 1 is a kind of flow chart of the clock count method based on CPLD provided in an embodiment of the present invention.It refer to Fig. 1, The specific steps of clock count method based on CPLD include:
Step S10:CPLD event duration is obtained, and is set according to event duration and characterizes the level for counting the cycle.
Wherein, level comprises at least two layers, and lowermost layer characterizes the system cycle;Count the duration in cycle and the rank of level For positive correlation, in adjacent level, what higher levels characterized counts the integer that the cycle is the counting cycle that lower-level characterizes Times.
It should be noted that " counting " herein refers both to CPLD clock count.This step is firstly the need of acquisition CPLD The duration of performed event, and then the level in suitable counting cycle can be determined.The quantity of level should depending on duration, Duration is longer, and in order to ensure usage count device numerical digit as not excessive as possible, the quantity of level should be relatively more.
Step S11:The counting cycle that lowermost layer characterizes using in level starts counting up as current period, is up to when counting During the object count cycle characterized to next level, using the object count cycle as current period to continue to count, until working as The counting cycle phase of top sign is with untill in preceding cycle and level.
It is understood that and then as the raising of level, its counting cycle characterized also gradually increase, and then often on A level is risen, reduces corresponding quantity for the counter numerical digit that current period is counted, and then save offer meter The quantity of the CPLD logic units of number device numerical digit, it ensure that CPLD can have relatively sufficient resource to handle other affairs.
Step S12:Continue to count according to current period to reach event duration.
Current period in this step, in the cycle characterized by highest level, can be to make CPLD whole in counting process The counting cycle of body expense relative equilibrium and CPLD state optimizations.
Clock count method provided by the present invention based on CPLD, the duration counted according to required for CPLD event, Counting cycle level of the setting for the duration.Because each level correspond to count the cycle, and level is from low to high The corresponding counting cycle, the counting cycle characterized using lowermost layer in the level started as current period from short to long Count, when counting duration reaches the object count cycle that more high-level in the level is characterized, by object count week Phase is as the new current period to continue to count.It can be seen that when often rising a level, the cycle all can be used by counting Increase, accordingly reaching the counts of counting duration will accordingly be reduced, and counts decrease counter while reduction The binary digit required for counts is represented, resource occupation for logic unit in CPLD is reduced with this, ensure that Operating efficiency overall CPLD.
Embodiment two
On the basis of above-described embodiment, as a preferred embodiment, the counting characterized with lowermost layer in level Cycle starts counting up specially as current period:
Display look-up table LUT is used to be opened as the counter counting cycle that lowermost layer characterizes using in level as current period Begin to count.
It should be noted that display look-up table LUT is inherently a RAM (internal memory), generally there is the spy of four inputs Property, each LUT can represent the binary number of four, the logical construction that counter is made up of one or more LUT, LUT usage quantity should be not specifically limited herein depending on the numerical digit needed for count number.Because LUT is normal in CPLD With element, therefore it counter is used as by LUT can realize, and then stabilization when can ensureing count preferably compatible with CPLD Property.
Fig. 2 is the flow chart of another clock count method based on CPLD provided in an embodiment of the present invention.Step in Fig. 2 S10-S12 is identical with Fig. 1, will not be repeated here.
As shown in Fig. 2 as a preferred embodiment, this method further comprises:
Step S20:The resource occupation amount of CPLD in counting process is obtained, and is shown to user.
It is to ensure that CPLD is normal and the base of efficient operation it is understood that for the reasonable employment of CPLD available resources Plinth, therefore in order that user's more intuitive understanding CPLD resource service condition, can be obtained in real time in counting process Current CPLD resource occupation amount is simultaneously shown to user, improves user in counting process to occupation condition Solution degree, and then corresponding processing can be done according to different occupation conditions.
As shown in Fig. 2 as a preferred embodiment, this method further comprises:
Step S21:Resource threshold is set, and judges whether resource occupation amount exceedes the scope of resource threshold, if it is, Perform step S22.
Step S22:Abnormal prompt is carried out to user.
It is understood that the scope that resource threshold is the resource occupation amount for regulation normal condition is set, by sentencing Whether disconnected current resource occupation amount exceedes the scope of resource threshold and determines whether the currently use to CPLD exception occurs, such as Fruit is then to need to inform user in time, and then user can make corresponding processing as early as possible.
On the basis of above-mentioned embodiment, as a preferred embodiment, being provided when judging that resource occupation amount exceedes During the scope of source threshold value, this method further comprises:
Resource occupation amount is recorded to daily record.
It is understood that when resource occupation amount exceedes the scope of threshold value, i.e., when resource occupation occurs abnormal, by resource Occupancy is recorded to daily record, the concrete condition of CPLD resource occupation amounts when user can understand abnormal conditions by searching daily record, For subsequently for CPLD clock count strategy optimization and improve strong reference is provided.
In addition, as a preferred embodiment, the system cycle is specially 20ns.
It should be noted that the system cycle can be modified according to the demand of user, but the system cycle should meet be The requirement for the nominal period united under most component working conditions, and the specified work of most components including CPLD generally Make the cycle for 20ns or so, thus the system cycle is set to 20ns being capable of the relative compatibility for ensureing to work between component.
Embodiment three
Hereinbefore it is described in detail for a kind of embodiment of the clock count method based on CPLD, the present invention A kind of clock count device based on CPLD is also provided, because the embodiment of device part and the embodiment of method part are mutually right Should, therefore the embodiment of device part refers to the description of the embodiment of method part, wouldn't repeat here.
Fig. 3 is a kind of clock count structure drawing of device based on CPLD provided in an embodiment of the present invention.As shown in figure 3, this A kind of clock count device based on CPLD that inventive embodiments provide, including:
Initial module 10, for obtaining CPLD event duration, and set according to event duration and characterize the layer for counting the cycle Level.
First counting module 11, started counting up for the counting cycle that lowermost layer characterizes using in level as current period, When counting duration and reaching the object count cycle that next level is characterized, using the object count cycle as current period to continue Count, untill the counting cycle phase of top sign in current period and level is same.
Second counting module 12, for continuing to count to reach event duration according to current period.
Clock count device provided by the present invention based on CPLD, the duration counted according to required for CPLD event, Counting cycle level of the setting for the duration.Because each level correspond to count the cycle, and level is from low to high The corresponding counting cycle, the counting cycle characterized using lowermost layer in the level started as current period from short to long Count, when counting duration reaches the object count cycle that more high-level in the level is characterized, by object count week Phase is as the new current period to continue to count.It can be seen that when often rising a level, the cycle all can be used by counting Increase, accordingly reaching the counts of counting duration will accordingly be reduced, and counts decrease counter while reduction The binary digit required for counts is represented, resource occupation for logic unit in CPLD is reduced with this, ensure that Operating efficiency overall CPLD.
On the basis of embodiment three, the device also includes:
Display module, for obtaining the resource occupation amount of CPLD in counting process, and it is shown to user.
Example IV
The present invention also provides a kind of clock count device based on CPLD, including:
Memory, for storing computer program;
Processor, the step of clock count method based on CPLD described above is realized during for performing computer program.
Clock count device provided by the present invention based on CPLD, the duration counted according to required for CPLD event, Counting cycle level of the setting for the duration.Because each level correspond to count the cycle, and level is from low to high The corresponding counting cycle, the counting cycle characterized using lowermost layer in the level started as current period from short to long Count, when counting duration reaches the object count cycle that more high-level in the level is characterized, by object count week Phase is as the new current period to continue to count.It can be seen that when often rising a level, the cycle all can be used by counting Increase, accordingly reaching the counts of counting duration will accordingly be reduced, and counts decrease counter while reduction The binary digit required for counts is represented, resource occupation for logic unit in CPLD is reduced with this, ensure that Operating efficiency overall CPLD.
The present invention also provides a kind of computer-readable recording medium, and computer journey is stored with computer-readable recording medium Sequence, the step of clock count method based on CPLD described above is realized when computer program is executed by processor.
The computer-readable recording medium of clock count provided by the present invention based on CPLD, according to CPLD event institute Need the duration counted, counting cycle level of the setting for the duration.Because each level correspond to count the cycle, and And level from low to high corresponding counting cycle, made from short to long by the counting cycle characterized with lowermost layer in the level Started counting up for current period, will when counting duration reaches the object count cycle that more high-level in the level is characterized The object count cycle is as the new current period to continue to count.It can be seen that when often rising a level, counting is used Cycle can all increased, accordingly reach count duration counts will accordingly reduce, counts reduce while The binary digit required for counter expression counts is decreased, the money for logic unit in CPLD is reduced with this Source takes, and ensure that the overall operating efficiencies of CPLD.
Detailed Jie has been carried out to a kind of clock count method, apparatus and medium based on CPLD provided by the present invention above Continue.Each embodiment is described by the way of progressive in specification, and what each embodiment stressed is and other embodiment Difference, between each embodiment identical similar portion mutually referring to.For device disclosed in embodiment, by Corresponded to the method disclosed in Example in it, so description is fairly simple, related part is referring to method part illustration. It should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention, can also be right The present invention carries out some improvement and modification, and these are improved and modification is also fallen into the protection domain of the claims in the present invention.
It should also be noted that, in this manual, such as first and second or the like relational terms be used merely to by One entity or operation make a distinction with another entity or operation, and not necessarily require or imply these entities or operation Between any this actual relation or order be present.Moreover, term " comprising ", "comprising" or its any other variant meaning Covering including for nonexcludability, so that process, method, article or equipment including a series of elements not only include that A little key elements, but also the other element including being not expressly set out, or also include for this process, method, article or The intrinsic key element of equipment.In the absence of more restrictions, the key element limited by sentence "including a ...", is not arranged Except other identical element in the process including the key element, method, article or equipment being also present.

Claims (10)

  1. A kind of 1. clock count method based on CPLD, it is characterised in that including:
    CPLD event duration is obtained, and is set according to the event duration and characterizes the level for counting the cycle;Wherein, the level Including at least two layers, and lowermost layer characterizes the system cycle;The duration for counting the cycle and the rank of the level are positive correlation, In the adjacent level, the counting cycle that higher levels characterize is the whole of the counting cycle that lower-level characterizes Several times;
    The counting cycle characterized using lowermost layer in the level starts counting up as current period, under counting duration and reaching During the object count cycle that one level is characterized, using the object count cycle as current period to continue to count, until work as The counting cycle phase of top sign is with untill in preceding cycle and the level;
    Continue to count according to current period to reach the event duration.
  2. 2. according to the method for claim 1, it is characterised in that the counting characterized with lowermost layer in the level Cycle starts counting up specially as current period:
    Use display look-up table LUT as counter using the counting cycle that lowermost layer in the level characterizes as currently all Phase starts counting up.
  3. 3. according to the method for claim 1, it is characterised in that this method further comprises:
    The resource occupation amount of CPLD described in counting process is obtained, and is shown to user.
  4. 4. according to the method for claim 1, it is characterised in that this method further comprises:
    Resource threshold is set, and judges whether the resource occupation amount exceedes the scope of the resource threshold;
    If it is, carry out abnormal prompt to user.
  5. 5. according to the method for claim 4, it is characterised in that when judging that the resource occupation amount exceedes the resource threshold Scope when, this method further comprises:
    The resource occupation amount is recorded to daily record.
  6. 6. according to the method described in claim 1-5 any one, it is characterised in that the system cycle is specially 20ns.
  7. A kind of 7. clock count device based on CPLD, it is characterised in that including:
    Initial module, for obtaining CPLD event duration, and set according to the event duration and characterize the level for counting the cycle;
    First counting module, start as current period by the counting cycle that lowermost layer characterizes using in the level in terms of Number, when counting duration reaches the object count cycle that next level is characterized, using the object count cycle as current week Phase to continue to count, until top sign in current period and the level the counting cycle phase with untill;
    Second counting module, for continuing to count to reach the event duration according to current period.
  8. 8. device according to claim 7, it is characterised in that the device further comprises:
    Display module, for obtaining the resource occupation amount of CPLD described in counting process, and it is shown to user.
  9. A kind of 9. clock count device based on CPLD, it is characterised in that including:
    Memory, for storing computer program;
    Processor, realize during for performing the computer program as described in any one of claim 1 to 6 based on CPLD when The step of clock method of counting.
  10. 10. a kind of computer-readable recording medium, it is characterised in that be stored with computer on the computer-readable recording medium Program, the clock based on CPLD as described in any one of claim 1 to 6 is realized when the computer program is executed by processor The step of method of counting.
CN201710977085.2A 2017-10-19 2017-10-19 A kind of clock count method, apparatus and medium based on CPLD Pending CN107659305A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710977085.2A CN107659305A (en) 2017-10-19 2017-10-19 A kind of clock count method, apparatus and medium based on CPLD

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710977085.2A CN107659305A (en) 2017-10-19 2017-10-19 A kind of clock count method, apparatus and medium based on CPLD

Publications (1)

Publication Number Publication Date
CN107659305A true CN107659305A (en) 2018-02-02

Family

ID=61118840

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710977085.2A Pending CN107659305A (en) 2017-10-19 2017-10-19 A kind of clock count method, apparatus and medium based on CPLD

Country Status (1)

Country Link
CN (1) CN107659305A (en)

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1586037A (en) * 2001-11-16 2005-02-23 皇家飞利浦电子股份有限公司 High-speed programmable frequency-divider with synchronous reload
CN1645334A (en) * 2005-01-12 2005-07-27 宁波大学 Timer dispatching method for real-time multi-task operating system
CN1710543A (en) * 2005-06-13 2005-12-21 浙江大学 Two-stage timing method for inlaid real-time operation system timer
CN1963766A (en) * 2006-12-11 2007-05-16 宁波市科技园区菊风系统软件有限公司 A scheduling method for timer
CN101320337A (en) * 2008-07-16 2008-12-10 北京中星微电子有限公司 Timer and its implementing method
CN101491015A (en) * 2006-07-27 2009-07-22 佛罗里达大学研究基金公司 Dynamic tree bitmap for IP lookup and update
CN101833451A (en) * 2010-05-10 2010-09-15 北京航空航天大学 Time strategy representation model and abstract method thereof
CN103019805A (en) * 2011-09-20 2013-04-03 佳都新太科技股份有限公司 Timer setting method under multithreading environment
CN103257670A (en) * 2012-02-21 2013-08-21 北京国微集成技术有限公司 Embedded system and timing method thereof
CN103677976A (en) * 2013-12-09 2014-03-26 大唐移动通信设备有限公司 Event handling method and device based on time wheel timer
CN103777922A (en) * 2012-10-23 2014-05-07 亚德诺半导体技术公司 Prediction counter
CN105630712A (en) * 2014-10-28 2016-06-01 深圳市中兴微电子技术有限公司 Counter and counting method
CN105717979A (en) * 2016-01-29 2016-06-29 山东鲁能智能技术有限公司 Clock device based on timestamp and counters and achieving method thereof
CN105807843A (en) * 2016-03-17 2016-07-27 东莞华芯世纪微电子有限公司 Method for achieving timer/counter and apparatus using method

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1586037A (en) * 2001-11-16 2005-02-23 皇家飞利浦电子股份有限公司 High-speed programmable frequency-divider with synchronous reload
CN1645334A (en) * 2005-01-12 2005-07-27 宁波大学 Timer dispatching method for real-time multi-task operating system
CN1710543A (en) * 2005-06-13 2005-12-21 浙江大学 Two-stage timing method for inlaid real-time operation system timer
CN101491015A (en) * 2006-07-27 2009-07-22 佛罗里达大学研究基金公司 Dynamic tree bitmap for IP lookup and update
CN1963766A (en) * 2006-12-11 2007-05-16 宁波市科技园区菊风系统软件有限公司 A scheduling method for timer
CN101320337A (en) * 2008-07-16 2008-12-10 北京中星微电子有限公司 Timer and its implementing method
CN101833451A (en) * 2010-05-10 2010-09-15 北京航空航天大学 Time strategy representation model and abstract method thereof
CN103019805A (en) * 2011-09-20 2013-04-03 佳都新太科技股份有限公司 Timer setting method under multithreading environment
CN103257670A (en) * 2012-02-21 2013-08-21 北京国微集成技术有限公司 Embedded system and timing method thereof
CN103777922A (en) * 2012-10-23 2014-05-07 亚德诺半导体技术公司 Prediction counter
CN103677976A (en) * 2013-12-09 2014-03-26 大唐移动通信设备有限公司 Event handling method and device based on time wheel timer
CN105630712A (en) * 2014-10-28 2016-06-01 深圳市中兴微电子技术有限公司 Counter and counting method
CN105717979A (en) * 2016-01-29 2016-06-29 山东鲁能智能技术有限公司 Clock device based on timestamp and counters and achieving method thereof
CN105807843A (en) * 2016-03-17 2016-07-27 东莞华芯世纪微电子有限公司 Method for achieving timer/counter and apparatus using method

Similar Documents

Publication Publication Date Title
CN104167789B (en) Charging current method to set up during the transmission of mobile terminal USB data and system
CN103685706B (en) A kind of method that mobile terminal electricity is revised and mobile terminal
DE102004062911A1 (en) Power supply voltage control method in cell phone, involves operating CPU at low operation speed in comparison with operation speed in normal mode until power supply voltage having idle level is increased to normal level
CN103677976B (en) A kind of event-handling method and device based on time wheel timer
CN106055077A (en) Wake-up lock-based processing method and device
WO2014130255A1 (en) State machine for low-noise clocking of high frequency clock
CN104007806A (en) Method and device for controlling CPU frequency in Android system and equipment
CN104239153A (en) Method and device for balancing multi-core CPU load
CN106058983A (en) Charging control circuit, electronic equipment and charging control method
CN104834657A (en) User behavior analysis method and servers
CN105677482A (en) Frequency adjusting method and electronic equipment
CN110083415A (en) Device screen adaptation method, terminal device and storage medium
CN108683155A (en) A kind of converter valve thyristor and capacitance-resistance parameter optimization method and device
CN107659305A (en) A kind of clock count method, apparatus and medium based on CPLD
CN104317542A (en) Method and system for converting frequency of internal storage
CN105917583A (en) Sizing power-gated sections by constraining voltage droop
CN106933673A (en) Adjust the method and device of component logic number of threads
TW201622321A (en) Method for lossless brown-in/brown-out and bleeding resistor removal circuit
CN104834553A (en) Service concurrent processing method for user terminal and user terminal
CN109358942A (en) A kind of method, device and equipment of the monitoring page of adjustment management equipment software
CN210693808U (en) PWM signal level duration detection circuit
CN114142110A (en) Battery control method, device, electronic equipment and storage medium
CN209000517U (en) A kind of adjusting circuit and display device
CN111211615B (en) Medium-voltage intelligent load control method and system for large-scale data center
US7466753B2 (en) Microcontroller having a digital to frequency converter and/or a pulse frequency modulator

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20180202