CN107658275A - The more package modules of stack and its manufacture method - Google Patents
The more package modules of stack and its manufacture method Download PDFInfo
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- CN107658275A CN107658275A CN201710828205.2A CN201710828205A CN107658275A CN 107658275 A CN107658275 A CN 107658275A CN 201710828205 A CN201710828205 A CN 201710828205A CN 107658275 A CN107658275 A CN 107658275A
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- electronic component
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- package modules
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- 238000000034 method Methods 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 230000004888 barrier function Effects 0.000 claims abstract description 107
- 239000000758 substrate Substances 0.000 claims abstract description 76
- 230000005611 electricity Effects 0.000 claims description 7
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 55
- 239000000463 material Substances 0.000 description 23
- 239000003292 glue Substances 0.000 description 13
- 238000005538 encapsulation Methods 0.000 description 12
- 239000000047 product Substances 0.000 description 7
- 229920001187 thermosetting polymer Polymers 0.000 description 7
- 238000004100 electronic packaging Methods 0.000 description 5
- 230000008020 evaporation Effects 0.000 description 5
- 238000001704 evaporation Methods 0.000 description 5
- 238000007733 ion plating Methods 0.000 description 5
- 238000000465 moulding Methods 0.000 description 5
- 238000005507 spraying Methods 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000012943 hotmelt Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000011265 semifinished product Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 239000002322 conducting polymer Substances 0.000 description 1
- 229920001940 conductive polymer Polymers 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011256 inorganic filler Substances 0.000 description 1
- 229910003475 inorganic filler Inorganic materials 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 239000012945 sealing adhesive Substances 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Ceramic Engineering (AREA)
Abstract
The embodiment of the present invention provides a kind of more package modules of stack and its manufacture method, and the manufacture method of the more package modules of stack includes at least one first electronic component being installed on a substrate.One conductive layer is configured on one first insulating barrier.First insulating barrier is covered in first electronic component and local complexity on the substrate surface.Separately at least one first electronic component is installed on first insulating barrier and is electrically connected with the conductive layer.And one second insulating barrier is covered on first electronic component and the substrate surface.
Description
The present invention is a divisional application, and the applying date of original application is on 05 31st, 2013, Application No.
It is 201310214754.2 entitled：The more package modules of stack and its manufacture method.
Technical field
The present invention is related to a kind of more package modules of stack, and in particular to the stack with the first insulating barrier
More package modules.
Background technology
Common Electronic Packaging module generally includes packaged type stacked structure (Package Stacking) at present, and in order to
Improve the stacking density of overall Electronic Packaging module and reduce the volume of encapsulation, usual Electronic Packaging module is hung down using three-dimensional
The straight combination for stacking (Vertically Integrated Circuits, VIC) is integrated.
When the electronic component for running into different height is electrically connected on substrate, to improve the heap of overall Electronic Packaging module
Folded density, existing three-dimensional perpendicular stacking method are generally initially formed molding coated electric components with mould, then will be highly relatively low
Electronic component above molding material pothole is dug out using the advance installation position as electronic component with laser, then in molding
Conductive pole and circuit are produced in pothole, electronic component is then put in molding pothole and to insert another sealing to fill out
Complementary modulus seals pothole.
In general, as the miniaturization of Electronic Packaging module, the ornaments mode and Making programme of electronic component are also got over
Become complicated, manufacture difficulty is also lifted therewith.In addition, such a method easily has the problems such as appearance color difference and bad planarization.
The content of the invention
A kind of more package modules of stack of present invention offer, the flow that its insulating barrier encapsulates to simplification, with
And the inside of the increase more package modules of stack stacks space availability ratio.
The more package modules of stack of the present invention, including substrate, stacked structure and at least one second electronic component；Stack
Structure includes multiple first electronic components, at least one first insulating barrier and an at least conductive pattern layer, which part some
One electronic component is installed on substrate, and the first insulating barrier is covered in some first electronic components of part and local complexity substrate
Surface, conductive pattern layer are configured on the first insulating barrier, and the electronic component of other first is installed on the first insulating barrier and
It is electrically connected with conductive pattern layer；Second electronic component is installed on substrate, and the height of the second electronic component be more than this first
The height of electronic component.
The present invention provides a kind of manufacture method of the more package modules of stack, to simplify the flow of encapsulation and increase heap
The inside of the more package modules of stacked stacks space availability ratio.
The manufacture method of the more package modules of stack of the present invention, including installing at least one first electronic component and at least
One second electronic component is on substrate, and first, second electronic component is connected with electrical property of substrate, and the second electronic component is highly big
In the height of first electronic component；After conductive layer is configured on the first insulating barrier, the first insulating barrier is covered in
One electronic component and local complexity are on substrate surface.Form at least one conduction for penetrating conductive layer and the first insulating barrier
Post, and conductive layer is subjected to patterned process, a conductive pattern layer is formed according to this；Separately it will install at least one first electronic component
It is electrically connected with the first insulating barrier and with conductive pattern layer.
In summary, the more package modules of stack of the invention, its second electronic component are highly more than the first electronic component
Height so that can have a difference in height between the first electronic component and the second electronic component.Some of first electronic components
And second electronic component be installed on substrate, and the first insulating barrier attach be covered in a portion the first electronic component and
On partial substrate.Technique is relatively simple, so as to simplify the flow of encapsulation.When the first insulating barrier covers these the first electronic components
And when on part substrate, will there be space above these first electronic components to house other first electronic components.Accordingly, no
The flow of encapsulation can only be simplified and shorten signal wire path, so that line loss and interference are reduced, product is electrically more preferably.
In addition, the encapsulation planarization of the more package modules of stack is high and appearance color is homogeneous, and the inside heap of the more package modules of stack
Folded space availability ratio is increased.
In addition, the manufacture method of the more package modules of stack of the invention, its second electronic component are highly more than the
The height of one electronic component so that can have a difference in height between the first electronic component and the second electronic component.By attaching the
One insulating barrier is covered on first electronic component and partial substrate of a portion, on these first electronic components
The space content of side puts other the first electronic components.Accordingly, it can not only simplify the flow of encapsulation and shorten signal wire path, from
And make it that line loss and interference are reduced, product is electrically more preferably.In addition, the encapsulation planarization of the more package modules of stack is high and outer
It is homogeneous to see color, and the inside of the more package modules of stack stacks space availability ratio and is increased.
In order to be further understood that the present invention to reach technology, method and effect that set purpose is taken, refers to
Below in connection with detailed description of the invention, schema, it is believed that the purpose of the present invention, feature and feature, when can thus be able to deeply and
It is specific to understand, but institute's accompanying drawings are only provided with annex and used with reference to explanation, are not used for the present invention person of being any limitation as.
Brief description of the drawings
Fig. 1 is the structural representation of the more package modules of stack of first embodiment of the invention.
Fig. 2 is the structural representation of the more package modules of stack of second embodiment of the invention.
Fig. 3 is the schematic flow sheet of the manufacture method of the more package modules of stack of the embodiment of the present invention.
Fig. 4 A~4F are the manufacture method of the stacked package module of first embodiment of the invention respectively in each step institute shape
Into semi-finished product schematic diagram.
Wherein, description of reference numerals is as follows：
100th, the more package modules of 200 stacks
110 substrates
112 ground mats
120th, 220 stacked structure
122nd, the electronic component of 122', 122a, 122b, 122c, 122a', 122b'122c' first
124th, the insulating barriers of 124' first
125 conductive layers
126th, 126' conductive pattern layers
127th, 127' guide holes
130 second electronic components
140 second insulating barriers
150 ELECTROMAGNETIC OBSCURANT layers
D1 cutters
S101~S106 steps flow charts
Embodiment
Fig. 1 is the structural representation of the more package modules of stack of first embodiment of the invention.Referring to Fig. 1, stack
More package modules 100 include substrate 110, stacked structure 120 and at least one second electronic component 130.Stacked structure 120 configures
On substrate 110, and the second electronic component 130 installs (mount) on substrate 110.
Connection pad (boding pad), ground mat (grounding pad) 112 and circuit are commonly configured with substrate 110
(trace) (do not illustrate).In the support plate (carrier) that in practice, substrate 110 is configured by circuit and various electronic components, and
These connection pads and circuit can be set according to needs are electrically connected with.
Stacked structure 120 includes multiple first electronic components 122, at least the first insulating barrier 124 and an at least conductive pattern
Pattern layer 126.Some of first electronic components 122 are installed on substrate 110, and the first insulating barrier 124 is covered in some of them
First electronic component 122 and the surface of local complexity substrate 110, conductive pattern layer 126 are configured on the first insulating barrier 124, and
The first electronic component of other 122 is installed on the first insulating barrier 124 and is electrically connected with conductive pattern layer 126.
First electronic component 122 can include all kinds, and the species of these the first electronic components 122 is not fully
It is identical.Such as first electronic component 122 can be active member or passive device, chip or discrete elements (discrete
Component) etc., as depicted in Fig. 1, the first electronic component 122 can include different species, with the first electronic component
122a, 122b and 122c are represented.But, the present invention is not limited to the species of the first electronic component 122.In addition, first
Electronic component 122a, 122b and 122c can be electrically connected with many ways with substrate 110, e.g. routing mode (wire
Bonding), the connection pad and/or circuit of flip mode (flip chip) or other method for packing and substrate 110 are electrically connected with.
First insulating barrier 124 is covered in first electronic component 122a, 122b and 122c of a portion, and extends and cover
Cover the local surface of substrate 110.First insulating barrier 124 is avoiding producing unnecessary electricity between the first electronic component 122
Property connection.Specifically, the first insulating barrier 124 is a thermosetting sheet glue material, has viscosity at room temperature, attaching and
It is covered on first electronic component 122a, 122b and 122c of a portion.Because the first insulating barrier 124 is sheet glue material,
So as to which the first insulating barrier 124 can be not required to be covered in first electronic component 122a, 122b of a portion by mould
And on 122c, that is to say, that the first insulating barrier 124 is partly taken shape on substrate 110.At a proper temperature, the first insulation
Layer 124 is able to more attach on the first electronic component 122 and substrate 110, and will not be dissolved with heating..It is worth
Illustrate, the material of the first insulating barrier 124 includes epoxy resin (Epoxy resin), inorfil (inorganic
Filler) etc., such as the material of the first insulating barrier 124 can be thermoset hot melt glue glue material (Thermo-melting
sealant sheet)。
In multiple first electronic component 122a, 122b and 122c, wherein the first electronic component of another part
122a', 122b' and 122c' are installed on the first insulating barrier 124, and are electrically connected with conductive pattern layer 126.Briefly,
First electronic component 122a, 122b and 122c of some of them is located within the first insulating barrier 124.First electronics of another part
Element 122a', 122b' and 122c' are located at outside the first insulating barrier 124, and the first electronic component 122' passes through conductive pattern
The circuit of layer 126 is designed and can electrically conducted.
Stacked structure 120 also includes at least one conductive pole 127, and conductive pole 127 penetrates the first insulating barrier 124.Typically
For, conductive pole 127 is interior through extension from conductive pattern layer 126 toward the first insulating barrier 124, and according to different product designs
It is for electrically connecting to different the first electronic component 122 or base plate line.
The more package modules 100 of stack include at least one second electronic component 130, wherein the second electronic component 130 is installed
In on substrate 110, and the height of the second electronic component 130 is more than the height of the first electronic component 122.Similarly, the second electronics member
Part 130 can also include all kinds, e.g. active member or passive device, chip or discrete elements etc..And second is electric
Subcomponent 130 can also be electrically connected with many ways with substrate 110, e.g. routing mode, flip mode or other envelopes
Dress method and the connection pad and/or circuit of substrate 110 are electrically connected with.
The more package modules 100 of stack also include the second insulating barrier 140, and the second insulating barrier 140 is covered in the second electronics member
Part 130, stacked structure 120 and the surface of substrate 110.Second insulating barrier 140 causes the second electronics to reduce moisture intrusion
The infringement of element 130, stacked structure 120 or circuit, and the second insulating barrier 140 can also avoid the second electronic component 130
Between produce unnecessary electric connection.The material of second insulating barrier 140 can be different with the material of the first insulating barrier 124, example
Such as the second insulating barrier 140 can be an adhesive layer, and main material includes pressing mold glue (molding compound), passes through sealing
Technique (encapsulation process) inserts the shaping of die cavity (cavity) baking hardening.Or second insulating barrier 140
Material can be identical with the material of the first insulating barrier 124, is all thermosetting sheet glue material, and the second electricity is covered in a manner of attaching
Subcomponent 130, stacked structure 120 and the surface of substrate 110.But, the present invention is not subject to the material of the second insulating barrier 140
Limit.
In addition, being designed for the ELECTROMAGNETIC OBSCURANT of product, the more package modules 100 of stack also include ELECTROMAGNETIC OBSCURANT layer 150, electricity
Magnetic shielding layer 150 is located at the outer surface of the second insulating barrier 140, and is electrically connected with ground mat 112.ELECTROMAGNETIC OBSCURANT layer 150 is used
To reduce electromagnetic interference effect caused by the electronic component 130 of electronic component 122 and second and Radio frequency interference effect.It is general and
Speech, ELECTROMAGNETIC OBSCURANT layer 150 are made by conductive material, e.g. with metal material, conducting polymer composite either conduction again
Made by condensation material.And ELECTROMAGNETIC OBSCURANT layer 150 can be by spraying (Spray Coating), ion plating (Ion
Plating), the mode such as sputter (Sputter Deposition) or evaporation (Evaporation Deposition) deposits
Conductive film or with metal cover cover in the outer surface of the second insulating barrier 140.
Fig. 2 is the diagrammatic cross-section of the more package modules of stack of second embodiment of the invention.The stacking of second embodiment
Both the more package modules 200 of formula package modules 100 more to the stack of first embodiment structure is similar, and effect is identical, such as heap
The more package modules 200 and 100 of stacked equally all include the first electronic component 122.The more package modules of stack will be only introduced below
Difference both 200 and 100, and then it is no longer repeated for identical feature.
Referring to Fig. 2, the more package modules 200 of the stack of second embodiment include substrate 110, stacked structure 220 and
At least one second electronic component 130.Stacked structure 220 is configured on substrate 110, and the second electronic component 130 is installed
(mount) on substrate 110.
Stacked structure 220 includes multiple first electronic components 122, multiple first insulating barriers 124 and multiple conductive patterns
Layer 126.What deserves to be explained is stacked structure 220 is by multiple first electronic components 122, multiple first insulating barriers 124 and more
Individual conductive pattern layer 126, which stacks, to be formed.
Specifically, some of first electronic component 122a, 122b and 122c are installed on substrate 110, and wherein
One first insulating barrier 124 is covered in these the first electronic component 122a, 122b and 122c and the surface of local complexity substrate 110
On, and a wherein conductive pattern layer 126 is configured on this first insulating barrier 124, and the first electronic component of another part
122a, 122b and 122c are installed on this first insulating barrier 124 and are electrically connected with this conductive pattern layer 126.Another first is exhausted
Edge layer 124' is on the first electronic component 122 and conductive pattern layer 126 is covered in, and another conductive pattern layer 126' is being covered
In on the first insulating barrier 124', and first electronic component 122a', 122b' and 122c' of another part is installed in the first insulation
It is electrically connected with layer 124' and with conductive pattern layer 126'.
Briefly, stacked structure 220 can be sandwich construction, and some of first electronic components 122 are installed in substrate
On 110 and within the first insulating barrier 124, the first electronic component of other 122 is located on the first insulating barrier 124, and
First electronic component 122' is located at outside the first insulating barrier 124'.Conductive pattern layer 126,126' be located at the first insulating barrier 124,
On 124'.
What deserves to be explained is in the present embodiment, stacked structure 220 is double-layer structure.But, in other embodiments,
According to considering for different electric connection designs, stacked structure 220 can be more than two layers of structure.But, the present invention not
This is limited.
Fig. 3 is the schematic flow sheet of the manufacture method of the more package modules of stack of the embodiment of the present invention.A~4F points of Fig. 4
It is not the signal of semi-finished product that the manufacture method of the more package modules of stack of first embodiment of the invention is formed in each step
Figure.Refer to Fig. 3 and sequentially coordinate reference picture 4A~4F.
In step 101, Fig. 4 A are referred to, will at least one first electronic component 122 and at least one second electronic component
130 are installed on substrate 110, and the first electronic component 122 is all electrically connected with the second electronic component 130 with substrate 110, and
The height of second electronic component 130 is more than the height of the first electronic component 122.What deserves to be explained is in this, highly it is defined as installing
The first electronic component 122 and the bottom surface of the second electronic component 130 afterwards extends vertically distance to top surface.Due to the second electronics
The height of element 130 is more than the height of the first electronic component 122, therefore, in the first electronic component 122 and the second electronic component 130
Between can have a difference in height.
Specifically, there is provided substrate 110, substrate 110 can be circuit yoke plate (circuit substrate panel or
Circuit substrate strip) (Fig. 4 A only illustrate a part for substrate 110).At least one first is installed on substrate 110
Electronic component 122 and at least one second electronic component 130, in the present embodiment, there is provided multiple first electronic component 122a,
122b and 122c and multiple second electronic components 130, wherein the first electronic component 122 and the second electronic component 130 can be with
It is active member or passive device, chip or discrete elements etc., and can be electrically connected with many ways with substrate 110, such as
It is routing mode (wire bonding), flip mode (flip chip) or the connection pad and/or line of other method for packing and substrate
Road is electrically connected with.
In step 102, Fig. 4 B are referred to, conductive layer 125 is configured on the first insulating barrier 124.Conductive layer 125 can
With by spraying (Spray Coating), ion plating (Ion Plating), sputter (Sputter Deposition) either
Metal material or conductive material are formed at the upper of the first insulating barrier 124 by the modes such as evaporation (Evaporation Deposition)
Surface.
In step 103, Fig. 4 C are referred to, it is exhausted by first after conductive layer 125 is configured on the first insulating barrier 124
Edge layer 124 is covered in the first electronic component 122 and local complexity on the surface of substrate 110.What deserves to be explained is the first insulation
Layer 124 is a thermosetting sheet glue material, and in the present embodiment, the material of the first insulating barrier 124 can be thermoset hot melt glue glue
Material, it is covered in by way of attaching on first electronic component 122 and partial substrate 110 of a portion, that is,
Say, the first insulating barrier 124 is partly taken shape on substrate 110.
In step 104, Fig. 4 D are referred to, form at least one conduction for penetrating the insulating barrier 124 of conductive layer 125 and first
Post 127, and conductive layer 125 is subjected to patterned process, conductive pattern layer 126 is formed according to this.Specifically, using laser pair
The insulating barrier 124 of conductive layer 125 and first is drilled, so that the first insulating barrier 124 forms an at least hollow via-hole, then,
Conductive material is formed in forming conductive pole 127 in hollow via-hole according to this, conductive pole 127 is from conductive layer 125 toward the first insulating barrier 124
It is interior to run through extension.What deserves to be explained is can according to different electric connection demands and designed, designed each conductive pole 127
Shape, quantity are with distributing position.Then, patterned process is carried out to conductive layer 125, to form conductive pattern layer 126.In detail and
Speech, can use laser ablation conductive layer, so that conductive layer 125 forms conductive pattern.
In addition, it should be noted that, considered in order to technologic, form conductive pole 127 and pattern is carried out to conductive layer 125
The step of changing processing order can be while or sequentially exchange.The present invention is limited not to this.
In step 105, Fig. 4 E are referred to, by separately at least one first electronic component 122' is installed in the first insulating barrier 124
Above and with conductive pattern layer 126 it is electrically connected with.In the present embodiment, there is provided multiple first electronic component 122a', 122b' and
122c', and first electronic component 122a', 122b' and 122c' that these are installed on the first insulating barrier 124 can pass through conduction
Patterned layer 126 and conductive pole 127 and the first electronic component 122 or the second electronic component 130 with being installed on substrate 110
It is electrically connected with.
What deserves to be explained is due to having difference in height between the first electronic component 122 and the second electronic component 130, therefore
When some of first electronic components 122 and the second electronic component 130 are installed on substrate 110, these first electronic components
Will there be space 122 tops to house other first electronic components 122.
Infringement and the guarantor of the second electronic component 130, stacked structure 120 or circuit are caused in order to reduce moisture intrusion
Protect between the second electronic component 130 and produce unnecessary electric connection, the manufacture method of the more package modules 100 of stack also includes
Second insulating barrier 140 is covered on stacked structure 120, the second electronic component 130 and the surface of substrate 110.
In step 106, Fig. 4 F are referred to, the second insulating barrier 140 is covered in stacked structure 120 and the surface of substrate 110
On.In general, the second insulating barrier 140 can be an adhesive layer, main material includes pressing mold glue.By sealing adhesive process, by
The material of two insulating barrier 140 is inserted in die cavity, via baking hardening is molded again after plastic squeeze, injecting glue.In addition, in other embodiments,
The material of second insulating barrier 140 can also be identical with the material of the first insulating barrier 124, that is, the material of the second insulating barrier 140 is
Thermosetting sheet glue material, and the second electronic component 130, stacked structure 120 and the table of substrate 110 are covered in a manner of attaching
Face.Also the second insulating barrier 140 can need not be made in practical application of the present invention.
Then, substrate 110 is cut into multiple units by cutter D1 or using laser.This cutting can be hemisection,
All cut off i.e. without by molding unit 130 and substrate 110, and again all cut the substrate 110 of hemisection when final step
It is disconnected.Or cutting can be cut entirely, i.e., once substrate 110 is all cut off.
Referring to Fig. 1, designed for the ELECTROMAGNETIC OBSCURANT of product, the manufacture method of the more package modules 100 of stack is also
It is electrically connected with including forming ELECTROMAGNETIC OBSCURANT layer 150 in the outer surface of the second insulating barrier 140, and with ground mat 112.ELECTROMAGNETIC OBSCURANT
Layer 150 can be that the conductive film made by conductive material is deposited by modes such as spraying, ion plating, sputter or evaporations.
Or ELECTROMAGNETIC OBSCURANT layer 150 can also be in the outer surface of the second insulating barrier 140 with metal cover cover.Via above-mentioned steps, heap
Stacked package module 100 has substantially been formed
In summary, the embodiment of the present invention provides a kind of more package modules of stack, and its second electronic component is highly more than
The height of first electronic component so that can have a difference in height between the first electronic component and the second electronic component.It is some of
First electronic component and the second electronic component are installed on substrate, and the first insulating barrier is thermosetting sheet glue material, is not required to pass through
Mould and attach and be covered on first electronic component and partial substrate of a portion.Therefore, technique is relatively simple, from
And simplify the flow of encapsulation.When the first insulating barrier is covered on these first electronic components and part substrate, these first electricity
To there be space above subcomponent to house other first electronic components.Accordingly, flow and the shortening of encapsulation can not only be simplified
Signal wire path, so that line loss and interference are reduced, product is electrically more preferably.In addition, the envelope of the more package modules of stack
Fill planarization height and appearance color is homogeneous, and the inside of the more package modules of stack stacks space availability ratio and is increased.
In addition, the embodiment of the present invention provides the manufacture method of the more package modules of stack, and its second electronic component is high
Height of the degree more than the first electronic component so that can have a difference in height between the first electronic component and the second electronic component.It is logical
Cross the first insulating barrier of attaching to be covered on first electronic component and partial substrate of a portion, then at these the first electricity
Space content above subcomponent puts other the first electronic components.Accordingly, it can not only simplify the flow of encapsulation and shorten signal
Thread path, so that line loss and interference are reduced, product is electrically more preferably.In addition, the encapsulation of the more package modules of stack is put down
Whole property is high and appearance color is homogeneous, and the inside of the more package modules of stack stacks space availability ratio and is increased.
Embodiments of the invention are the foregoing is only, it is not limited to the claims of the present invention.Appoint
What those skilled in the art, is not departing from spirit and scope of the invention, the change made and the equivalence replacement of retouching, still for
In the claims of the present invention.
Claims (13)
1. a kind of more package modules of stack, it is characterised in that the more package modules of the stack include：
One substrate；
At least one first insulating barrier, the local complexity substrate surface；
An at least conductive pattern layer, it is configured on first insulating barrier；
Multiple first electronic components, the plurality of first electronic component in part are covered by least one first insulating barrier, and in addition should
Multiple first electronic components are installed on first insulating barrier and are electrically connected with the conductive pattern layer；And
One second insulating barrier, cover the plurality of first electronic component in the part and at least one first insulating barrier, be exposed to
The substrate surface of at least one first insulating barrier.
It is exhausted that 2. the more package modules of stack as claimed in claim 1, the wherein more package modules of the stack include multiple first
Edge layer and multiple conductive pattern layers, wherein the conductive pattern layer is located therein between 2 first insulating barriers, and this is more in addition
Individual first electronic component is located therein on first insulating barrier and is electrically connected with the conductive pattern layer.
3. the more package modules of stack as claimed in claim 1, in addition at least one second electronic component, second electronics member
Part is installed on the substrate.
4. the more package modules of stack as claimed in claim 3, the wherein height of second electronic component are more than first electricity
The height of subcomponent.
5. the more package modules of stack as claimed in claim 1, in addition to an at least conductive pole, the conductive pole penetrate this first
Insulating barrier.
6. a kind of more package modules of stack, it is characterised in that the more package modules of the stack include：
One substrate；
Stacked arrangement, including multiple first electronic components and at least one first insulating barrier, the plurality of first electronics of which part
Element is installed on the substrate, and first insulating barrier is covered in the plurality of first electronic component in part, and in addition the plurality of first
Electronic component is installed on first insulating barrier；
One second insulating barrier, cover the plurality of first electronic component in the part and at least one first insulating barrier；And
One ELECTROMAGNETIC OBSCURANT layer, positioned at an outer surface of second insulating barrier, and first insulating barrier is not contacted.
7. the more package modules of stack as claimed in claim 6, in addition at least one second electronic component, second electronics member
Part is installed on the substrate, and the height of second electronic component is more than the height of first electronic component.
8. the more package modules of stack as claimed in claim 7, the wherein height of second electronic component are more than first electricity
The height of subcomponent.
9. the more package modules of stack as claimed in claim 7, wherein second electronic component separate the ELECTROMAGNETIC OBSCURANT layer and
First insulating barrier.
A kind of 10. manufacture method of the more package modules of stack, it is characterised in that the manufacture method of the more package modules of the stack
Including：
At least one first electronic component is installed on a substrate；
One conductive layer is configured on one first insulating barrier；
First insulating barrier is covered in first electronic component and local complexity on the substrate surface；
Separately at least one first electronic component is installed on first insulating barrier and is electrically connected with the conductive layer；And
One second insulating barrier is covered on first electronic component and the substrate surface.
11. the manufacture method of the more package modules of stack as claimed in claim 10, in addition to：
Form at least one conductive pole for penetrating the conductive layer and first insulating barrier；And
The conductive layer is subjected to patterned process, forms a conductive pattern layer according to this.
12. the manufacture method of the more package modules of stack as claimed in claim 10, in addition to：
At least one second electronic component is installed on the substrate, second insulating barrier is covered second electronic component.
13. the manufacture method of the more package modules of stack as claimed in claim 10, the wherein more package modules of the stack
Manufacture method also includes being formed an ELECTROMAGNETIC OBSCURANT layer in the outer surface of second insulating barrier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710828205.2A CN107658275A (en) | 2013-05-31 | 2013-05-31 | The more package modules of stack and its manufacture method |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310214754.2A CN104218030B (en) | 2013-05-31 | 2013-05-31 | The many package modules of stack and its manufacture method |
| CN201710828205.2A CN107658275A (en) | 2013-05-31 | 2013-05-31 | The more package modules of stack and its manufacture method |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201310214754.2A Division CN104218030B (en) | 2013-05-31 | 2013-05-31 | The many package modules of stack and its manufacture method |
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| CN107658275A true CN107658275A (en) | 2018-02-02 |
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| CN201310214754.2A Active CN104218030B (en) | 2013-05-31 | 2013-05-31 | The many package modules of stack and its manufacture method |
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Cited By (1)
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|---|---|---|---|---|
| CN112071811A (en) * | 2020-09-18 | 2020-12-11 | 环维电子(上海)有限公司 | Semiconductor package and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11908781B2 (en) | 2021-03-22 | 2024-02-20 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and a method of manufacturing the same |
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| CN104218030A (en) | 2014-12-17 |
| CN104218030B (en) | 2017-09-26 |
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