CN107658263A - A kind of vertical interconnected method of three-dimensional silicon hole based on carbon nanomaterial composite construction - Google Patents
A kind of vertical interconnected method of three-dimensional silicon hole based on carbon nanomaterial composite construction Download PDFInfo
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- CN107658263A CN107658263A CN201710900247.2A CN201710900247A CN107658263A CN 107658263 A CN107658263 A CN 107658263A CN 201710900247 A CN201710900247 A CN 201710900247A CN 107658263 A CN107658263 A CN 107658263A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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Abstract
The invention discloses a kind of vertical interconnected method of three-dimensional silicon hole based on carbon nanomaterial composite construction, silicon hole is made on a silicon substrate；In silicon substrate surface and silicon hole inwall depositing insulating layer；Barrier layer is deposited on the insulating layer, over the barrier layer deposition of catalytic metals layer；Catalyzing metal layer is etched, forms catalyzing nano-particles；Carbon nanomaterial composite bed is grown using catalyzing nano-particles；Carbon nanomaterial composite construction layer surface patch dry film on a silicon substrate, exposure, development form photopolymer layer；The deposited seed layer on silicon hole bottom surface and dry film layer surface；Conductive material is filled in silicon hole.The present invention solves the thermal stress mismatch problems between the heat dissipation problem and encapsulating material of the TSV encapsulating structures as caused by increasing power density, improves the thermal conductivity and package reliability of 3D TSV structures using the good calorifics of carbon nanomaterial and mechanical performance.
Description
Technical field
The present invention relates to a kind of vertical interconnected method of silicon hole, and in particular to a kind of based on carbon nanomaterial composite construction
The vertical interconnected method of three-dimensional silicon hole, belongs to microelectronic packaging technology field.
Background technology
As the enhancing of integrated circuit (IC, Integrated Circuit) chip functions, size reduction, energy consumption and cost drop
Low, microelectronic packaging technology is faced with new challenges.In order to meet the requirement of IC products, three-dimensional packaging technology is arisen at the historic moment.Silicon
Through hole vertically interconnects (TSV, Through Silicon Via) technology by two layers and more layers device die or whole silicon wafer
By many vertically through electrode Direct Bonding together, realize most short, most abundant z to interconnection.So it can not only improve
Device integration, and interconnection delay can be reduced, improve the device speed of service and reduce power consumption.Therefore TSV technology is considered as not
Carry out one of prevailing technology of encapsulation technology development.
Under 22/16nm technology nodes, TSV interconnecting channels will be changed into highly dense and sufficiently complex three-dimensional microstructures
Group, the raising of packaging density steeply rise the power density of stacked chips, due to aobvious between the thermal coefficient of expansion of encapsulating material
Difference is write, 3D TSV structures are faced with serious heat dissipation problem, and silicon/copper thermal stress mismatch problems are also more prominent.TSV is caused to tie
Larger thermal stress be present in technological temperature and at a temperature of being on active service in structure.The stress migration occurred under technique residual stress, promotes
Room is produced in metal, and moved along stress gradient direction, assemble formation cavity, ultimately results in interconnection open circuit；Technical process is tired out
Thermal stress superposition at a temperature of long-pending residual stress and military service in TSV structure so that stress situation is increasingly complex in TSV structure,
Serious thermal stress mismatch will cause TSV interconnection structures to fail.
The content of the invention
In view of the above-mentioned problems of the prior art, the present invention provides a kind of three-dimensional based on carbon nanomaterial composite construction
The vertical interconnected method of silicon hole, between the heat dissipation problem and encapsulating material that solve the TSV encapsulating structures as caused by increasing power density
Thermal stress mismatch problems.
To achieve these goals, the technical solution adopted by the present invention is：It is a kind of based on carbon nanomaterial composite construction
The vertical interconnected method of three-dimensional silicon hole, comprises the following steps：
A. silicon hole is made on a silicon substrate；
B. in silicon substrate surface and silicon hole inwall depositing insulating layer；
C. barrier layer is deposited on the insulating layer, over the barrier layer deposition of catalytic metals layer；
D. catalyzing metal layer is etched, forms nano-catalytic metallic particles；
E. nano-catalytic metallic particles growth carbon nanomaterial composite construction layer is utilized；
F. carbon nanomaterial composite construction layer surface patch dry film on a silicon substrate, exposure, development form photopolymer layer；
G. the deposited seed layer on silicon hole bottom surface and dry film layer surface；
H. conductive material is filled in silicon hole.
Further, catalyzing metal layer is made using ion beam sputtering or physical vaporous deposition in the step c,
Catalytic metal layer material is cobalt or iron.
Further, catalyzing nano-particles using plasma etching method makes in the step d, and etching gas use hydrogen
Gas or argon gas.
Further, carbon nanomaterial composite construction layer is grown in the step e to make using thermal chemical vapor deposition method,
Carbon-source gas use methane, stable in 1kPa as protective gas, total gas pressure using hydrogen.
Further, carbon nanomaterial composite construction Rotating fields are grown in the step e to be divided into two layers, upper strata is horizontal
Multi-layer graphene, lower floor are vertical carbon nano pipe array.
Further, the bore dia of photopolymer layer is less than silicon hole diameter in the step f and the hole of photopolymer layer and silicon hole are coaxial.
Further, it is that guiding fills conductive material to carrying out plating in silicon hole using Seed Layer in the step h.
The present invention on a silicon substrate then receive for perforate by priority depositing insulating layer, barrier layer, growth carbon compared with prior art
Rice Material cladding structure sheaf, dry film is pasted, conductive material is filled after deposited seed layer, utilizes carbon nano-tube bundle good calorifics and machine
Tool performance, solves the thermal stress mismatch between the heat dissipation problem and encapsulating material of the TSV encapsulating structures as caused by increasing power density
Problem, improve the thermal conductivity and package reliability of 3D-TSV structures.
Brief description of the drawings
Fig. 1 is the structural representation that the present invention makes silicon hole；
Fig. 2 is the structural representation of priority depositing insulating layer of the present invention, barrier layer and catalyzing metal layer；
Fig. 3 is present invention etching catalyzing metal layer, forms the structural representation of nano-catalytic metallic particles；
Fig. 4 is the structural representation of present invention growth carbon nanomaterial composite construction layer；
Fig. 5 is the structural representation of carbon nanomaterial composite construction layer；
Fig. 6 is the structural representation of present invention patch photopolymer layer；
Fig. 7 is deposited seed layer of the present invention and fills the structural representation of conductive material；
Fig. 8 is carbon nanomaterial composite construction layer thermal stress buffering schematic diagram of the present invention.
In figure：1st, silicon chip, 2, insulating barrier, 3, barrier layer, 4, catalyzing metal layer, 5, carbon nanomaterial composite construction layer,
6th, photopolymer layer, 7, Seed Layer, 8, conductive material, 9, silicon hole.
Embodiment
The invention will be further described below in conjunction with the accompanying drawings.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
As shown in fig. 7, the present invention comprises the following steps：
A. silicon hole 9 is made on silicon chip 1；
B. in the surface of silicon chip 1 and the inwall depositing insulating layer 2 of silicon hole 9；
C. barrier layer 3, the deposition of catalytic metals layer 4 on barrier layer 3 are deposited on insulating barrier 2；
D. catalyzing metal layer 4 is etched, forms catalyzing nano-particles；
E. nano-catalytic metallic particles growth carbon nanomaterial composite construction layer 5 is utilized；
F. the surface of the carbon nanomaterial composite construction layer 5 patch dry film on silicon chip 1, exposure, development form photopolymer layer 6；
G. the deposited seed layer 7 on the bottom surface of silicon hole 9 and the surface of photopolymer layer 6；
H. the filling conductive material 8 in silicon hole 9.
Embodiment：
As shown in figure 1, made on silicon chip 1 using deep reactive ion etching method, laser ablation method or wet etching method etching
Silicon hole 9；A diameter of 1-100 microns of silicon hole 9, the cross section of silicon hole 9 is generally circular in cross section, and the depth-to-width ratio of silicon hole 9 is generally 1~
30。
As shown in Fig. 2 on the surface of silicon chip 1 and the inwall of silicon hole 9 (periphery and bottom surface) growth insulating barrier 2, insulating barrier 2
Deposition made using thermal oxide, chemical vapor deposition or physical gas-phase deposite method, the material of insulating barrier 2 can select two
The inorganic matters such as silica, aluminum oxide or silicon nitride, the thickness of insulating barrier 2 is 0.5-1 microns；Deposit and stop on insulating barrier 2
Layer 3, the deposition on barrier layer 3 are made using physical vapour deposition (PVD) or chemical vapour deposition technique, and the material on barrier layer 3 can select
Titanium, titanium nitride, tantalum, tantalum nitride etc., the thickness on barrier layer 3 is 50-100 nanometers；Deposition of catalytic metals layer 4, is urged on barrier layer 3
Change metal level 4 to make using ion beam sputtering or physical vaporous deposition, material typically selects cobalt or iron, catalytic metal
The thickness of layer 4 is 2-5 nanometers.
As shown in figure 3, using plasma etching method etches catalyzing metal layer 4, catalyzing nano-particles are formed；Etching gas
Using hydrogen or argon gas, plasma power density is 0.1-0.5 (W/cm2), minute time 0.5-3.
As shown in figure 4, in the superficial growth carbon nanomaterial composite construction layer 5 of catalyzing metal layer 4；Growth technique uses thermalization
Learn CVD method to make, carbon-source gas use methane, using hydrogen as protective gas, total gas pressure stabilization exist
1kPa, growth temperature are 450-600 DEG C；The growth of carbon nanomaterial composite construction layer 5 separates out stone from catalytic metal cobalt first
Black alkene layer, carbon nanomaterial composite construction layer 5 is then synthesized from cobalt nano-particle according to tip growing mode, as shown in figure 5, raw
The structure of carbon nanomaterial composite construction layer 5 after length is that upper strata is graphene layer, and lower floor is carbon nano-tube bundle array.
As shown in fig. 6, the surface of the carbon nanomaterial composite construction layer 5 patch dry film on silicon chip 1, by exposing, developing
The structure of silicon hole 9 is exposed, multilayer dry film is then affixed on by the surface of silicon chip 1 using hot-press method, is exposed using litho machine,
Silicon chip 1 after exposure is positioned in developer solution, removes part dry film, forms the photopolymer layer 6 for needing pattern, photopolymer layer 6
Bore dia is less than the diameter of silicon hole 9 and the hole of photopolymer layer 6 and silicon hole 9 are coaxial.
As shown in fig. 7, the deposited seed layer 7 on the bottom surface of silicon hole 9 and the surface of photopolymer layer 6, Seed Layer 7 are to be with photopolymer layer 6
Mask, it is deposited on using electron beam evaporation or magnetically controlled sputter method on the bottom surface of silicon hole 9 and the surface of photopolymer layer 6, the material of Seed Layer 7
Material is typically from gold or copper；Adopted with Seed Layer 7 for guiding to carrying out plating filling conductive material 8, conductive material 8 in silicon hole 9
It is filled with electro-plating method, conductive material 8 is usually copper；Inhibitor and accelerator are added in electroplate liquid, realizes conduction material
Material 8 " from bottom and on " high speed, high quality filling.
As shown in figure 8, TSV channel bottoms are removed by cmp technology after the completion of filling and realize planarization.
No matter in the case of process conditions or military service, the heat in TSV passages can be by carbon nanomaterial composite construction layer 5 rapidly upward
Lower and left and right transmission, accelerates thermal diffusion；Meanwhile carbon nanomaterial composite construction layer 5 as packing material 8 thermal stress release and
Cushion, avoid thermal stress mismatch serious between packing material 8 and the silicon chip 1 of insulating barrier 2/ and cause TSV interconnections defect very
To the situation of failure.
It is obvious to a person skilled in the art that the invention is not restricted to the details of above-mentioned one exemplary embodiment, Er Qie
In the case of without departing substantially from spirit or essential attributes of the invention, the present invention can be realized in other specific forms.Therefore, no matter
From the point of view of which point, embodiment all should be regarded as exemplary, and be nonrestrictive, the scope of the present invention is by appended power
Profit requires rather than described above limits, it is intended that all in the implication and scope of the equivalency of claim by falling
Change is included in the present invention.Any reference in claim should not be considered as to the involved claim of limitation.
Described above, only presently preferred embodiments of the present invention is not intended to limit the invention, every skill according to the present invention
Any trickle amendment, equivalent substitution and the improvement that art is substantially made to above example, should be included in technical solution of the present invention
Protection domain within.
Claims (7)
1. a kind of vertical interconnected method of three-dimensional silicon hole based on carbon nanomaterial composite construction, it is characterised in that including following
Step：
A. silicon hole (9) is made on silicon chip (1)；
B. in silicon chip (1) surface and silicon hole (9) inwall depositing insulating layer (2)；
C. barrier layer (3) are deposited on insulating barrier (2), the deposition of catalytic metals layer (4) on barrier layer (3)；
D. catalyzing metal layer (4) is etched, forms nano-catalytic metallic particles；
E. nano-catalytic metallic particles growth carbon nanomaterial composite construction layer (5) is utilized；
F. carbon nanomaterial composite construction layer (5) surface patch dry film on silicon chip (1), exposure, development form photopolymer layer
(6)；
G. the deposited seed layer (7) on silicon hole (9) bottom surface and photopolymer layer (6) surface；
H. the filling conductive material (8) in silicon hole (9).
2. a kind of vertical interconnected method of three-dimensional silicon hole based on carbon nanomaterial composite construction according to claim 1,
Characterized in that, catalyzing metal layer (4) is made using ion beam sputtering or physical vaporous deposition in the step c, urge
It is cobalt or iron to change metal level (4) material.
3. a kind of vertical interconnected method of three-dimensional silicon hole based on carbon nanomaterial composite construction according to claim 1,
Characterized in that, catalyzing nano-particles using plasma etching method makes in the step d, etching gas using hydrogen or
Argon gas.
4. a kind of vertical interconnected method of three-dimensional silicon hole based on carbon nanomaterial composite construction according to claim 1,
Made characterized in that, growing carbon nanomaterial composite construction layer (5) in the step e using thermal chemical vapor deposition method, carbon
Source gas uses methane, stable in 1kPa as protective gas, total gas pressure using hydrogen.
5. a kind of vertical interconnected method of three-dimensional silicon hole based on carbon nanomaterial composite construction according to claim 1,
It is divided into two layers characterized in that, growing carbon nanomaterial composite construction layer (5) structure in the step e, upper strata is horizontal more
Layer graphene, lower floor are vertical carbon nano pipe array.
6. a kind of vertical interconnected method of three-dimensional silicon hole based on carbon nanomaterial composite construction according to claim 1,
Characterized in that, the bore dia of photopolymer layer (6) is less than silicon hole (9) diameter in the step f.
7. a kind of vertical interconnected method of three-dimensional silicon hole based on carbon nanomaterial composite construction according to claim 1,
Characterized in that, conductive material (8) is filled to carrying out plating in silicon hole (9) for guiding with Seed Layer (7) in the step h.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710900247.2A CN107658263B (en) | 2017-09-28 | 2017-09-28 | Three-dimensional through silicon via vertical interconnection method based on carbon nano material composite structure |
| PCT/CN2018/000016 WO2019061926A1 (en) | 2017-09-28 | 2018-01-15 | Carbon nano-material composite structure-based three-dimensional silicon through-hole vertical interconnection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710900247.2A CN107658263B (en) | 2017-09-28 | 2017-09-28 | Three-dimensional through silicon via vertical interconnection method based on carbon nano material composite structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107658263A true CN107658263A (en) | 2018-02-02 |
| CN107658263B CN107658263B (en) | 2021-01-22 |
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| CN201710900247.2A Active CN107658263B (en) | 2017-09-28 | 2017-09-28 | Three-dimensional through silicon via vertical interconnection method based on carbon nano material composite structure |
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| CN (1) | CN107658263B (en) |
| WO (1) | WO2019061926A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109524513A (en) * | 2018-11-23 | 2019-03-26 | 江苏新广联半导体有限公司 | A kind of silicon substrate flip LED chips and preparation method thereof |
| CN116435290A (en) * | 2023-06-13 | 2023-07-14 | 中诚华隆计算机技术有限公司 | Three-dimensional stacking structure and stacking method of chips |
Citations (5)
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|---|---|---|---|---|
| US20010025962A1 (en) * | 2000-03-31 | 2001-10-04 | Masayuki Nakamoto | Field emmision type cold cathode device, manufacturing method thereof and vacuum micro device |
| US20020163079A1 (en) * | 2001-05-02 | 2002-11-07 | Fujitsu Limited | Integrated circuit device and method of producing the same |
| CN102530931A (en) * | 2011-12-14 | 2012-07-04 | 天津大学 | Graphene-based nano composite material and preparation method thereof |
| CN102569181A (en) * | 2011-12-15 | 2012-07-11 | 中国科学院微电子研究所 | Method for manufacturing vertically interconnecting carbon nanotube bundle |
| CN103258789A (en) * | 2013-04-17 | 2013-08-21 | 华中科技大学 | Manufacturing method of through hole interconnection structure and product of through hole interconnection structure |
-
2017
- 2017-09-28 CN CN201710900247.2A patent/CN107658263B/en active Active
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2018
- 2018-01-15 WO PCT/CN2018/000016 patent/WO2019061926A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010025962A1 (en) * | 2000-03-31 | 2001-10-04 | Masayuki Nakamoto | Field emmision type cold cathode device, manufacturing method thereof and vacuum micro device |
| US20020163079A1 (en) * | 2001-05-02 | 2002-11-07 | Fujitsu Limited | Integrated circuit device and method of producing the same |
| CN102530931A (en) * | 2011-12-14 | 2012-07-04 | 天津大学 | Graphene-based nano composite material and preparation method thereof |
| CN102569181A (en) * | 2011-12-15 | 2012-07-11 | 中国科学院微电子研究所 | Method for manufacturing vertically interconnecting carbon nanotube bundle |
| CN103258789A (en) * | 2013-04-17 | 2013-08-21 | 华中科技大学 | Manufacturing method of through hole interconnection structure and product of through hole interconnection structure |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109524513A (en) * | 2018-11-23 | 2019-03-26 | 江苏新广联半导体有限公司 | A kind of silicon substrate flip LED chips and preparation method thereof |
| CN116435290A (en) * | 2023-06-13 | 2023-07-14 | 中诚华隆计算机技术有限公司 | Three-dimensional stacking structure and stacking method of chips |
| CN116435290B (en) * | 2023-06-13 | 2023-08-22 | 中诚华隆计算机技术有限公司 | Three-dimensional stacking structure and stacking method of chips |
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| Publication number | Publication date |
|---|---|
| CN107658263B (en) | 2021-01-22 |
| WO2019061926A1 (en) | 2019-04-04 |
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