CN107658264A - A kind of vertical interconnected method of three-dimensional silicon hole based on multi-layer graphene auxiliary layer - Google Patents
A kind of vertical interconnected method of three-dimensional silicon hole based on multi-layer graphene auxiliary layer Download PDFInfo
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- CN107658264A CN107658264A CN201710901161.1A CN201710901161A CN107658264A CN 107658264 A CN107658264 A CN 107658264A CN 201710901161 A CN201710901161 A CN 201710901161A CN 107658264 A CN107658264 A CN 107658264A
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- silicon hole
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- auxiliary layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
Abstract
The invention discloses a kind of vertical interconnected method of three-dimensional silicon hole based on multi-layer graphene auxiliary layer, silicon hole is made on a silicon substrate；In silicon substrate surface and silicon hole inwall depositing insulating layer；Barrier layer is deposited on the insulating layer；Multi-layer graphene auxiliary layer is formed on barrier layer surface；Dry film is pasted on multi-layer graphene auxiliary layer on silicon substrate surface, is then exposed, developing forms photopolymer layer；The deposited seed layer on silicon hole bottom surface and dry film layer surface；Conductive material is filled in silicon hole.Perforate on a silicon substrate of the invention and then priority depositing insulating layer, barrier layer, form multi-layer graphene auxiliary layer, paste dry film, conductive material is filled after deposited seed layer, using the good electric property of grapheme material, to solve the TSV resistance values as caused by Kelvin effect and atomic migration etc. and power consumption increase problem, graphene and copper are as TSV signal transmission passages, the electrical property and reliability of 3D TSV structures are improved, improves under new technology node TSV vertically interconnections and the problems such as envelope eapsulotomy.
Description
Technical field
The present invention relates to a kind of vertical interconnected method of silicon hole, and in particular to it is a kind of based on multi-layer graphene auxiliary layer three
The vertical interconnected method of silicon hole is tieed up, belongs to microelectronic packaging technology field.
Background technology
With the continuous improvement of integrated circuit (IC, Integrated Circuit) chip performance demand, as function enhancing,
Size reduction, energy consumption and cost reduction etc., microelectronic packaging technology is faced with new challenges.In order to meet the requirement of IC products, three
Dimension encapsulation technology is arisen at the historic moment.It makes full use of z director spaces, greatly reduces interconnection length, improves packaging density, reduces
Power consumption, chip functions integrated level are higher.Silicon hole vertically interconnects (TSV, Through Silicon Via) technology and passed through in crystalline substance
Circle or chip internal make vertical channel, by filling metal in hole, realize that multilayer planar device interconnects in z-axis direction signal
Technology.TSV technology receives the widely studied of industry because of its distinct process characteristic.
The packing material of silicon hole is generally the materials such as copper Cu, tungsten W, polysilicon and conducting resinl, and wherein copper Cu is good because of its
Electrical and thermal conductivity performance, turn into the first choices of TSV packing materials.3D-TSV perpendicular interconnections, reduce signal transmission distance and delay
Time, make working frequency more and more faster, as TSV depth-to-width ratios gradually increase, when high frequency electric is by interconnection Cu lines, electric current collection
In in " skin " part of conductor, closer to conductive surface, current density is bigger, and actually electric current is smaller inside wire, as a result
Increase the resistance of conductor, power consumption increase.Meanwhile electric current distribution is uneven in copper cash, local current densities gradient is spent
Greatly, cause copper atom to be produced migration by electronics wind-force, form cavity, finally make circuit breaker, it is ineffectiveness caused by electromigration to ask
Topic is also more obvious.
The content of the invention
In view of the above-mentioned problems of the prior art, the present invention provides a kind of three-dimensional silica based on multi-layer graphene auxiliary layer
The vertical interconnected method of through hole, using the good electric property of grapheme material, to solve to be drawn by Kelvin effect and atomic migration etc.
TSV resistance values and power consumption the increase problem risen, improve the electrical property and reliability of 3D-TSV structures.
To achieve these goals, the technical solution adopted by the present invention is：It is a kind of based on multi-layer graphene auxiliary layer three
The vertical interconnected method of silicon hole is tieed up, is comprised the following steps：
A. silicon hole is made on a silicon substrate；
B. in silicon substrate surface and silicon hole inwall depositing insulating layer；
C. barrier layer is deposited on the insulating layer；
D. multi-layer graphene auxiliary layer is formed on barrier layer surface；
E. dry film is pasted on the multi-layer graphene auxiliary layer on silicon substrate surface, then exposed, developing forms photopolymer layer；
F. the deposited seed layer on silicon hole bottom surface and dry film layer surface；
G. conductive material is filled in silicon hole.
Further, the making of silicon hole uses deep reaction ion etching, laser ablation or wet etching method in the step a
Etching.
Further, the insulating barrier deposited in the step b is sunk using thermal oxide, chemical vapor deposition or physical vapor
Product method makes, and material is silica, aluminum oxide, polyimides, Parylene or photoresist.
Further, the barrier layer deposited in the step c uses physical vapor deposition, atomic layer deposition or chemical gaseous phase
Deposition process makes, and material is titanium, titanium nitride, tantalum, tantalum nitride etc..
Further, multi-layer graphene is prepared using oxidation-reduction method in step d, and graphene oxide is used into wet processing
Multi-layer graphene auxiliary layer is formed coated on barrier layer, then by reduction, CVD techniques growth multi-layer graphene can also be utilized to make
For auxiliary layer.
Further, Seed Layer uses physical vapor deposition, atomic layer deposition or chemical vapor deposition in the step f
Method makes, and material can be gold or copper.
Further, the bore dia of photopolymer layer is less than silicon hole diameter in the step e and the hole of photopolymer layer and silicon hole are coaxial.
Further, it is that guiding fills conductive material to carrying out plating in silicon hole using Seed Layer in the step g.
Perforate on a silicon substrate of the invention and then priority depositing insulating layer, barrier layer compared with prior art, form multilayer
Graphene auxiliary layer, pastes dry film, fills conductive material after deposited seed layer, using graphene and copper as TSV signal transmission passages,
Using the good electric property of grapheme material, solve the TSV track resistance values as caused by Kelvin effect and atomic migration etc. and
Power consumption increases problem, improves the electrical property and reliability of 3D-TSV structures, improves the signal that TSV is vertically interconnected under high frequency condition
The problems such as fidelity transmits.
Brief description of the drawings
Fig. 1 is the structural representation that the present invention makes silicon hole；
Fig. 2 is priority depositing insulating layer of the present invention and the structural representation on barrier layer；
Fig. 3 is the structural representation that the present invention forms multi-layer graphene auxiliary layer；
Fig. 4 is the structural representation of present invention patch dry film；
Fig. 5 is deposited seed layer of the present invention and fills the structural representation of conductive material.
Fig. 6 is the multi-layer graphene additional conductive schematic diagram that the present invention is formed；
In figure：1st, silicon chip, 2, insulating barrier, 3, barrier layer, 4, multi-layer graphene auxiliary layer, 5, photopolymer layer, 6, Seed Layer,
7th, conductive material, 8, silicon hole.
Embodiment
The invention will be further described below in conjunction with the accompanying drawings.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
As shown in figure 5, the present invention comprises the following steps：
A. silicon hole 8 is made on silicon chip 1；
B. in the surface of silicon chip 1 and the inwall depositing insulating layer 2 of silicon hole 8；
C. barrier layer 3 is deposited on insulating barrier 2；
D. multi-layer graphene auxiliary layer 4 is formed on the surface of barrier layer 3；
E. dry film is pasted on the multi-layer graphene auxiliary layer 4 on the surface of silicon chip 1, then exposed, developing forms photopolymer layer
5；
F. the deposited seed layer 6 on the bottom surface of silicon hole 8 and the surface of photopolymer layer 5；
G. the filling conductive material 7 in silicon hole 8.
Embodiment：
As shown in figure 1, made on silicon chip 1 using deep reaction ion etching, laser ablation or wet etching method etching
Silicon hole 8；A diameter of 1 micron to 100 microns of silicon hole 8, the cross section of silicon hole 8 is generally circular in cross section, and the depth-to-width ratio of silicon hole 8 is generally
1~30.
As shown in Fig. 2 on the surface of silicon chip 1 and the inwall of silicon hole 8 (periphery and bottom surface) depositing insulating layer 2, insulating barrier 2
Deposition made using thermal oxide, chemical vapor deposition or physical gas-phase deposite method, the material of insulating barrier 2 can select two
Silica, aluminum oxide etc., polyimides, Parylene etc., the thickness of insulating barrier 2 is 0.5~1 micron；Sunk on insulating barrier 2
Product barrier layer 3, barrier layer 3 is using magnetron sputtering, physical vapor deposition, atomic layer deposition or chemical vapor deposition the methods of system
Make, the material on barrier layer 3 can select titanium, titanium nitride, tantalum, tantalum nitride etc., and the thickness on barrier layer 3 is 50~100 nanometers；
As shown in figure 3, multi-layer graphene auxiliary layer 4 is formed on the surface of barrier layer 3；The preparation of graphene is gone back using oxidation
Former method, graphite powder are reacted to form graphene oxide, are then rotated graphene oxide using wet processing with strong oxidizer
Multi-layer graphene auxiliary layer 4 is obtained coated in the surface of barrier layer 3, then by reduction.
As shown in figure 4, dry film is pasted on multi-layer graphene auxiliary layer 4 on the surface of silicon chip 1, it is sudden and violent by exposing, developing
Expose the structure of silicon hole 8；Multilayer dry film is affixed on by the surface of silicon chip 1 using hot-press method, is exposed using litho machine, then will
Silicon chip 1 after exposure is positioned in developer solution, after removing part dry film, forms the photopolymer layer 5 for needing pattern, photopolymer layer 5
Bore dia is less than the diameter of silicon hole 8 and the hole of photopolymer layer 5 and silicon hole 8 are coaxial.
As shown in figure 5, the deposited seed layer 6 on the bottom surface of silicon hole 8 and the surface of photopolymer layer 5, and the filling conduction material in silicon hole 8
Material 7；Seed Layer 6 is for mask, using electron beam evaporation, magnetron sputtering, physical vapor deposition, atomic layer deposition with photopolymer layer 5
Or CVD method is deposited on the bottom surface of silicon hole 8 and the surface of photopolymer layer 5；The material of Seed Layer 6 be usually gold or
Copper；Conductive material 7 is filled to carrying out plating in silicon hole 8 for guiding with Seed Layer 6, filling in silicon hole 8 led using electro-plating method
Electric material 7, material are usually copper Cu.Inhibitor and accelerator are added in electroplate liquid, realize conductive material 7 " from bottom and on "
At a high speed, high quality is filled.
As shown in fig. 6, TSV channel bottoms are removed by cmp technology after the completion of filling and realize planarization.
When high frequency electric passes through packing material 7, electric current is intended to its surface, and multi-layer graphene reduces as conductive auxiliary layer
The resistance of signal transmission passage, avoid local current densities it is excessive formed atomic migration caused by it is empty, breaking the defects of.
It is obvious to a person skilled in the art that the invention is not restricted to the details of above-mentioned one exemplary embodiment, Er Qie
In the case of without departing substantially from spirit or essential attributes of the invention, the present invention can be realized in other specific forms.Therefore, no matter
From the point of view of which point, embodiment all should be regarded as exemplary, and be nonrestrictive, the scope of the present invention is by appended power
Profit requires rather than described above limits, it is intended that all in the implication and scope of the equivalency of claim by falling
Change is included in the present invention.Any reference in claim should not be considered as to the involved claim of limitation.
Described above, only presently preferred embodiments of the present invention is not intended to limit the invention, every skill according to the present invention
Any trickle amendment, equivalent substitution and the improvement that art is substantially made to above example, should be included in technical solution of the present invention
Protection domain within.
Claims (8)
1. a kind of vertical interconnected method of three-dimensional silicon hole based on multi-layer graphene auxiliary layer, it is characterised in that including following step
Suddenly：
A. silicon hole (8) is made on silicon chip (1)；
B. in silicon chip (1) surface and silicon hole (8) inwall depositing insulating layer (2)；
C. barrier layer (3) are deposited on insulating barrier (2)；
D. multi-layer graphene auxiliary layer (4) is formed on barrier layer (3) surface；
E. dry film is pasted on the multi-layer graphene auxiliary layer (4) on silicon chip (1) surface, then exposed, developing forms photopolymer layer
(5)；
F. the deposited seed layer (6) on silicon hole (8) bottom surface and photopolymer layer (5) surface；
G. the filling conductive material (7) in silicon hole (8).
2. a kind of vertical interconnected method of three-dimensional silicon hole based on multi-layer graphene auxiliary layer according to claim 1, its
It is characterised by, the making of silicon hole (8) is using deep reaction ion etching, laser ablation or wet etching method etching in the step a.
3. a kind of vertical interconnected method of three-dimensional silicon hole based on multi-layer graphene auxiliary layer according to claim 1, its
It is characterised by, the insulating barrier (2) deposited in the step b uses thermal oxide, chemical vapor deposition or physical vapour deposition (PVD) side
Method makes, and material is silica, aluminum oxide, polyimides, Parylene or photoresist.
4. a kind of vertical interconnected method of three-dimensional silicon hole based on multi-layer graphene auxiliary layer according to claim 1, its
It is characterised by, the barrier layer (3) deposited in the step c uses physical vapor deposition, atomic layer deposition or chemical vapor deposition
Method makes, and material is titanium, titanium nitride, tantalum, tantalum nitride.
5. a kind of vertical interconnected method of three-dimensional silicon hole based on multi-layer graphene auxiliary layer according to claim 1, its
It is characterised by, multi-layer graphene is prepared using oxidation-reduction method in the step d, and using wet processing in barrier layer (3) shape
Into multi-layer graphene auxiliary layer (4).
6. a kind of vertical interconnected method of three-dimensional silicon hole based on multi-layer graphene auxiliary layer according to claim 1, its
It is characterised by, Seed Layer (6) uses physical vapor deposition, atomic layer deposition or chemical gas-phase deposition method in the step f
Make, material can be gold or copper.
7. a kind of vertical interconnected method of three-dimensional silicon hole based on multi-layer graphene auxiliary layer according to claim 1, its
It is characterised by, the bore dia of photopolymer layer (5) is less than silicon hole (8) diameter in the step f.
8. a kind of vertical interconnected method of three-dimensional silicon hole based on multi-layer graphene auxiliary layer according to claim 1, its
It is characterised by, conductive material (7) is filled to carrying out plating in silicon hole (8) for guiding with Seed Layer (6) in the step g.
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| CN201710901161.1A CN107658264A (en) | 2017-09-28 | 2017-09-28 | A kind of vertical interconnected method of three-dimensional silicon hole based on multi-layer graphene auxiliary layer |
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| CN201710901161.1A CN107658264A (en) | 2017-09-28 | 2017-09-28 | A kind of vertical interconnected method of three-dimensional silicon hole based on multi-layer graphene auxiliary layer |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110379768A (en) * | 2019-07-23 | 2019-10-25 | 合肥工业大学 | A kind of TSV production method based on graphene filled therewith |
| CN112255526A (en) * | 2020-09-09 | 2021-01-22 | 北京航天控制仪器研究所 | Preparation method and test method of copper-filled silicon through hole electromigration test structure |
| CN113078131A (en) * | 2021-03-23 | 2021-07-06 | 浙江集迈科微电子有限公司 | TSV structure and TSV electroplating process |
| CN113506767A (en) * | 2021-06-16 | 2021-10-15 | 天津津航计算技术研究所 | TSV adapter plate manufacturing method |
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| CN110379768A (en) * | 2019-07-23 | 2019-10-25 | 合肥工业大学 | A kind of TSV production method based on graphene filled therewith |
| CN112255526A (en) * | 2020-09-09 | 2021-01-22 | 北京航天控制仪器研究所 | Preparation method and test method of copper-filled silicon through hole electromigration test structure |
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| CN113506767A (en) * | 2021-06-16 | 2021-10-15 | 天津津航计算技术研究所 | TSV adapter plate manufacturing method |
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Application publication date: 20180202 |